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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / mcusat / mcusat_reg_toggle_sample.vrhpal
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: mcusat_reg_toggle_sample.vrhpal
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35 wildcard state s_REG_CAS_AD_WIDTH (REG_CAS_AD_WIDTH);
36 wildcard state s_REG_RAS_AD_WIDTH13_4BNK (REG_RAS_AD_WIDTH13_4BNK);
37 wildcard state s_REG_RAS_AD_WIDTH14_4BNK (REG_RAS_AD_WIDTH14_4BNK);
38 wildcard state s_REG_RAS_AD_WIDTH14_8BNK (REG_RAS_AD_WIDTH14_8BNK);
39 wildcard state s_REG_RAS_AD_WIDTH15_8BNK (REG_RAS_AD_WIDTH15_8BNK);
40 wildcard state s_REG_STACK_PRES0 (REG_STACK_PRES0);
41 wildcard state s_REG_STACK_PRES1 (REG_STACK_PRES1);
42 wildcard state s_REG_CAS_LAT2 (REG_CAS_LAT2);
43 wildcard state s_REG_CAS_LAT3 (REG_CAS_LAT3);
44 wildcard state s_REG_CAS_LAT4 (REG_CAS_LAT4);
45 wildcard state s_REG_CAS_LAT5 (REG_CAS_LAT5);
46 wildcard state s_REG_RRD_REG2 (REG_RRD_REG2);
47 wildcard state s_REG_RRD_REG3 (REG_RRD_REG3);
48 wildcard state s_REG_RRD_REG4 (REG_RRD_REG4);
49 wildcard state s_REG_RRD_REG5 (REG_RRD_REG5);
50 wildcard state s_REG_RRD_REG6 (REG_RRD_REG6);
51 wildcard state s_REG_RRD_REG7 (REG_RRD_REG7);
52 wildcard state s_REG_RRD_REG8 (REG_RRD_REG8);
53 wildcard state s_REG_RRD_REG9 (REG_RRD_REG9);
54 wildcard state s_REG_RRD_REG10 (REG_RRD_REG10);
55 wildcard state s_REG_RRD_REG11 (REG_RRD_REG11);
56 wildcard state s_REG_RRD_REG12 (REG_RRD_REG12);
57 wildcard state s_REG_RRD_REG13 (REG_RRD_REG13);
58 wildcard state s_REG_RRD_REG14 (REG_RRD_REG14);
59 wildcard state s_REG_RRD_REG15 (REG_RRD_REG15);
60 wildcard state s_REG_RC_REG13 (REG_RC_REG13);
61 wildcard state s_REG_RC_REG14 (REG_RC_REG14);
62 wildcard state s_REG_RC_REG15 (REG_RC_REG15);
63 wildcard state s_REG_RCD_REG4 (REG_RCD_REG4);
64 wildcard state s_REG_RCD_REG5 (REG_RCD_REG5);
65 wildcard state s_REG_RCD_REG6 (REG_RCD_REG6);
66 wildcard state s_REG_RCD_REG7 (REG_RCD_REG7);
67 wildcard state s_REG_RCD_REG8 (REG_RCD_REG8);
68 wildcard state s_REG_RCD_REG9 (REG_RCD_REG9);
69 wildcard state s_REG_RCD_REG10 (REG_RCD_REG10);
70 wildcard state s_REG_RCD_REG11 (REG_RCD_REG11);
71 wildcard state s_REG_RCD_REG12 (REG_RCD_REG12);
72 wildcard state s_REG_RCD_REG13 (REG_RCD_REG13);
73 wildcard state s_REG_RCD_REG14 (REG_RCD_REG14);
74 wildcard state s_REG_RCD_REG15 (REG_RCD_REG15);
75 wildcard state s_REG_WTR_DLY1 (REG_WTR_DLY1);
76 wildcard state s_REG_WTR_DLY2 (REG_WTR_DLY2);
77 wildcard state s_REG_WTR_DLY3 (REG_WTR_DLY3);
78 wildcard state s_REG_WTR_DLY4 (REG_WTR_DLY4);
79 wildcard state s_REG_WTR_DLY5 (REG_WTR_DLY5);
80 wildcard state s_REG_WTR_DLY6 (REG_WTR_DLY6);
81 wildcard state s_REG_WTR_DLY7 (REG_WTR_DLY7);
82 wildcard state s_REG_WTR_DLY8 (REG_WTR_DLY8);
83 wildcard state s_REG_WTR_DLY9 (REG_WTR_DLY9);
84 wildcard state s_REG_WTR_DLY10 (REG_WTR_DLY10);
85 wildcard state s_REG_WTR_DLY11 (REG_WTR_DLY11);
86 wildcard state s_REG_WTR_DLY12 (REG_WTR_DLY12);
87 wildcard state s_REG_WTR_DLY13 (REG_WTR_DLY13);
88 wildcard state s_REG_WTR_DLY14 (REG_WTR_DLY14);
89 wildcard state s_REG_WTR_DLY15 (REG_WTR_DLY15);
90 wildcard state s_REG_RTW_DLY1 (REG_RTW_DLY1);
91 wildcard state s_REG_RTW_DLY2 (REG_RTW_DLY2);
92 wildcard state s_REG_RTW_DLY3 (REG_RTW_DLY3);
93 wildcard state s_REG_RTW_DLY4 (REG_RTW_DLY4);
94 wildcard state s_REG_RTW_DLY5 (REG_RTW_DLY5);
95 wildcard state s_REG_RTW_DLY6 (REG_RTW_DLY6);
96 wildcard state s_REG_RTW_DLY7 (REG_RTW_DLY7);
97 wildcard state s_REG_RTW_DLY8 (REG_RTW_DLY8);
98 wildcard state s_REG_RTW_DLY9 (REG_RTW_DLY9);
99 wildcard state s_REG_RTW_DLY10 (REG_RTW_DLY10);
100 wildcard state s_REG_RTW_DLY11 (REG_RTW_DLY11);
101 wildcard state s_REG_RTW_DLY12 (REG_RTW_DLY12);
102 wildcard state s_REG_RTW_DLY13 (REG_RTW_DLY13);
103 wildcard state s_REG_RTW_DLY14 (REG_RTW_DLY14);
104 wildcard state s_REG_RTW_DLY15 (REG_RTW_DLY15);
105 wildcard state s_REG_RTR_REG2 (REG_RTR_REG2);
106 wildcard state s_REG_RTR_REG3 (REG_RTR_REG3);
107 wildcard state s_REG_RTR_REG4 (REG_RTR_REG4);
108 wildcard state s_REG_RTR_REG5 (REG_RTR_REG5);
109 wildcard state s_REG_RTR_REG6 (REG_RTR_REG6);
110 wildcard state s_REG_RTR_REG7 (REG_RTR_REG7);
111 // this register is 3 bits now so we dont need these
112 //wildcard state s_REG_RTR_REG8 (REG_RTR_REG8);
113 //wildcard state s_REG_RTR_REG9 (REG_RTR_REG9);
114 //wildcard state s_REG_RTR_REG10 (REG_RTR_REG10);
115 //wildcard state s_REG_RTR_REG11 (REG_RTR_REG11);
116 //wildcard state s_REG_RTR_REG12 (REG_RTR_REG12);
117 //wildcard state s_REG_RTR_REG13 (REG_RTR_REG13);
118 //wildcard state s_REG_RTR_REG14 (REG_RTR_REG14);
119 //wildcard state s_REG_RTR_REG15 (REG_RTR_REG15);
120 wildcard state s_REG_WTW_REG2 (REG_WTW_REG2);
121 wildcard state s_REG_WTW_REG3 (REG_WTW_REG3);
122 wildcard state s_REG_WTW_REG4 (REG_WTW_REG4);
123 wildcard state s_REG_WTW_REG5 (REG_WTW_REG5);
124 wildcard state s_REG_WTW_REG6 (REG_WTW_REG6);
125 wildcard state s_REG_WTW_REG7 (REG_WTW_REG7);
126 wildcard state s_REG_WTW_REG8 (REG_WTW_REG8);
127 wildcard state s_REG_WTW_REG9 (REG_WTW_REG9);
128 wildcard state s_REG_WTW_REG10 (REG_WTW_REG10);
129 wildcard state s_REG_WTW_REG11 (REG_WTW_REG11);
130 wildcard state s_REG_WTW_REG12 (REG_WTW_REG12);
131 wildcard state s_REG_WTW_REG13 (REG_WTW_REG13);
132 wildcard state s_REG_WTW_REG14 (REG_WTW_REG14);
133 wildcard state s_REG_WTW_REG15 (REG_WTW_REG15);
134 wildcard state s_REG_RP_REG4 (REG_RP_REG4);
135 wildcard state s_REG_RP_REG5 (REG_RP_REG5);
136 wildcard state s_REG_RP_REG6 (REG_RP_REG6);
137 wildcard state s_REG_RP_REG7 (REG_RP_REG7);
138 wildcard state s_REG_RP_REG8 (REG_RP_REG8);
139 wildcard state s_REG_RP_REG9 (REG_RP_REG9);
140 wildcard state s_REG_RP_REG10 (REG_RP_REG10);
141 wildcard state s_REG_RP_REG11 (REG_RP_REG11);
142 wildcard state s_REG_RP_REG12 (REG_RP_REG12);
143 wildcard state s_REG_RP_REG13 (REG_RP_REG13);
144 wildcard state s_REG_RP_REG14 (REG_RP_REG14);
145 wildcard state s_REG_RP_REG15 (REG_RP_REG15);
146 wildcard state s_REG_WR_REG3 (REG_WR_REG3);
147 wildcard state s_REG_WR_REG4 (REG_WR_REG4);
148 wildcard state s_REG_WR_REG5 (REG_WR_REG5);
149 wildcard state s_REG_WR_REG6 (REG_WR_REG6);
150 wildcard state s_REG_WR_REG7 (REG_WR_REG7);
151 wildcard state s_REG_WR_REG8 (REG_WR_REG8);
152 wildcard state s_REG_WR_REG9 (REG_WR_REG9);
153 wildcard state s_REG_WR_REG10 (REG_WR_REG10);
154 wildcard state s_REG_WR_REG11 (REG_WR_REG11);
155 wildcard state s_REG_WR_REG12 (REG_WR_REG12);
156 wildcard state s_REG_WR_REG13 (REG_WR_REG13);
157 wildcard state s_REG_WR_REG14 (REG_WR_REG14);
158 wildcard state s_REG_WR_REG15 (REG_WR_REG15);
159 wildcard state s_REG_MRD_REG2 (REG_MRD_REG2);
160 wildcard state s_REG_MRD_REG3 (REG_MRD_REG3);
161 wildcard state s_REG_IWTR_REG2 (REG_IWTR_REG2);
162 wildcard state s_REG_IWTR_REG3 (REG_IWTR_REG3);
163 wildcard state s_REG_RANK_PRES0 (REG_RANK_PRES0);
164 wildcard state s_REG_RANK_PRES1 (REG_RANK_PRES1);
165 wildcard state s_REG_CHANNEL_DISABLE0 (REG_CHANNEL_DISABLE0);
166 wildcard state s_REG_CHANNEL_DISABLE1 (REG_CHANNEL_DISABLE1);
167 wildcard state s_REG_LOW_AD_SEL0 (REG_LOW_AD_SEL0);
168 wildcard state s_REG_LOW_AD_SEL1 (REG_LOW_AD_SEL1);
169 wildcard state s_REG_QUE_INIT0 (REG_QUE_INIT0 );
170 wildcard state s_REG_QUE_INIT1 (REG_QUE_INIT1 );
171 wildcard state s_REG_DEL_CNT_UP_BIT_ENB0 (REG_DEL_CNT_UP_BIT_ENB0 );
172 wildcard state s_REG_DEL_CNT_UP_BIT_ENB1 (REG_DEL_CNT_UP_BIT_ENB1 );
173 wildcard state s_REG_DEL_CNT0 (REG_DEL_CNT0 );
174 wildcard state s_REG_DEL_CNT1 (REG_DEL_CNT1 );
175 wildcard state s_REG_DEL_CNT2 (REG_DEL_CNT2 );
176 wildcard state s_REG_DEL_CNT3 (REG_DEL_CNT3 );
177 wildcard state s_REG_DEL_CNT4 (REG_DEL_CNT4 );
178 wildcard state s_REG_DEL_CNT5 (REG_DEL_CNT5 );
179 wildcard state s_REG_DEL_CNT6 (REG_DEL_CNT6 );
180 wildcard state s_REG_DEL_CNT7 (REG_DEL_CNT7 );
181 wildcard state s_REG_IO_PAD_CLK_INV0 (REG_IO_PAD_CLK_INV0 );
182 wildcard state s_REG_IO_PAD_CLK_INV1 (REG_IO_PAD_CLK_INV1 );
183 wildcard state s_REG_IO_PTR_CLK_INV0 (REG_IO_PTR_CLK_INV0 );
184 wildcard state s_REG_IO_PTR_CLK_INV1 (REG_IO_PTR_CLK_INV1 );
185 wildcard state s_REG_IO_PTR_CLK_INV2 (REG_IO_PTR_CLK_INV2 );
186 wildcard state s_REG_IO_PTR_CLK_INV3 (REG_IO_PTR_CLK_INV3 );
187 wildcard state s_REG_WR_MODE_REG_DONE0 (REG_WR_MODE_REG_DONE0 );
188 wildcard state s_REG_WR_MODE_REG_DONE1 (REG_WR_MODE_REG_DONE1 );
189 wildcard state s_REG_INIT_STATUS0 (REG_INIT_STATUS0 );
190 wildcard state s_REG_INIT_STATUS1 (REG_INIT_STATUS1 );
191 //wildcard state s_REG_DIMMS_PRES1 (REG_DIMMS_PRES1 );
192 wildcard state s_REG_DIMMS_PRES3 (REG_DIMMS_PRES3 );
193 wildcard state s_REG_DIMMS_PRESf (REG_DIMMS_PRESf );
194 wildcard state s_REG_FAIL_OVER_MODE0 (REG_FAIL_OVER_MODE0 );
195 wildcard state s_REG_FAIL_OVER_MODE1 (REG_FAIL_OVER_MODE1 );
196 wildcard state s_REG_FAIL_OVER_MASK0 (REG_FAIL_OVER_MASK0 );
197 wildcard state s_REG_FAIL_OVER_MASK1 (REG_FAIL_OVER_MASK1 );
198 wildcard state s_REG_FAIL_OVER_MASK2 (REG_FAIL_OVER_MASK2 );
199 wildcard state s_REG_FAIL_OVER_MASK3 (REG_FAIL_OVER_MASK3 );
200 wildcard state s_REG_FAIL_OVER_MASK4 (REG_FAIL_OVER_MASK4 );
201 wildcard state s_REG_FAIL_OVER_MASK5 (REG_FAIL_OVER_MASK5 );
202 wildcard state s_REG_FAIL_OVER_MASK6 (REG_FAIL_OVER_MASK6 );
203 wildcard state s_REG_FAIL_OVER_MASK7 (REG_FAIL_OVER_MASK7 );
204 wildcard state s_REG_FAIL_OVER_MASK8 (REG_FAIL_OVER_MASK8 );
205 wildcard state s_REG_FAIL_OVER_MASK9 (REG_FAIL_OVER_MASK9 );
206 wildcard state s_REG_FAIL_OVER_MASK10 (REG_FAIL_OVER_MASK10 );
207 wildcard state s_REG_FAIL_OVER_MASK11 (REG_FAIL_OVER_MASK11 );
208 wildcard state s_REG_FAIL_OVER_MASK12 (REG_FAIL_OVER_MASK12 );
209 wildcard state s_REG_FAIL_OVER_MASK13 (REG_FAIL_OVER_MASK13 );
210 wildcard state s_REG_FAIL_OVER_MASK14 (REG_FAIL_OVER_MASK14 );
211 wildcard state s_REG_FAIL_OVER_MASK15 (REG_FAIL_OVER_MASK15 );
212 wildcard state s_REG_FAIL_OVER_MASK16 (REG_FAIL_OVER_MASK16 );
213 wildcard state s_REG_FAIL_OVER_MASK17 (REG_FAIL_OVER_MASK17 );
214 wildcard state s_REG_FAIL_OVER_MASK18 (REG_FAIL_OVER_MASK18 );
215 wildcard state s_REG_FAIL_OVER_MASK19 (REG_FAIL_OVER_MASK19 );
216 wildcard state s_REG_FAIL_OVER_MASK20 (REG_FAIL_OVER_MASK20 );
217 wildcard state s_REG_FAIL_OVER_MASK21 (REG_FAIL_OVER_MASK21 );
218 wildcard state s_REG_FAIL_OVER_MASK22 (REG_FAIL_OVER_MASK22 );
219 wildcard state s_REG_FAIL_OVER_MASK23 (REG_FAIL_OVER_MASK23 );
220 wildcard state s_REG_FAIL_OVER_MASK24 (REG_FAIL_OVER_MASK24 );
221 wildcard state s_REG_FAIL_OVER_MASK25 (REG_FAIL_OVER_MASK25 );
222 wildcard state s_REG_FAIL_OVER_MASK26 (REG_FAIL_OVER_MASK26 );
223 wildcard state s_REG_FAIL_OVER_MASK27 (REG_FAIL_OVER_MASK27 );
224 wildcard state s_REG_FAIL_OVER_MASK28 (REG_FAIL_OVER_MASK28 );
225 wildcard state s_REG_FAIL_OVER_MASK29 (REG_FAIL_OVER_MASK29 );
226 wildcard state s_REG_FAIL_OVER_MASK30 (REG_FAIL_OVER_MASK30 );
227 wildcard state s_REG_FAIL_OVER_MASK31 (REG_FAIL_OVER_MASK31 );
228 wildcard state s_REG_DBG_TRIG_EN0 (REG_DBG_TRIG_EN0 );
229 wildcard state s_REG_DBG_TRIG_EN1 (REG_DBG_TRIG_EN1 );
230 wildcard state s_REG_ERR_STS_22_0 (REG_ERR_STS_22_0 );
231 wildcard state s_REG_ERR_STS_22_1 (REG_ERR_STS_22_1 );
232 wildcard state s_REG_ERR_STS_21_0 (REG_ERR_STS_21_0 );
233 wildcard state s_REG_ERR_STS_21_1 (REG_ERR_STS_21_1 );
234 wildcard state s_REG_ERR_STS_20_0 (REG_ERR_STS_20_0 );
235 wildcard state s_REG_ERR_STS_20_1 (REG_ERR_STS_20_1 );
236 wildcard state s_REG_ERR_STS_19_0 (REG_ERR_STS_19_0 );
237 wildcard state s_REG_ERR_STS_19_1 (REG_ERR_STS_19_1 );
238 wildcard state s_REG_ERR_STS_18_0 (REG_ERR_STS_18_0 );
239 wildcard state s_REG_ERR_STS_18_1 (REG_ERR_STS_18_1 );
240 wildcard state s_REG_ERR_STS_17_0 (REG_ERR_STS_17_0 );
241 wildcard state s_REG_ERR_STS_17_1 (REG_ERR_STS_17_1 );
242 wildcard state s_REG_ERR_STS_16_0 (REG_ERR_STS_16_0 );
243 wildcard state s_REG_ERR_STS_16_1 (REG_ERR_STS_16_1 );
244 wildcard state s_REG_ERR_INJ0 (REG_ERR_INJ0 );
245 wildcard state s_REG_ERR_INJ1 (REG_ERR_INJ1 );
246 wildcard state s_REG_SSHOT_ERR0 (REG_SSHOT_ERR0 );
247 wildcard state s_REG_SSHOT_ERR1 (REG_SSHOT_ERR1 );
248 wildcard state s_REG_ERR_INT_ENB0 (REG_ERR_INT_ENB0 );
249 wildcard state s_REG_ERR_INT_ENB1 (REG_ERR_INT_ENB1 );
250 wildcard state s_REG_ERR_CNT_VAL0 (REG_ERR_CNT_VAL0 );
251 wildcard state s_REG_ERR_CNT_VAL1 (REG_ERR_CNT_VAL1 );
252 wildcard state s_REG_E_MODE1_A0_0 (REG_E_MODE1_A0_0);
253 wildcard state s_REG_E_MODE1_A0_1 (REG_E_MODE1_A0_1);
254 wildcard state s_REG_E_MODE1_A1_0 (REG_E_MODE1_A1_0);
255 wildcard state s_REG_E_MODE1_A1_1 (REG_E_MODE1_A1_1);
256 wildcard state s_REG_E_MODE1_A5to3_0 (REG_E_MODE1_A5to3_0);
257 wildcard state s_REG_E_MODE1_A5to3_1 (REG_E_MODE1_A5to3_1);
258 wildcard state s_REG_E_MODE1_A5to3_2 (REG_E_MODE1_A5to3_2);
259 wildcard state s_REG_E_MODE1_A5to3_3 (REG_E_MODE1_A5to3_3);
260 wildcard state s_REG_E_MODE1_A5to3_4 (REG_E_MODE1_A5to3_4);
261 wildcard state s_REG_E_MODE1_A6n2_0 (REG_E_MODE1_A6n2_0);
262 wildcard state s_REG_E_MODE1_A6n2_1 (REG_E_MODE1_A6n2_1);
263 wildcard state s_REG_E_MODE1_A6n2_2 (REG_E_MODE1_A6n2_2);
264 wildcard state s_REG_E_MODE1_A9to7_0 (REG_E_MODE1_A9to7_0);
265 wildcard state s_REG_E_MODE1_A9to7_1 (REG_E_MODE1_A9to7_1);
266 wildcard state s_REG_E_MODE1_A9to7_2 (REG_E_MODE1_A9to7_2);
267 wildcard state s_REG_E_MODE1_A9to7_4 (REG_E_MODE1_A9to7_4);
268 wildcard state s_REG_E_MODE1_A9to7_7 (REG_E_MODE1_A9to7_7);
269 wildcard state s_REG_E_MODE1_A11to10_0 (REG_E_MODE1_A11to10_0);
270 wildcard state s_REG_E_MODE1_A11to10_1 (REG_E_MODE1_A11to10_1);
271 wildcard state s_REG_E_MODE1_A11to10_2 (REG_E_MODE1_A11to10_2);
272 wildcard state s_REG_E_MODE1_A11to10_3 (REG_E_MODE1_A11to10_3);
273 wildcard state s_REG_E_MODE1_A12_0 (REG_E_MODE1_A12_0);
274 wildcard state s_REG_E_MODE1_A12_1 (REG_E_MODE1_A12_1);
275
276 // bad states
277 //bad_state s_not_rd_sync0 (not state);
278
279 // bad transitions
280 //bad_trans t_not_rd_sync0 (not trans);
281 //bad_trans t_rd_bad_sync1_3 (2'b01 -> 2'b11);
282
283//}
284
Full OpenSPARC design & verification tarball including full HDL.