// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: mcusat_reg_toggle_sample.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
wildcard state s_REG_CAS_AD_WIDTH (REG_CAS_AD_WIDTH);
wildcard state s_REG_RAS_AD_WIDTH13_4BNK (REG_RAS_AD_WIDTH13_4BNK);
wildcard state s_REG_RAS_AD_WIDTH14_4BNK (REG_RAS_AD_WIDTH14_4BNK);
wildcard state s_REG_RAS_AD_WIDTH14_8BNK (REG_RAS_AD_WIDTH14_8BNK);
wildcard state s_REG_RAS_AD_WIDTH15_8BNK (REG_RAS_AD_WIDTH15_8BNK);
wildcard state s_REG_STACK_PRES0 (REG_STACK_PRES0);
wildcard state s_REG_STACK_PRES1 (REG_STACK_PRES1);
wildcard state s_REG_CAS_LAT2 (REG_CAS_LAT2);
wildcard state s_REG_CAS_LAT3 (REG_CAS_LAT3);
wildcard state s_REG_CAS_LAT4 (REG_CAS_LAT4);
wildcard state s_REG_CAS_LAT5 (REG_CAS_LAT5);
wildcard state s_REG_RRD_REG2 (REG_RRD_REG2);
wildcard state s_REG_RRD_REG3 (REG_RRD_REG3);
wildcard state s_REG_RRD_REG4 (REG_RRD_REG4);
wildcard state s_REG_RRD_REG5 (REG_RRD_REG5);
wildcard state s_REG_RRD_REG6 (REG_RRD_REG6);
wildcard state s_REG_RRD_REG7 (REG_RRD_REG7);
wildcard state s_REG_RRD_REG8 (REG_RRD_REG8);
wildcard state s_REG_RRD_REG9 (REG_RRD_REG9);
wildcard state s_REG_RRD_REG10 (REG_RRD_REG10);
wildcard state s_REG_RRD_REG11 (REG_RRD_REG11);
wildcard state s_REG_RRD_REG12 (REG_RRD_REG12);
wildcard state s_REG_RRD_REG13 (REG_RRD_REG13);
wildcard state s_REG_RRD_REG14 (REG_RRD_REG14);
wildcard state s_REG_RRD_REG15 (REG_RRD_REG15);
wildcard state s_REG_RC_REG13 (REG_RC_REG13);
wildcard state s_REG_RC_REG14 (REG_RC_REG14);
wildcard state s_REG_RC_REG15 (REG_RC_REG15);
wildcard state s_REG_RCD_REG4 (REG_RCD_REG4);
wildcard state s_REG_RCD_REG5 (REG_RCD_REG5);
wildcard state s_REG_RCD_REG6 (REG_RCD_REG6);
wildcard state s_REG_RCD_REG7 (REG_RCD_REG7);
wildcard state s_REG_RCD_REG8 (REG_RCD_REG8);
wildcard state s_REG_RCD_REG9 (REG_RCD_REG9);
wildcard state s_REG_RCD_REG10 (REG_RCD_REG10);
wildcard state s_REG_RCD_REG11 (REG_RCD_REG11);
wildcard state s_REG_RCD_REG12 (REG_RCD_REG12);
wildcard state s_REG_RCD_REG13 (REG_RCD_REG13);
wildcard state s_REG_RCD_REG14 (REG_RCD_REG14);
wildcard state s_REG_RCD_REG15 (REG_RCD_REG15);
wildcard state s_REG_WTR_DLY1 (REG_WTR_DLY1);
wildcard state s_REG_WTR_DLY2 (REG_WTR_DLY2);
wildcard state s_REG_WTR_DLY3 (REG_WTR_DLY3);
wildcard state s_REG_WTR_DLY4 (REG_WTR_DLY4);
wildcard state s_REG_WTR_DLY5 (REG_WTR_DLY5);
wildcard state s_REG_WTR_DLY6 (REG_WTR_DLY6);
wildcard state s_REG_WTR_DLY7 (REG_WTR_DLY7);
wildcard state s_REG_WTR_DLY8 (REG_WTR_DLY8);
wildcard state s_REG_WTR_DLY9 (REG_WTR_DLY9);
wildcard state s_REG_WTR_DLY10 (REG_WTR_DLY10);
wildcard state s_REG_WTR_DLY11 (REG_WTR_DLY11);
wildcard state s_REG_WTR_DLY12 (REG_WTR_DLY12);
wildcard state s_REG_WTR_DLY13 (REG_WTR_DLY13);
wildcard state s_REG_WTR_DLY14 (REG_WTR_DLY14);
wildcard state s_REG_WTR_DLY15 (REG_WTR_DLY15);
wildcard state s_REG_RTW_DLY1 (REG_RTW_DLY1);
wildcard state s_REG_RTW_DLY2 (REG_RTW_DLY2);
wildcard state s_REG_RTW_DLY3 (REG_RTW_DLY3);
wildcard state s_REG_RTW_DLY4 (REG_RTW_DLY4);
wildcard state s_REG_RTW_DLY5 (REG_RTW_DLY5);
wildcard state s_REG_RTW_DLY6 (REG_RTW_DLY6);
wildcard state s_REG_RTW_DLY7 (REG_RTW_DLY7);
wildcard state s_REG_RTW_DLY8 (REG_RTW_DLY8);
wildcard state s_REG_RTW_DLY9 (REG_RTW_DLY9);
wildcard state s_REG_RTW_DLY10 (REG_RTW_DLY10);
wildcard state s_REG_RTW_DLY11 (REG_RTW_DLY11);
wildcard state s_REG_RTW_DLY12 (REG_RTW_DLY12);
wildcard state s_REG_RTW_DLY13 (REG_RTW_DLY13);
wildcard state s_REG_RTW_DLY14 (REG_RTW_DLY14);
wildcard state s_REG_RTW_DLY15 (REG_RTW_DLY15);
wildcard state s_REG_RTR_REG2 (REG_RTR_REG2);
wildcard state s_REG_RTR_REG3 (REG_RTR_REG3);
wildcard state s_REG_RTR_REG4 (REG_RTR_REG4);
wildcard state s_REG_RTR_REG5 (REG_RTR_REG5);
wildcard state s_REG_RTR_REG6 (REG_RTR_REG6);
wildcard state s_REG_RTR_REG7 (REG_RTR_REG7);
// this register is 3 bits now so we dont need these
//wildcard state s_REG_RTR_REG8 (REG_RTR_REG8);
//wildcard state s_REG_RTR_REG9 (REG_RTR_REG9);
//wildcard state s_REG_RTR_REG10 (REG_RTR_REG10);
//wildcard state s_REG_RTR_REG11 (REG_RTR_REG11);
//wildcard state s_REG_RTR_REG12 (REG_RTR_REG12);
//wildcard state s_REG_RTR_REG13 (REG_RTR_REG13);
//wildcard state s_REG_RTR_REG14 (REG_RTR_REG14);
//wildcard state s_REG_RTR_REG15 (REG_RTR_REG15);
wildcard state s_REG_WTW_REG2 (REG_WTW_REG2);
wildcard state s_REG_WTW_REG3 (REG_WTW_REG3);
wildcard state s_REG_WTW_REG4 (REG_WTW_REG4);
wildcard state s_REG_WTW_REG5 (REG_WTW_REG5);
wildcard state s_REG_WTW_REG6 (REG_WTW_REG6);
wildcard state s_REG_WTW_REG7 (REG_WTW_REG7);
wildcard state s_REG_WTW_REG8 (REG_WTW_REG8);
wildcard state s_REG_WTW_REG9 (REG_WTW_REG9);
wildcard state s_REG_WTW_REG10 (REG_WTW_REG10);
wildcard state s_REG_WTW_REG11 (REG_WTW_REG11);
wildcard state s_REG_WTW_REG12 (REG_WTW_REG12);
wildcard state s_REG_WTW_REG13 (REG_WTW_REG13);
wildcard state s_REG_WTW_REG14 (REG_WTW_REG14);
wildcard state s_REG_WTW_REG15 (REG_WTW_REG15);
wildcard state s_REG_RP_REG4 (REG_RP_REG4);
wildcard state s_REG_RP_REG5 (REG_RP_REG5);
wildcard state s_REG_RP_REG6 (REG_RP_REG6);
wildcard state s_REG_RP_REG7 (REG_RP_REG7);
wildcard state s_REG_RP_REG8 (REG_RP_REG8);
wildcard state s_REG_RP_REG9 (REG_RP_REG9);
wildcard state s_REG_RP_REG10 (REG_RP_REG10);
wildcard state s_REG_RP_REG11 (REG_RP_REG11);
wildcard state s_REG_RP_REG12 (REG_RP_REG12);
wildcard state s_REG_RP_REG13 (REG_RP_REG13);
wildcard state s_REG_RP_REG14 (REG_RP_REG14);
wildcard state s_REG_RP_REG15 (REG_RP_REG15);
wildcard state s_REG_WR_REG3 (REG_WR_REG3);
wildcard state s_REG_WR_REG4 (REG_WR_REG4);
wildcard state s_REG_WR_REG5 (REG_WR_REG5);
wildcard state s_REG_WR_REG6 (REG_WR_REG6);
wildcard state s_REG_WR_REG7 (REG_WR_REG7);
wildcard state s_REG_WR_REG8 (REG_WR_REG8);
wildcard state s_REG_WR_REG9 (REG_WR_REG9);
wildcard state s_REG_WR_REG10 (REG_WR_REG10);
wildcard state s_REG_WR_REG11 (REG_WR_REG11);
wildcard state s_REG_WR_REG12 (REG_WR_REG12);
wildcard state s_REG_WR_REG13 (REG_WR_REG13);
wildcard state s_REG_WR_REG14 (REG_WR_REG14);
wildcard state s_REG_WR_REG15 (REG_WR_REG15);
wildcard state s_REG_MRD_REG2 (REG_MRD_REG2);
wildcard state s_REG_MRD_REG3 (REG_MRD_REG3);
wildcard state s_REG_IWTR_REG2 (REG_IWTR_REG2);
wildcard state s_REG_IWTR_REG3 (REG_IWTR_REG3);
wildcard state s_REG_RANK_PRES0 (REG_RANK_PRES0);
wildcard state s_REG_RANK_PRES1 (REG_RANK_PRES1);
wildcard state s_REG_CHANNEL_DISABLE0 (REG_CHANNEL_DISABLE0);
wildcard state s_REG_CHANNEL_DISABLE1 (REG_CHANNEL_DISABLE1);
wildcard state s_REG_LOW_AD_SEL0 (REG_LOW_AD_SEL0);
wildcard state s_REG_LOW_AD_SEL1 (REG_LOW_AD_SEL1);
wildcard state s_REG_QUE_INIT0 (REG_QUE_INIT0 );
wildcard state s_REG_QUE_INIT1 (REG_QUE_INIT1 );
wildcard state s_REG_DEL_CNT_UP_BIT_ENB0 (REG_DEL_CNT_UP_BIT_ENB0 );
wildcard state s_REG_DEL_CNT_UP_BIT_ENB1 (REG_DEL_CNT_UP_BIT_ENB1 );
wildcard state s_REG_DEL_CNT0 (REG_DEL_CNT0 );
wildcard state s_REG_DEL_CNT1 (REG_DEL_CNT1 );
wildcard state s_REG_DEL_CNT2 (REG_DEL_CNT2 );
wildcard state s_REG_DEL_CNT3 (REG_DEL_CNT3 );
wildcard state s_REG_DEL_CNT4 (REG_DEL_CNT4 );
wildcard state s_REG_DEL_CNT5 (REG_DEL_CNT5 );
wildcard state s_REG_DEL_CNT6 (REG_DEL_CNT6 );
wildcard state s_REG_DEL_CNT7 (REG_DEL_CNT7 );
wildcard state s_REG_IO_PAD_CLK_INV0 (REG_IO_PAD_CLK_INV0 );
wildcard state s_REG_IO_PAD_CLK_INV1 (REG_IO_PAD_CLK_INV1 );
wildcard state s_REG_IO_PTR_CLK_INV0 (REG_IO_PTR_CLK_INV0 );
wildcard state s_REG_IO_PTR_CLK_INV1 (REG_IO_PTR_CLK_INV1 );
wildcard state s_REG_IO_PTR_CLK_INV2 (REG_IO_PTR_CLK_INV2 );
wildcard state s_REG_IO_PTR_CLK_INV3 (REG_IO_PTR_CLK_INV3 );
wildcard state s_REG_WR_MODE_REG_DONE0 (REG_WR_MODE_REG_DONE0 );
wildcard state s_REG_WR_MODE_REG_DONE1 (REG_WR_MODE_REG_DONE1 );
wildcard state s_REG_INIT_STATUS0 (REG_INIT_STATUS0 );
wildcard state s_REG_INIT_STATUS1 (REG_INIT_STATUS1 );
//wildcard state s_REG_DIMMS_PRES1 (REG_DIMMS_PRES1 );
wildcard state s_REG_DIMMS_PRES3 (REG_DIMMS_PRES3 );
wildcard state s_REG_DIMMS_PRESf (REG_DIMMS_PRESf );
wildcard state s_REG_FAIL_OVER_MODE0 (REG_FAIL_OVER_MODE0 );
wildcard state s_REG_FAIL_OVER_MODE1 (REG_FAIL_OVER_MODE1 );
wildcard state s_REG_FAIL_OVER_MASK0 (REG_FAIL_OVER_MASK0 );
wildcard state s_REG_FAIL_OVER_MASK1 (REG_FAIL_OVER_MASK1 );
wildcard state s_REG_FAIL_OVER_MASK2 (REG_FAIL_OVER_MASK2 );
wildcard state s_REG_FAIL_OVER_MASK3 (REG_FAIL_OVER_MASK3 );
wildcard state s_REG_FAIL_OVER_MASK4 (REG_FAIL_OVER_MASK4 );
wildcard state s_REG_FAIL_OVER_MASK5 (REG_FAIL_OVER_MASK5 );
wildcard state s_REG_FAIL_OVER_MASK6 (REG_FAIL_OVER_MASK6 );
wildcard state s_REG_FAIL_OVER_MASK7 (REG_FAIL_OVER_MASK7 );
wildcard state s_REG_FAIL_OVER_MASK8 (REG_FAIL_OVER_MASK8 );
wildcard state s_REG_FAIL_OVER_MASK9 (REG_FAIL_OVER_MASK9 );
wildcard state s_REG_FAIL_OVER_MASK10 (REG_FAIL_OVER_MASK10 );
wildcard state s_REG_FAIL_OVER_MASK11 (REG_FAIL_OVER_MASK11 );
wildcard state s_REG_FAIL_OVER_MASK12 (REG_FAIL_OVER_MASK12 );
wildcard state s_REG_FAIL_OVER_MASK13 (REG_FAIL_OVER_MASK13 );
wildcard state s_REG_FAIL_OVER_MASK14 (REG_FAIL_OVER_MASK14 );
wildcard state s_REG_FAIL_OVER_MASK15 (REG_FAIL_OVER_MASK15 );
wildcard state s_REG_FAIL_OVER_MASK16 (REG_FAIL_OVER_MASK16 );
wildcard state s_REG_FAIL_OVER_MASK17 (REG_FAIL_OVER_MASK17 );
wildcard state s_REG_FAIL_OVER_MASK18 (REG_FAIL_OVER_MASK18 );
wildcard state s_REG_FAIL_OVER_MASK19 (REG_FAIL_OVER_MASK19 );
wildcard state s_REG_FAIL_OVER_MASK20 (REG_FAIL_OVER_MASK20 );
wildcard state s_REG_FAIL_OVER_MASK21 (REG_FAIL_OVER_MASK21 );
wildcard state s_REG_FAIL_OVER_MASK22 (REG_FAIL_OVER_MASK22 );
wildcard state s_REG_FAIL_OVER_MASK23 (REG_FAIL_OVER_MASK23 );
wildcard state s_REG_FAIL_OVER_MASK24 (REG_FAIL_OVER_MASK24 );
wildcard state s_REG_FAIL_OVER_MASK25 (REG_FAIL_OVER_MASK25 );
wildcard state s_REG_FAIL_OVER_MASK26 (REG_FAIL_OVER_MASK26 );
wildcard state s_REG_FAIL_OVER_MASK27 (REG_FAIL_OVER_MASK27 );
wildcard state s_REG_FAIL_OVER_MASK28 (REG_FAIL_OVER_MASK28 );
wildcard state s_REG_FAIL_OVER_MASK29 (REG_FAIL_OVER_MASK29 );
wildcard state s_REG_FAIL_OVER_MASK30 (REG_FAIL_OVER_MASK30 );
wildcard state s_REG_FAIL_OVER_MASK31 (REG_FAIL_OVER_MASK31 );
wildcard state s_REG_DBG_TRIG_EN0 (REG_DBG_TRIG_EN0 );
wildcard state s_REG_DBG_TRIG_EN1 (REG_DBG_TRIG_EN1 );
wildcard state s_REG_ERR_STS_22_0 (REG_ERR_STS_22_0 );
wildcard state s_REG_ERR_STS_22_1 (REG_ERR_STS_22_1 );
wildcard state s_REG_ERR_STS_21_0 (REG_ERR_STS_21_0 );
wildcard state s_REG_ERR_STS_21_1 (REG_ERR_STS_21_1 );
wildcard state s_REG_ERR_STS_20_0 (REG_ERR_STS_20_0 );
wildcard state s_REG_ERR_STS_20_1 (REG_ERR_STS_20_1 );
wildcard state s_REG_ERR_STS_19_0 (REG_ERR_STS_19_0 );
wildcard state s_REG_ERR_STS_19_1 (REG_ERR_STS_19_1 );
wildcard state s_REG_ERR_STS_18_0 (REG_ERR_STS_18_0 );
wildcard state s_REG_ERR_STS_18_1 (REG_ERR_STS_18_1 );
wildcard state s_REG_ERR_STS_17_0 (REG_ERR_STS_17_0 );
wildcard state s_REG_ERR_STS_17_1 (REG_ERR_STS_17_1 );
wildcard state s_REG_ERR_STS_16_0 (REG_ERR_STS_16_0 );
wildcard state s_REG_ERR_STS_16_1 (REG_ERR_STS_16_1 );
wildcard state s_REG_ERR_INJ0 (REG_ERR_INJ0 );
wildcard state s_REG_ERR_INJ1 (REG_ERR_INJ1 );
wildcard state s_REG_SSHOT_ERR0 (REG_SSHOT_ERR0 );
wildcard state s_REG_SSHOT_ERR1 (REG_SSHOT_ERR1 );
wildcard state s_REG_ERR_INT_ENB0 (REG_ERR_INT_ENB0 );
wildcard state s_REG_ERR_INT_ENB1 (REG_ERR_INT_ENB1 );
wildcard state s_REG_ERR_CNT_VAL0 (REG_ERR_CNT_VAL0 );
wildcard state s_REG_ERR_CNT_VAL1 (REG_ERR_CNT_VAL1 );
wildcard state s_REG_E_MODE1_A0_0 (REG_E_MODE1_A0_0);
wildcard state s_REG_E_MODE1_A0_1 (REG_E_MODE1_A0_1);
wildcard state s_REG_E_MODE1_A1_0 (REG_E_MODE1_A1_0);
wildcard state s_REG_E_MODE1_A1_1 (REG_E_MODE1_A1_1);
wildcard state s_REG_E_MODE1_A5to3_0 (REG_E_MODE1_A5to3_0);
wildcard state s_REG_E_MODE1_A5to3_1 (REG_E_MODE1_A5to3_1);
wildcard state s_REG_E_MODE1_A5to3_2 (REG_E_MODE1_A5to3_2);
wildcard state s_REG_E_MODE1_A5to3_3 (REG_E_MODE1_A5to3_3);
wildcard state s_REG_E_MODE1_A5to3_4 (REG_E_MODE1_A5to3_4);
wildcard state s_REG_E_MODE1_A6n2_0 (REG_E_MODE1_A6n2_0);
wildcard state s_REG_E_MODE1_A6n2_1 (REG_E_MODE1_A6n2_1);
wildcard state s_REG_E_MODE1_A6n2_2 (REG_E_MODE1_A6n2_2);
wildcard state s_REG_E_MODE1_A9to7_0 (REG_E_MODE1_A9to7_0);
wildcard state s_REG_E_MODE1_A9to7_1 (REG_E_MODE1_A9to7_1);
wildcard state s_REG_E_MODE1_A9to7_2 (REG_E_MODE1_A9to7_2);
wildcard state s_REG_E_MODE1_A9to7_4 (REG_E_MODE1_A9to7_4);
wildcard state s_REG_E_MODE1_A9to7_7 (REG_E_MODE1_A9to7_7);
wildcard state s_REG_E_MODE1_A11to10_0 (REG_E_MODE1_A11to10_0);
wildcard state s_REG_E_MODE1_A11to10_1 (REG_E_MODE1_A11to10_1);
wildcard state s_REG_E_MODE1_A11to10_2 (REG_E_MODE1_A11to10_2);
wildcard state s_REG_E_MODE1_A11to10_3 (REG_E_MODE1_A11to10_3);
wildcard state s_REG_E_MODE1_A12_0 (REG_E_MODE1_A12_0);
wildcard state s_REG_E_MODE1_A12_1 (REG_E_MODE1_A12_1);
//bad_state s_not_rd_sync0 (not state);
//bad_trans t_not_rd_sync0 (not trans);
//bad_trans t_rd_bad_sync1_3 (2'b01 -> 2'b11);
projects / OpenSPARC-T2-DV / blob