[OpenSPARC-T2-DV] / verif / env / common / coverage / siu / siu_cov.if.vrhpal

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: siu_cov.if.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
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// may be used, or where a choice of which version of the GPL is applied is 
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// ========== Copyright Header End ============================================
#ifndef __SIU_COV_IF_VRH__
#define __SIU_COV_IF_VRH__

#include <vera_defines.vrh>

#define OUTPUT_EDGE  PHOLD
#define OUTPUT_SKEW  #3
#define INPUT_EDGE   PSAMPLE
#define INPUT_SKEW   #-3

#ifdef FC_COVERAGE
#define SII	`TOP.cpu.sii
#define SIO	`TOP.cpu.sio
#else
#define SII	siu_top.cpu.sii
#define SIO	siu_top.cpu.sio
#endif


interface siu_coverage_ifc
{
// Common & Clock Signals
input           clk     CLOCK                           verilog_node "`SII.iol2clk";

input           cmp_diag_done           PSAMPLE;

// dmu interface
input           dmureq          INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.dmu_sii_hdr_vld";
input           dmubypass       INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.dmu_sii_reqbypass";
input           dmudatareq      INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.dmu_sii_datareq";
input           dmudatareq16    INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.dmu_sii_datareq16";
input [127:0]   dmudata         INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.dmu_sii_data";
input [1:0]     dmuparity       INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.dmu_sii_parity";
input [15:0]    dmube           INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.dmu_sii_be";
input           dmuwrack_vld    INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.sii_dmu_wrack_vld";
input [3:0]     dmuwrack_tag    INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.sii_dmu_wrack_tag";

//sio-dmu
input           sio_dmu_req     INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.sio_dmu_hdr_vld";
input [127:0]   sio_dmu_data   	INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.sio_dmu_data";

// niu interface
input           niureq          INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.niu_sii_hdr_vld";
input           niubypass       INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.niu_sii_reqbypass";
input           niudatareq      INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.niu_sii_datareq";
input           niudatareq16    INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.niu_sii_datareq16";
input [127:0]   niudata         INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.niu_sii_data";
input [1:0]     niuparity       INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.niu_sii_parity";
input           niuoqdq    	INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.sii_niu_oqdq";
input           niubqdq    	INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.sii_niu_bqdq";

//sio-niu
input           sio_niu_req    	INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.sio_niu_hdr_vld";
input [127:0]   sio_niu_data   	INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.sio_niu_data";
input           niu_sio_dq    	INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.niu_sio_dq";

//ncu-sii
input           ncu_gnt         INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ncu_sii_gnt";
input           ncu_req         INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.sii_ncu_req";
input           ncu_pm          INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ncu_sii_pm";
input           ncu_ba01        INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ncu_sii_ba01";
input           ncu_ba23        INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ncu_sii_ba23";
input           ncu_ba45        INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ncu_sii_ba45";
input           ncu_ba67        INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ncu_sii_ba67";

}

interface siu_coverage_ifc_l2
{
input           clk     	CLOCK		verilog_node "`SII.l2clk";
input           cmp_diag_done	PSAMPLE;

// L2 interface
. for ($bank=0; $bank<8; $bank++)
.{
  input           l2t${bank}_iq_dq		INPUT_EDGE	INPUT_SKEW      verilog_node "`SII.l2t${bank}_sii_iq_dequeue";
  input           l2t${bank}_wib_dq       	INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.l2t${bank}_sii_wib_dequeue";
  input           sii_l2t${bank}        	INPUT_EDGE     	INPUT_SKEW     	verilog_node "`SII.sii_l2t${bank}_req_vld";
  input  [31:0]   sii_l2t${bank}_data   	INPUT_EDGE     	INPUT_SKEW     	verilog_node "`SII.sii_l2t${bank}_req";

input l2b${bank}_sio_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`SIO.l2b${bank}_sio_ctag_vld";
input [31:0] l2b${bank}_sio_data INPUT_EDGE INPUT_SKEW verilog_node "`SIO.l2b${bank}_sio_data"; 

.}

}

// ipdohq ipodq
.for ($q=0; $q<2; $q++)
.{
interface siu_coverage_ipdoq${q}_rd 
{
input		clk		CLOCK		verilog_node "`SII.ipdohq${q}.rdclk";
input           cmp_diag_done	PSAMPLE;

input		h_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdohq${q}.rd_en";
input [3:0]	h_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdohq${q}.rd_adr";
input		d_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdodq${q}_l.rd_en";
input [5:0]	d_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdodq${q}_l.rd_adr";
}

interface siu_coverage_ipdoq${q}_wr 
{
input		clk		CLOCK		verilog_node "`SII.ipdohq${q}.wrclk";
input           cmp_diag_done	PSAMPLE;

input		h_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdohq${q}.wr_en";
input [3:0]	h_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdohq${q}.wr_adr";
input		d_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdodq${q}_l.wr_en";
input [5:0]	d_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdodq${q}_l.wr_adr";

}
.}

.for ($q=0; $q<2; $q++)
.{
interface siu_coverage_ipdbq${q}_rd
{
input		clk		CLOCK		verilog_node "`SII.ipdbhq${q}.rdclk";
input           cmp_diag_done	PSAMPLE;

input		h_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdbhq${q}.rd_en";
input [3:0]	h_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdbhq${q}.rd_adr";
input		d_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdbdq${q}_l.rd_en";
input [5:0]	d_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdbdq${q}_l.rd_adr";
}

interface siu_coverage_ipdbq${q}_wr
{
input		clk		CLOCK		verilog_node "`SII.ipdbhq${q}.wrclk";
input           cmp_diag_done	PSAMPLE;

input		h_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdbhq${q}.wr_en";
input [3:0]	h_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdbhq${q}.wr_adr";
input		d_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdbdq${q}_l.wr_en";
input [5:0]	d_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdbdq${q}_l.wr_adr";
}
.}

.for ($q=0; $q<8; $q++)
.{
interface siu_coverage_ildq${q}
{
input		clk		CLOCK		verilog_node "`SII.ildq${q}.rdclk";
input           cmp_diag_done	PSAMPLE;

input		wr_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ildq${q}.wr_en";
input [4:0]	wr_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ildq${q}.wr_adr";
input		rd_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ildq${q}.rd_en";
input [4:0]	rd_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ildq${q}.rd_adr";
}
.}

interface siu_coverage_indq
{
input		clk		CLOCK		verilog_node "`SII.indq.rdclk";
input           cmp_diag_done	PSAMPLE;

input		wr_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.indq.wr_en";
input [5:0]	wr_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.indq.wr_adr";
input		rd_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.indq.rd_en";
input [5:0]	rd_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.indq.rd_adr";
}

interface siu_coverage_ipcc_ipcs
{
input		clk		CLOCK		verilog_node "`SII.ipcs0.iol2clk";
input           cmp_diag_done	PSAMPLE;

input		by0_go		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs0.ipcc_ipcs_by_go";
input [3:0]	by0_raddr	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs0.ipcc_ipcs_by_raddr";
input		or0_go		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs0.ipcc_ipcs_or_go";
input [3:0]	or0_raddr	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs0.ipcc_ipcs_or_raddr";
input		by1_go		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs1.ipcc_ipcs_by_go";
input [3:0]	by1_raddr	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs1.ipcc_ipcs_by_raddr";
input		or1_go		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs1.ipcc_ipcs_or_go";
input [3:0]	or1_raddr	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs1.ipcc_ipcs_or_raddr";
}

interface siu_sii_check_cnt_dmu_or
{
input		clk		CLOCK		verilog_node "`SII.ipcc.l2clk";
input [4:0]	dmu_or_cnt_r	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.dmu_or_cnt_r";
}

interface siu_sii_check_cnt_dmu_by
{
input		clk		CLOCK		verilog_node "`SII.ipcc.l2clk";
input [4:0]	dmu_by_cnt_r	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.dmu_by_cnt_r";
}

interface siu_sii_check_cnt_niu_or
{
input		clk		CLOCK		verilog_node "`SII.ipcc.l2clk";
input [4:0]	niu_or_cnt_r	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.niu_or_cnt_r";
}

interface siu_sii_check_cnt_niu_by
{
input		clk		CLOCK		verilog_node "`SII.ipcc.l2clk";
input [4:0]	niu_by_cnt_r	INPUT_EDGE	INPUT_SKEW      verilog_node "`SII.ipcc.niu_by_cnt_r";
}

interface siu_sio_commun_dmu_by
{
input		clk				CLOCK		verilog_node "`SIO.opcc.l2clk";
input [2:0]	sio_sii_opcc_ipcc_dmu_by_cnt	INPUT_EDGE	INPUT_SKEW      verilog_node "`SIO.opcc.sio_sii_opcc_ipcc_dmu_by_cnt";
}

interface siu_sio_commun_niu_by
{
input		clk				CLOCK		verilog_node "`SIO.opcc.l2clk";
input [2:0]	sio_sii_opcc_ipcc_niu_by_cnt	INPUT_EDGE	INPUT_SKEW      verilog_node "`SIO.opcc.sio_sii_opcc_ipcc_niu_by_cnt";
}

.for ($q=0; $q<8; $q++)
.{
interface siu_sio_buffer_cnt_ilc${q}
{
input		clk		CLOCK		verilog_node "`SII.ipcc.l2clk";
input [2:0]	sio_cnt_r	INPUT_EDGE	INPUT_SKEW      verilog_node "`SII.ilc${q}.sio_cnt_r";
}
.}

interface siu_ipcc_wrm_cnt
{
input		clk		CLOCK		verilog_node "`SII.ipcc.l2clk";
input [3:0]	dmu_wrm_cnt_r	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.dmu_wrm_cnt_r";
}

.for ($q=0; $q<8; $q++)
.{
interface siu_ilc${q}_wrm_cnt
{
input		clk		CLOCK		verilog_node "`SII.ipcc.l2clk";
input [2:0]	wrm_cnt_r	INPUT_EDGE	INPUT_SKEW      verilog_node "`SII.ilc${q}.wrm_cnt_r";
}
.}

.for ($q=0; $q<8; $q++)
.{
interface siu_ilc${q}_state_machine
{
input		clk		CLOCK		verilog_node "`SII.ilc${q}.l2clk";
input [5:0]	cstate  	INPUT_EDGE	INPUT_SKEW      verilog_node "`SII.ilc${q}.cstate";
}
.}

interface siu_ipcc_state_machine
{
input		clk		CLOCK		verilog_node "`SII.ipcc.l2clk";
input [13:0]	cstate		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.cstate";
}

interface siu_inc_state_machine
{
input		clk		CLOCK		verilog_node "`SII.inc.l2clk";
input [4:0]	cstate		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.inc.cstate";
}

.for ($q=0; $q<2; $q++)
.{
interface siu_ipcs${q}_state_machine
{
input		clk		CLOCK		verilog_node "`SII.ipcs${q}.iol2clk";
input [6:0]	cstate  	INPUT_EDGE	INPUT_SKEW      verilog_node "`SII.ipcs${q}.cstate";
}
.}

.for ($q=0; $q<2; $q++)
.{
interface siu_opcs${q}_state_machine
{
input		clk		CLOCK		verilog_node "`SIO.opcs${q}.iol2clk";
input [7:0]	cstate		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.opcs${q}.cstate";
}
.}

interface siu_coverage_ipcs_order
{
input		clk		CLOCK		verilog_node "`SII.ipcs0.iol2clk";
input [3:0]	young0_match	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs0.youngest_match";
input [3:0]	young0_dep	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs0.youngest_dep";
input [3:0]	young1_match	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs1.youngest_match";
input [3:0]	young1_dep	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs1.youngest_dep";
}


interface siu_coverage_ipcc_arb
{
input		clk		CLOCK		verilog_node "`SII.ipcc.l2clk";
input		niu_by_go	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.niu_by_go";
input		niu_or_go	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.niu_or_go";
input		dmu_by_go	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.dmu_by_go";
input		dmu_or_go	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.dmu_or_go";
input		tcu_go		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.tcu_go";
}

///
/// SIO
///
.for ($q=0; $q<2; $q++)
.{
interface siu_coverage_opdhq${q}_rd
{
input		clk		CLOCK		verilog_node "`SIO.opdhq${q}.rdclk";

input		rd_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.opdhq${q}.rd_en";
input [3:0]	rd_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.opdhq${q}.rd_adr";
}

interface siu_coverage_opdhq${q}_wr
{
input		clk		CLOCK		verilog_node "`SIO.opdhq${q}.wrclk";

input		wr_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.opdhq${q}.wr_en";
input [3:0]	wr_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.opdhq${q}.wr_adr";
}
.}

.for ($q=0; $q<2; $q++)
.{
.for ($p=0; $p<2; $p++)
.{
interface siu_coverage_opddq${q}${p}_rd
{
input		clk		CLOCK		verilog_node "`SIO.opddq${q}${p}.rdclk";

input		rd_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.opddq${q}${p}.rd_en";
input [5:0]	rd_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.opddq${q}${p}.rd_adr";
}

interface siu_coverage_opddq${q}${p}_wr
{
input		clk		CLOCK		verilog_node "`SIO.opddq${q}${p}.wrclk";

input		wr_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.opddq${q}${p}.wr_en";
input [5:0]	wr_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.opddq${q}${p}.wr_adr";
}
.}
.}

.for ($bank=0; $bank<8; $bank++)
.{
.for ($q=0; $q<2; $q++)
.{
interface siu_coverage_olddq${bank}${q}
{
input		clk		CLOCK		verilog_node "`SIO.olddq${bank}${q}.rdclk";
input           cmp_diag_done	PSAMPLE;

input		wr_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olddq${bank}${q}.wr_en";
input [4:0]	wr_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olddq${bank}${q}.wr_adr";
input		rd_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olddq${bank}${q}.rd_en";
input [4:0]	rd_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olddq${bank}${q}.rd_adr";
}
.}
.}


interface siu_coverage_opcc_arb
{
input		clk		CLOCK		verilog_node "`SIO.l2clk";
input		olc0_req	INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olc0_opcc_req";
input		olc1_req	INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olc1_opcc_req";
input		olc2_req	INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olc2_opcc_req";
input		olc3_req	INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olc3_opcc_req";
input		olc4_req	INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olc4_opcc_req";
input		olc5_req	INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olc5_opcc_req";
input		olc6_req	INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olc6_opcc_req";
input		olc7_req	INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olc7_opcc_req";
}

interface siu_coverage_tcu_pkt
{
input           clk            CLOCK            verilog_node "`SII.l2clk";
input		jtag_cov       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.newhdr_l2[63]";
input[2:0]	tcurdwr	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.newhdr_l2[58:56]";
input		tcureq	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.tcu_sii_vld";
}

interface siu_coverage_err_det
{
input           clk            CLOCK            verilog_node "`SII.l2clk";
input		cp_err	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.cmd_parity_err";
input		ap_err	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.addr_parity_err";
input		dp_err	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.data_parity_err";
input		cecc_ue	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.ctag_ecc_ue";
input		cecc_ce	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.ctag_ecc_ce";
input[15:0]	id	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.id";
input[5:0]	c	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.c";
input[5:0]	e	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.e";
input[3:0]	ebits_piortn   INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.sii_ncu_data[31:28]";
input[5:0]	err_sig_l      INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.err_sig_l";
input		sending_r      INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.sending_r";
}
// *****************************************************************************************************
// Interface for SIU internal coverage obj for FC
// *****************************************************************************************************

.for ($q=0; $q<2; $q++)
.{
interface siu_coverage_opcs${q}_err
{
input           clk            CLOCK            verilog_node "`SIO.l2clk";
input           ctag_ue        INPUT_EDGE       INPUT_SKEW      verilog_node "`SIO.opcs${q}.myctag_ue"; 
input           ctag_ce        INPUT_EDGE       INPUT_SKEW      verilog_node "`SIO.opcs${q}.myctag_ce"; 
input[5:0]      e              INPUT_EDGE       INPUT_SKEW      verilog_node "`SIO.opcs${q}.e"; 
input[15:0]	id	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.opcs${q}.id";
}
.}

.for ($bank=0; $bank<8; $bank++)
.{
.for ($q=0; $q<2; $q++)
.{
interface sio_fifo_depth_olddq${bank}${q}
{ 
input           clk             CLOCK                           verilog_node "`SIO.olddq${bank}${q}.rdclk";
input           wr_en           INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.olddq${bank}${q}.wr_en";
input [4:0]     wr_adr          INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.olddq${bank}${q}.wr_adr";
input           rd_en           INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.olddq${bank}${q}.rd_en";
input [4:0]     rd_adr          INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.olddq${bank}${q}.rd_adr";
} 
.}
        
interface sii_fifo_depth_ildq${bank}
{
input           clk             CLOCK                           verilog_node "`SII.ildq${q}.rdclk";
input           wr_en           INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ildq${q}.wr_en";
input [4:0]     wr_adr          INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ildq${q}.wr_adr";
input           rd_en           INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ildq${q}.rd_en";
input [4:0]     rd_adr          INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ildq${q}.rd_adr";
}       
.}      

interface l2b_to_sio_UEs
{
input           clk             CLOCK                           verilog_node "`SII.l2clk";
.for ($bank=0; $bank<8; $bank++)
.{
input           l2b${bank}_to_sio_ue_err	INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.l2b${bank}_sio_ue_err";
input [31:0]    l2b${bank}_to_sio_data 		INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.l2b${bank}_sio_data";
input           l2b${bank}_to_sio_ctag_vld	INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.l2b${bank}_sio_ctag_vld";
.}
}

interface siu_ncu_ctag_ce
{
input           clk             CLOCK                           		verilog_node "`SII.iol2clk";
input           sii_ncu_niuctag_ce		INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.sii_ncu_niuctag_ce";
input           sii_ncu_dmuctag_ce		INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.sii_ncu_dmuctag_ce";
input           sio_ncu_ctag_ce			INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.sio_ncu_ctag_ce";
}

#endif
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: siu_cov.if.vrhpal
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	#ifndef __SIU_COV_IF_VRH__
	36	#define __SIU_COV_IF_VRH__
	37
	38	#include <vera_defines.vrh>
	39
	40	#define OUTPUT_EDGE PHOLD
	41	#define OUTPUT_SKEW #3
	42	#define INPUT_EDGE PSAMPLE
	43	#define INPUT_SKEW #-3
	44
	45	#ifdef FC_COVERAGE
	46	#define SII `TOP.cpu.sii
	47	#define SIO `TOP.cpu.sio
	48	#else
	49	#define SII siu_top.cpu.sii
	50	#define SIO siu_top.cpu.sio
	51	#endif
	52
	53
	54
	55	interface siu_coverage_ifc
	56	{
	57	// Common & Clock Signals
	58	input clk CLOCK verilog_node "`SII.iol2clk";
	59
	60	input cmp_diag_done PSAMPLE;
	61
	62	// dmu interface
	63	input dmureq INPUT_EDGE INPUT_SKEW verilog_node "`SII.dmu_sii_hdr_vld";
	64	input dmubypass INPUT_EDGE INPUT_SKEW verilog_node "`SII.dmu_sii_reqbypass";
65	input dmudatareq INPUT_EDGE INPUT_SKEW verilog_node "`SII.dmu_sii_datareq";
66	input dmudatareq16 INPUT_EDGE INPUT_SKEW verilog_node "`SII.dmu_sii_datareq16";
67	input [127:0] dmudata INPUT_EDGE INPUT_SKEW verilog_node "`SII.dmu_sii_data";
68	input [1:0] dmuparity INPUT_EDGE INPUT_SKEW verilog_node "`SII.dmu_sii_parity";
69	input [15:0] dmube INPUT_EDGE INPUT_SKEW verilog_node "`SII.dmu_sii_be";
70	input dmuwrack_vld INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_dmu_wrack_vld";
71	input [3:0] dmuwrack_tag INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_dmu_wrack_tag";
72
73	//sio-dmu
74	input sio_dmu_req INPUT_EDGE INPUT_SKEW verilog_node "`SIO.sio_dmu_hdr_vld";
75	input [127:0] sio_dmu_data INPUT_EDGE INPUT_SKEW verilog_node "`SIO.sio_dmu_data";
76
77	// niu interface
78	input niureq INPUT_EDGE INPUT_SKEW verilog_node "`SII.niu_sii_hdr_vld";
79	input niubypass INPUT_EDGE INPUT_SKEW verilog_node "`SII.niu_sii_reqbypass";
80	input niudatareq INPUT_EDGE INPUT_SKEW verilog_node "`SII.niu_sii_datareq";
81	input niudatareq16 INPUT_EDGE INPUT_SKEW verilog_node "`SII.niu_sii_datareq16";
82	input [127:0] niudata INPUT_EDGE INPUT_SKEW verilog_node "`SII.niu_sii_data";
83	input [1:0] niuparity INPUT_EDGE INPUT_SKEW verilog_node "`SII.niu_sii_parity";
84	input niuoqdq INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_niu_oqdq";
85	input niubqdq INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_niu_bqdq";
86
87	//sio-niu
88	input sio_niu_req INPUT_EDGE INPUT_SKEW verilog_node "`SIO.sio_niu_hdr_vld";
89	input [127:0] sio_niu_data INPUT_EDGE INPUT_SKEW verilog_node "`SIO.sio_niu_data";
90	input niu_sio_dq INPUT_EDGE INPUT_SKEW verilog_node "`SIO.niu_sio_dq";
91
92	//ncu-sii
93	input ncu_gnt INPUT_EDGE INPUT_SKEW verilog_node "`SII.ncu_sii_gnt";
94	input ncu_req INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_ncu_req";
95	input ncu_pm INPUT_EDGE INPUT_SKEW verilog_node "`SII.ncu_sii_pm";
96	input ncu_ba01 INPUT_EDGE INPUT_SKEW verilog_node "`SII.ncu_sii_ba01";
97	input ncu_ba23 INPUT_EDGE INPUT_SKEW verilog_node "`SII.ncu_sii_ba23";
98	input ncu_ba45 INPUT_EDGE INPUT_SKEW verilog_node "`SII.ncu_sii_ba45";
99	input ncu_ba67 INPUT_EDGE INPUT_SKEW verilog_node "`SII.ncu_sii_ba67";
100
101	}
102
103	interface siu_coverage_ifc_l2
104	{
105	input clk CLOCK verilog_node "`SII.l2clk";
106	input cmp_diag_done PSAMPLE;
107
108	// L2 interface
109	. for ($bank=0; $bank<8; $bank++)
110	.{
111	input l2t${bank}_iq_dq INPUT_EDGE INPUT_SKEW verilog_node "`SII.l2t${bank}_sii_iq_dequeue";
112	input l2t${bank}_wib_dq INPUT_EDGE INPUT_SKEW verilog_node "`SII.l2t${bank}_sii_wib_dequeue";
113	input sii_l2t${bank} INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_l2t${bank}_req_vld";
114	input [31:0] sii_l2t${bank}_data INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_l2t${bank}_req";
115
116	input l2b${bank}_sio_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`SIO.l2b${bank}_sio_ctag_vld";
117	input [31:0] l2b${bank}_sio_data INPUT_EDGE INPUT_SKEW verilog_node "`SIO.l2b${bank}_sio_data";
118
119	.}
120
121	}
122
123	// ipdohq ipodq
124	.for ($q=0; $q<2; $q++)
125	.{
126	interface siu_coverage_ipdoq${q}_rd
127	{
128	input clk CLOCK verilog_node "`SII.ipdohq${q}.rdclk";
129	input cmp_diag_done PSAMPLE;
130
131	input h_en INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipdohq${q}.rd_en";
132	input [3:0] h_adr INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipdohq${q}.rd_adr";
133	input d_en INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipdodq${q}_l.rd_en";
134	input [5:0] d_adr INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipdodq${q}_l.rd_adr";
135	}
136
137	interface siu_coverage_ipdoq${q}_wr
138	{
139	input clk CLOCK verilog_node "`SII.ipdohq${q}.wrclk";
140	input cmp_diag_done PSAMPLE;
141
142	input h_en INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipdohq${q}.wr_en";
143	input [3:0] h_adr INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipdohq${q}.wr_adr";
144	input d_en INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipdodq${q}_l.wr_en";
145	input [5:0] d_adr INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipdodq${q}_l.wr_adr";
146
147	}
148	.}
149
150	.for ($q=0; $q<2; $q++)
151	.{
152	interface siu_coverage_ipdbq${q}_rd
153	{
154	input clk CLOCK verilog_node "`SII.ipdbhq${q}.rdclk";
155	input cmp_diag_done PSAMPLE;
156
157	input h_en INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipdbhq${q}.rd_en";
158	input [3:0] h_adr INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipdbhq${q}.rd_adr";
159	input d_en INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipdbdq${q}_l.rd_en";
160	input [5:0] d_adr INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipdbdq${q}_l.rd_adr";
161	}
162
163	interface siu_coverage_ipdbq${q}_wr
164	{
165	input clk CLOCK verilog_node "`SII.ipdbhq${q}.wrclk";
166	input cmp_diag_done PSAMPLE;
167
168	input h_en INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipdbhq${q}.wr_en";
169	input [3:0] h_adr INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipdbhq${q}.wr_adr";
170	input d_en INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipdbdq${q}_l.wr_en";
171	input [5:0] d_adr INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipdbdq${q}_l.wr_adr";
172	}
173	.}
174
175	.for ($q=0; $q<8; $q++)
176	.{
177	interface siu_coverage_ildq${q}
178	{
179	input clk CLOCK verilog_node "`SII.ildq${q}.rdclk";
180	input cmp_diag_done PSAMPLE;
181
182	input wr_en INPUT_EDGE INPUT_SKEW verilog_node "`SII.ildq${q}.wr_en";
183	input [4:0] wr_adr INPUT_EDGE INPUT_SKEW verilog_node "`SII.ildq${q}.wr_adr";
184	input rd_en INPUT_EDGE INPUT_SKEW verilog_node "`SII.ildq${q}.rd_en";
185	input [4:0] rd_adr INPUT_EDGE INPUT_SKEW verilog_node "`SII.ildq${q}.rd_adr";
186	}
187	.}
188
189	interface siu_coverage_indq
190	{
191	input clk CLOCK verilog_node "`SII.indq.rdclk";
192	input cmp_diag_done PSAMPLE;
193
194	input wr_en INPUT_EDGE INPUT_SKEW verilog_node "`SII.indq.wr_en";
195	input [5:0] wr_adr INPUT_EDGE INPUT_SKEW verilog_node "`SII.indq.wr_adr";
196	input rd_en INPUT_EDGE INPUT_SKEW verilog_node "`SII.indq.rd_en";
197	input [5:0] rd_adr INPUT_EDGE INPUT_SKEW verilog_node "`SII.indq.rd_adr";
198	}
199
200	interface siu_coverage_ipcc_ipcs
201	{
202	input clk CLOCK verilog_node "`SII.ipcs0.iol2clk";
203	input cmp_diag_done PSAMPLE;
204
205	input by0_go INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcs0.ipcc_ipcs_by_go";
206	input [3:0] by0_raddr INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcs0.ipcc_ipcs_by_raddr";
207	input or0_go INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcs0.ipcc_ipcs_or_go";
208	input [3:0] or0_raddr INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcs0.ipcc_ipcs_or_raddr";
209	input by1_go INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcs1.ipcc_ipcs_by_go";
210	input [3:0] by1_raddr INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcs1.ipcc_ipcs_by_raddr";
211	input or1_go INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcs1.ipcc_ipcs_or_go";
212	input [3:0] or1_raddr INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcs1.ipcc_ipcs_or_raddr";
213	}
214
215	interface siu_sii_check_cnt_dmu_or
216	{
217	input clk CLOCK verilog_node "`SII.ipcc.l2clk";
218	input [4:0] dmu_or_cnt_r INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.dmu_or_cnt_r";
219	}
220
221	interface siu_sii_check_cnt_dmu_by
222	{
223	input clk CLOCK verilog_node "`SII.ipcc.l2clk";
224	input [4:0] dmu_by_cnt_r INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.dmu_by_cnt_r";
225	}
226
227	interface siu_sii_check_cnt_niu_or
228	{
229	input clk CLOCK verilog_node "`SII.ipcc.l2clk";
230	input [4:0] niu_or_cnt_r INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.niu_or_cnt_r";
231	}
232
233	interface siu_sii_check_cnt_niu_by
234	{
235	input clk CLOCK verilog_node "`SII.ipcc.l2clk";
236	input [4:0] niu_by_cnt_r INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.niu_by_cnt_r";
237	}
238
239	interface siu_sio_commun_dmu_by
240	{
241	input clk CLOCK verilog_node "`SIO.opcc.l2clk";
242	input [2:0] sio_sii_opcc_ipcc_dmu_by_cnt INPUT_EDGE INPUT_SKEW verilog_node "`SIO.opcc.sio_sii_opcc_ipcc_dmu_by_cnt";
243	}
244
245	interface siu_sio_commun_niu_by
246	{
247	input clk CLOCK verilog_node "`SIO.opcc.l2clk";
248	input [2:0] sio_sii_opcc_ipcc_niu_by_cnt INPUT_EDGE INPUT_SKEW verilog_node "`SIO.opcc.sio_sii_opcc_ipcc_niu_by_cnt";
249	}
250
251	.for ($q=0; $q<8; $q++)
252	.{
253	interface siu_sio_buffer_cnt_ilc${q}
254	{
255	input clk CLOCK verilog_node "`SII.ipcc.l2clk";
256	input [2:0] sio_cnt_r INPUT_EDGE INPUT_SKEW verilog_node "`SII.ilc${q}.sio_cnt_r";
257	}
258	.}
259
260	interface siu_ipcc_wrm_cnt
261	{
262	input clk CLOCK verilog_node "`SII.ipcc.l2clk";
263	input [3:0] dmu_wrm_cnt_r INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.dmu_wrm_cnt_r";
264	}
265
266	.for ($q=0; $q<8; $q++)
267	.{
268	interface siu_ilc${q}_wrm_cnt
269	{
270	input clk CLOCK verilog_node "`SII.ipcc.l2clk";
271	input [2:0] wrm_cnt_r INPUT_EDGE INPUT_SKEW verilog_node "`SII.ilc${q}.wrm_cnt_r";
272	}
273	.}
274
275	.for ($q=0; $q<8; $q++)
276	.{
277	interface siu_ilc${q}_state_machine
278	{
279	input clk CLOCK verilog_node "`SII.ilc${q}.l2clk";
280	input [5:0] cstate INPUT_EDGE INPUT_SKEW verilog_node "`SII.ilc${q}.cstate";
281	}
282	.}
283
284	interface siu_ipcc_state_machine
285	{
286	input clk CLOCK verilog_node "`SII.ipcc.l2clk";
287	input [13:0] cstate INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.cstate";
288	}
289
290	interface siu_inc_state_machine
291	{
292	input clk CLOCK verilog_node "`SII.inc.l2clk";
293	input [4:0] cstate INPUT_EDGE INPUT_SKEW verilog_node "`SII.inc.cstate";
294	}
295
296	.for ($q=0; $q<2; $q++)
297	.{
298	interface siu_ipcs${q}_state_machine
299	{
300	input clk CLOCK verilog_node "`SII.ipcs${q}.iol2clk";
301	input [6:0] cstate INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcs${q}.cstate";
302	}
303	.}
304
305	.for ($q=0; $q<2; $q++)
306	.{
307	interface siu_opcs${q}_state_machine
308	{
309	input clk CLOCK verilog_node "`SIO.opcs${q}.iol2clk";
310	input [7:0] cstate INPUT_EDGE INPUT_SKEW verilog_node "`SIO.opcs${q}.cstate";
311	}
312	.}
313
314	interface siu_coverage_ipcs_order
315	{
316	input clk CLOCK verilog_node "`SII.ipcs0.iol2clk";
317	input [3:0] young0_match INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcs0.youngest_match";
318	input [3:0] young0_dep INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcs0.youngest_dep";
319	input [3:0] young1_match INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcs1.youngest_match";
320	input [3:0] young1_dep INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcs1.youngest_dep";
321	}
322
323
324	interface siu_coverage_ipcc_arb
325	{
326	input clk CLOCK verilog_node "`SII.ipcc.l2clk";
327	input niu_by_go INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.niu_by_go";
328	input niu_or_go INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.niu_or_go";
329	input dmu_by_go INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.dmu_by_go";
330	input dmu_or_go INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.dmu_or_go";
331	input tcu_go INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.tcu_go";
332	}
333
334	///
335	/// SIO
336	///
337	.for ($q=0; $q<2; $q++)
338	.{
339	interface siu_coverage_opdhq${q}_rd
340	{
341	input clk CLOCK verilog_node "`SIO.opdhq${q}.rdclk";
342
343	input rd_en INPUT_EDGE INPUT_SKEW verilog_node "`SIO.opdhq${q}.rd_en";
344	input [3:0] rd_adr INPUT_EDGE INPUT_SKEW verilog_node "`SIO.opdhq${q}.rd_adr";
345	}
346
347	interface siu_coverage_opdhq${q}_wr
348	{
349	input clk CLOCK verilog_node "`SIO.opdhq${q}.wrclk";
350
351	input wr_en INPUT_EDGE INPUT_SKEW verilog_node "`SIO.opdhq${q}.wr_en";
352	input [3:0] wr_adr INPUT_EDGE INPUT_SKEW verilog_node "`SIO.opdhq${q}.wr_adr";
353	}
354	.}
355
356	.for ($q=0; $q<2; $q++)
357	.{
358	.for ($p=0; $p<2; $p++)
359	.{
360	interface siu_coverage_opddq${q}${p}_rd
361	{
362	input clk CLOCK verilog_node "`SIO.opddq${q}${p}.rdclk";
363
364	input rd_en INPUT_EDGE INPUT_SKEW verilog_node "`SIO.opddq${q}${p}.rd_en";
365	input [5:0] rd_adr INPUT_EDGE INPUT_SKEW verilog_node "`SIO.opddq${q}${p}.rd_adr";
366	}
367
368	interface siu_coverage_opddq${q}${p}_wr
369	{
370	input clk CLOCK verilog_node "`SIO.opddq${q}${p}.wrclk";
371
372	input wr_en INPUT_EDGE INPUT_SKEW verilog_node "`SIO.opddq${q}${p}.wr_en";
373	input [5:0] wr_adr INPUT_EDGE INPUT_SKEW verilog_node "`SIO.opddq${q}${p}.wr_adr";
374	}
375	.}
376	.}
377
378	.for ($bank=0; $bank<8; $bank++)
379	.{
380	.for ($q=0; $q<2; $q++)
381	.{
382	interface siu_coverage_olddq${bank}${q}
383	{
384	input clk CLOCK verilog_node "`SIO.olddq${bank}${q}.rdclk";
385	input cmp_diag_done PSAMPLE;
386
387	input wr_en INPUT_EDGE INPUT_SKEW verilog_node "`SIO.olddq${bank}${q}.wr_en";
388	input [4:0] wr_adr INPUT_EDGE INPUT_SKEW verilog_node "`SIO.olddq${bank}${q}.wr_adr";
389	input rd_en INPUT_EDGE INPUT_SKEW verilog_node "`SIO.olddq${bank}${q}.rd_en";
390	input [4:0] rd_adr INPUT_EDGE INPUT_SKEW verilog_node "`SIO.olddq${bank}${q}.rd_adr";
391	}
392	.}
393	.}
394
395
396	interface siu_coverage_opcc_arb
397	{
398	input clk CLOCK verilog_node "`SIO.l2clk";
399	input olc0_req INPUT_EDGE INPUT_SKEW verilog_node "`SIO.olc0_opcc_req";
400	input olc1_req INPUT_EDGE INPUT_SKEW verilog_node "`SIO.olc1_opcc_req";
401	input olc2_req INPUT_EDGE INPUT_SKEW verilog_node "`SIO.olc2_opcc_req";
402	input olc3_req INPUT_EDGE INPUT_SKEW verilog_node "`SIO.olc3_opcc_req";
403	input olc4_req INPUT_EDGE INPUT_SKEW verilog_node "`SIO.olc4_opcc_req";
404	input olc5_req INPUT_EDGE INPUT_SKEW verilog_node "`SIO.olc5_opcc_req";
405	input olc6_req INPUT_EDGE INPUT_SKEW verilog_node "`SIO.olc6_opcc_req";
406	input olc7_req INPUT_EDGE INPUT_SKEW verilog_node "`SIO.olc7_opcc_req";
407	}
408
409	interface siu_coverage_tcu_pkt
410	{
411	input clk CLOCK verilog_node "`SII.l2clk";
412	input jtag_cov INPUT_EDGE INPUT_SKEW verilog_node "`SII.newhdr_l2[63]";
413	input[2:0] tcurdwr INPUT_EDGE INPUT_SKEW verilog_node "`SII.newhdr_l2[58:56]";
414	input tcureq INPUT_EDGE INPUT_SKEW verilog_node "`SII.tcu_sii_vld";
415	}
416
417	interface siu_coverage_err_det
418	{
419	input clk CLOCK verilog_node "`SII.l2clk";
420	input cp_err INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.cmd_parity_err";
421	input ap_err INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.addr_parity_err";
422	input dp_err INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.data_parity_err";
423	input cecc_ue INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.ctag_ecc_ue";
424	input cecc_ce INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.ctag_ecc_ce";
425	input[15:0] id INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.id";
426	input[5:0] c INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.c";
427	input[5:0] e INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.e";
428	input[3:0] ebits_piortn INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_ncu_data[31:28]";
429	input[5:0] err_sig_l INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.err_sig_l";
430	input sending_r INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.sending_r";
431	}
432	// *****************************************************************************************************
433	// Interface for SIU internal coverage obj for FC
434	// *****************************************************************************************************
435
436	.for ($q=0; $q<2; $q++)
437	.{
438	interface siu_coverage_opcs${q}_err
439	{
440	input clk CLOCK verilog_node "`SIO.l2clk";
441	input ctag_ue INPUT_EDGE INPUT_SKEW verilog_node "`SIO.opcs${q}.myctag_ue";
442	input ctag_ce INPUT_EDGE INPUT_SKEW verilog_node "`SIO.opcs${q}.myctag_ce";
443	input[5:0] e INPUT_EDGE INPUT_SKEW verilog_node "`SIO.opcs${q}.e";
444	input[15:0] id INPUT_EDGE INPUT_SKEW verilog_node "`SIO.opcs${q}.id";
445	}
446	.}
447
448	.for ($bank=0; $bank<8; $bank++)
449	.{
450	.for ($q=0; $q<2; $q++)
451	.{
452	interface sio_fifo_depth_olddq${bank}${q}
453	{
454	input clk CLOCK verilog_node "`SIO.olddq${bank}${q}.rdclk";
455	input wr_en INPUT_EDGE INPUT_SKEW verilog_node "`SIO.olddq${bank}${q}.wr_en";
456	input [4:0] wr_adr INPUT_EDGE INPUT_SKEW verilog_node "`SIO.olddq${bank}${q}.wr_adr";
457	input rd_en INPUT_EDGE INPUT_SKEW verilog_node "`SIO.olddq${bank}${q}.rd_en";
458	input [4:0] rd_adr INPUT_EDGE INPUT_SKEW verilog_node "`SIO.olddq${bank}${q}.rd_adr";
459	}
460	.}
461
462	interface sii_fifo_depth_ildq${bank}
463	{
464	input clk CLOCK verilog_node "`SII.ildq${q}.rdclk";
465	input wr_en INPUT_EDGE INPUT_SKEW verilog_node "`SII.ildq${q}.wr_en";
466	input [4:0] wr_adr INPUT_EDGE INPUT_SKEW verilog_node "`SII.ildq${q}.wr_adr";
467	input rd_en INPUT_EDGE INPUT_SKEW verilog_node "`SII.ildq${q}.rd_en";
468	input [4:0] rd_adr INPUT_EDGE INPUT_SKEW verilog_node "`SII.ildq${q}.rd_adr";
469	}
470	.}
471
472	interface l2b_to_sio_UEs
473	{
474	input clk CLOCK verilog_node "`SII.l2clk";
475	.for ($bank=0; $bank<8; $bank++)
476	.{
477	input l2b${bank}_to_sio_ue_err INPUT_EDGE INPUT_SKEW verilog_node "`SIO.l2b${bank}_sio_ue_err";
478	input [31:0] l2b${bank}_to_sio_data INPUT_EDGE INPUT_SKEW verilog_node "`SIO.l2b${bank}_sio_data";
479	input l2b${bank}_to_sio_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`SIO.l2b${bank}_sio_ctag_vld";
480	.}
481	}
482
483	interface siu_ncu_ctag_ce
484	{
485	input clk CLOCK verilog_node "`SII.iol2clk";
486	input sii_ncu_niuctag_ce INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_ncu_niuctag_ce";
487	input sii_ncu_dmuctag_ce INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_ncu_dmuctag_ce";
488	input sio_ncu_ctag_ce INPUT_EDGE INPUT_SKEW verilog_node "`SIO.sio_ncu_ctag_ce";
489	}
490
491	#endif
492