Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / siu / siu_ipcc_state.vrhpal
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: siu_ipcc_state.vrhpal
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
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10// it under the terms of the GNU General Public License as published by
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14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
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20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
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34// ========== Copyright Header End ============================================
35#define START (14'b00000000000001)
36#define DEC (14'b00000000000010)
37#define ARB (14'b00000000000100)
38#define HDR (14'b00000000001000)
39#define HDRDLY (14'b00000000010000)
40#define DATA1 (14'b00000000100000)
41#define DATA2 (14'b00000001000000)
42#define DATA3 (14'b00000010000000)
43#define DATA4 (14'b00000100000000)
44#define DATA5 (14'b00001000000000)
45#define DATA6 (14'b00010000000000)
46#define DATA7 (14'b00100000000000)
47#define DATA8 (14'b01000000000000)
48#define RDDW (14'b10000000000000)
49
50
51
52sample siu_ipcc_state_machine.cstate
53
54{
55
56 state s_START (START);
57 state s_DEC (DEC );
58 state s_ARB (ARB );
59 state s_HDR (HDR);
60 state s_HDRDLY (HDRDLY);
61 state s_DATA1 (DATA1);
62 state s_DATA2 (DATA2);
63 state s_DATA3 (DATA3);
64 state s_DATA4 (DATA4);
65 state s_DATA5 (DATA5);
66 state s_DATA6 (DATA6);
67 state s_DATA7 (DATA7);
68 state s_DATA8 (DATA8);
69 state s_RDDW (RDDW);
70
71 trans t_START_START_01 (START -> START);
72 trans t_START_DEC_02 (START -> DEC);
73 trans t_DEC_START_03 (DEC -> START);
74 trans t_DEC_ARB_04 (DEC -> ARB);
75 trans t_ARB_START_05 (ARB -> START);
76 trans t_ARB_HDR_06 (ARB -> HDR);
77 trans t_HDR_HDRDLY_07 (HDR -> HDRDLY );
78 trans t_HDRDLY_DATA1_09 (HDRDLY -> DATA1);
79 trans t_HDRDLY_RDDW_10 (HDRDLY -> RDDW);
80 trans t_RDDW_START_11 (RDDW -> START );
81 trans t_DATA1_DATA2_13 (DATA1 -> DATA2);
82 trans t_DATA2_START_14 (DATA2 -> START);
83 trans t_DATA2_DATA2_15 (DATA2 -> DATA3);
84 trans t_DATA3_DATA4_16 (DATA3 -> DATA4);
85 trans t_DATA4_DATA5_17 (DATA4 -> DATA5);
86 trans t_DATA5_DATA6_18 (DATA5 -> DATA6);
87 trans t_DATA6_DATA7_19 (DATA6 -> DATA7);
88 trans t_DATA7_DATA8_20 (DATA7 -> DATA8);
89 trans t_DATA8_START_21 (DATA8 -> START);
90
91 // bad transitions
92 bad_trans t_HDRDLY_START_08 (HDRDLY -> START);
93 bad_trans t_DATA1_START_12 (DATA1 -> START);
94
95}