[OpenSPARC-T2-DV] / verif / env / common / vera / classes / MCUStub.if.vrh

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: MCUStub.if.vrh
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#ifndef INC__MCUSTUB_IF_VRH
#define INC__MCUSTUB_IF_VRH

#include <defines.vri>

#define MCU_OUTPUT_SKEW  #0
#define MCU_INPUT_SKEW   #-0
#define MCU_OUTPUT_EDGE  NHOLD
#define MCU_INPUT_EDGE   NSAMPLE

interface mcustub_if {

    input       clk      CLOCK    hdl_node "tb_top.cpu.cmp_gclk_c4_mcu0";


#ifndef RTL_NO_BNK01
    /////// MCU 0
    
    // shared signals. shared by 2 BFM instances.
    output [127:0]  mcu_l2b_data_r2_01 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW               hdl_node "tb_top.cpu.mcu0_l2b01_data_r2";     
    output [27:0]   mcu_l2b_ecc_r2_01 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW                hdl_node "tb_top.cpu.mcu0_l2b01_ecc_r2";      

    //l2t0 port
    //  read signals
    input           l2t_mcu_rd_req_0 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t0_mcu0_rd_req";
    input  [39:0]   l2t_mcu_addr_0 MCU_INPUT_EDGE MCU_INPUT_SKEW               hdl_node "tb_top.cpu.l2t0_mcu0_addr";
    input           l2t_mcu_addr_5_0 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t0_mcu0_addr_5";
    input  [2:0]    l2t_mcu_rd_req_id_0 MCU_INPUT_EDGE MCU_INPUT_SKEW          hdl_node "tb_top.cpu.l2t0_mcu0_rd_req_id";
    input           l2t_mcu_rd_dummy_req_0 MCU_INPUT_EDGE MCU_INPUT_SKEW       hdl_node "tb_top.cpu.l2t0_mcu0_rd_dummy_req";
    output          mcu_l2t_rd_ack_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu0_l2t0_rd_ack";
    output [2:0]    mcu_l2t_rd_req_id_r0_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu0_l2t0_rd_req_id_r0";
    output          mcu_l2t_data_vld_r0_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu0_l2t0_data_vld_r0";
    output [1:0]    mcu_l2t_qword_id_r0_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu0_l2t0_qword_id_r0"; 
    output          mcu_l2t_secc_err_r2_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu0_l2t0_secc_err_r2";
    output          mcu_l2t_mecc_err_r2_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu0_l2t0_mecc_err_r2";
    output          mcu_l2t_scb_secc_err_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu0_l2t0_scb_secc_err";
    output          mcu_l2t_scb_mecc_err_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu0_l2t0_scb_mecc_err";

    //  write signals
    input           l2t_mcu_wr_req_0 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t0_mcu0_wr_req";
    output          mcu_l2t_wr_ack_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu0_l2t0_wr_ack";
    input           evict_l2b_mcu_data_vld_r5_0 MCU_INPUT_EDGE MCU_INPUT_SKEW  hdl_node "tb_top.cpu.l2b0_mcu0_data_vld_r5";
    input  [63:0]   evict_l2b_mcu_wr_data_r5_0 MCU_INPUT_EDGE MCU_INPUT_SKEW   hdl_node "tb_top.cpu.l2b0_mcu0_wr_data_r5";   


    //l2t1 port
    //  read signals
    input           l2t_mcu_rd_req_1 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t1_mcu0_rd_req";       
    input  [39:0]   l2t_mcu_addr_1 MCU_INPUT_EDGE MCU_INPUT_SKEW               hdl_node "tb_top.cpu.l2t1_mcu0_addr";         
    input           l2t_mcu_addr_5_1 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t1_mcu0_addr_5";       
    input  [2:0]    l2t_mcu_rd_req_id_1 MCU_INPUT_EDGE MCU_INPUT_SKEW          hdl_node "tb_top.cpu.l2t1_mcu0_rd_req_id";    
    input           l2t_mcu_rd_dummy_req_1 MCU_INPUT_EDGE MCU_INPUT_SKEW       hdl_node "tb_top.cpu.l2t1_mcu0_rd_dummy_req"; 
    output          mcu_l2t_rd_ack_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu0_l2t1_rd_ack";       
    output [2:0]    mcu_l2t_rd_req_id_r0_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu0_l2t1_rd_req_id_r0"; 
    output          mcu_l2t_data_vld_r0_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu0_l2t1_data_vld_r0";  
    output [1:0]    mcu_l2t_qword_id_r0_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu0_l2t1_qword_id_r0";  
    output          mcu_l2t_secc_err_r2_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu0_l2t1_secc_err_r2";  
    output          mcu_l2t_mecc_err_r2_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu0_l2t1_mecc_err_r2";  
    output          mcu_l2t_scb_secc_err_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu0_l2t1_scb_secc_err"; 
    output          mcu_l2t_scb_mecc_err_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu0_l2t1_scb_mecc_err"; 
                                                                                                                                                                        
    //  write signals                                                                                                                              
    input           l2t_mcu_wr_req_1 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t1_mcu0_wr_req";       
    output          mcu_l2t_wr_ack_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu0_l2t1_wr_ack";       
    input           evict_l2b_mcu_data_vld_r5_1 MCU_INPUT_EDGE MCU_INPUT_SKEW  hdl_node "tb_top.cpu.l2b1_mcu0_data_vld_r5";  
    input  [63:0]   evict_l2b_mcu_wr_data_r5_1 MCU_INPUT_EDGE MCU_INPUT_SKEW   hdl_node "tb_top.cpu.l2b1_mcu0_wr_data_r5";   

#endif

    
#ifndef RTL_NO_BNK23
    /////// MCU 1

    // shared signals. shared by 2 BFM instances.
    output [127:0]  mcu_l2b_data_r2_23 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW               hdl_node "tb_top.cpu.mcu1_l2b23_data_r2";     
    output [27:0]   mcu_l2b_ecc_r2_23 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW                hdl_node "tb_top.cpu.mcu1_l2b23_ecc_r2";      

    
    //l2t2 port
    //  read signals
    input           l2t_mcu_rd_req_2 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t2_mcu1_rd_req";       
    input  [39:0]   l2t_mcu_addr_2 MCU_INPUT_EDGE MCU_INPUT_SKEW               hdl_node "tb_top.cpu.l2t2_mcu1_addr";         
    input           l2t_mcu_addr_5_2 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t2_mcu1_addr_5";       
    input  [2:0]    l2t_mcu_rd_req_id_2 MCU_INPUT_EDGE MCU_INPUT_SKEW          hdl_node "tb_top.cpu.l2t2_mcu1_rd_req_id";    
    input           l2t_mcu_rd_dummy_req_2 MCU_INPUT_EDGE MCU_INPUT_SKEW       hdl_node "tb_top.cpu.l2t2_mcu1_rd_dummy_req"; 
    output          mcu_l2t_rd_ack_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu1_l2t2_rd_ack";       
    output [2:0]    mcu_l2t_rd_req_id_r0_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu1_l2t2_rd_req_id_r0"; 
    output          mcu_l2t_data_vld_r0_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu1_l2t2_data_vld_r0";  
    output [1:0]    mcu_l2t_qword_id_r0_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu1_l2t2_qword_id_r0";  
    output          mcu_l2t_secc_err_r2_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu1_l2t2_secc_err_r2";  
    output          mcu_l2t_mecc_err_r2_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu1_l2t2_mecc_err_r2";  
    output          mcu_l2t_scb_secc_err_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu1_l2t2_scb_secc_err"; 
    output          mcu_l2t_scb_mecc_err_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu1_l2t2_scb_mecc_err"; 
                                                                                                                                                                        
    //  write signals                                                                                                                              
    input           l2t_mcu_wr_req_2 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t2_mcu1_wr_req";       
    output          mcu_l2t_wr_ack_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu1_l2t2_wr_ack";       
    input           evict_l2b_mcu_data_vld_r5_2 MCU_INPUT_EDGE MCU_INPUT_SKEW  hdl_node "tb_top.cpu.l2b2_mcu1_data_vld_r5";  
    input  [63:0]   evict_l2b_mcu_wr_data_r5_2 MCU_INPUT_EDGE MCU_INPUT_SKEW   hdl_node "tb_top.cpu.l2b2_mcu1_wr_data_r5";   


    //l2t3 port
    //  read signals
    input           l2t_mcu_rd_req_3 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t3_mcu1_rd_req";       
    input  [39:0]   l2t_mcu_addr_3 MCU_INPUT_EDGE MCU_INPUT_SKEW               hdl_node "tb_top.cpu.l2t3_mcu1_addr";         
    input           l2t_mcu_addr_5_3 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t3_mcu1_addr_5";       
    input  [2:0]    l2t_mcu_rd_req_id_3 MCU_INPUT_EDGE MCU_INPUT_SKEW          hdl_node "tb_top.cpu.l2t3_mcu1_rd_req_id";    
    input           l2t_mcu_rd_dummy_req_3 MCU_INPUT_EDGE MCU_INPUT_SKEW       hdl_node "tb_top.cpu.l2t3_mcu1_rd_dummy_req"; 
    output          mcu_l2t_rd_ack_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu1_l2t3_rd_ack";       
    output [2:0]    mcu_l2t_rd_req_id_r0_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu1_l2t3_rd_req_id_r0"; 
    output          mcu_l2t_data_vld_r0_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu1_l2t3_data_vld_r0";  
    output [1:0]    mcu_l2t_qword_id_r0_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu1_l2t3_qword_id_r0";  
    output          mcu_l2t_secc_err_r2_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu1_l2t3_secc_err_r2";  
    output          mcu_l2t_mecc_err_r2_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu1_l2t3_mecc_err_r2";  
    output          mcu_l2t_scb_secc_err_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu1_l2t3_scb_secc_err"; 
    output          mcu_l2t_scb_mecc_err_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu1_l2t3_scb_mecc_err"; 
                                                                                                                                                                        
    //  write signals                                                                                                                              
    input           l2t_mcu_wr_req_3 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t3_mcu1_wr_req";       
    output          mcu_l2t_wr_ack_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu1_l2t3_wr_ack";       
    input           evict_l2b_mcu_data_vld_r5_3 MCU_INPUT_EDGE MCU_INPUT_SKEW  hdl_node "tb_top.cpu.l2b3_mcu1_data_vld_r5";  
    input  [63:0]   evict_l2b_mcu_wr_data_r5_3 MCU_INPUT_EDGE MCU_INPUT_SKEW   hdl_node "tb_top.cpu.l2b3_mcu1_wr_data_r5";   

#endif

    
#ifndef RTL_NO_BNK45    
    /////// MCU 2

    // shared signals. shared by 2 BFM instances.
    output [127:0]  mcu_l2b_data_r2_45 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW               hdl_node "tb_top.cpu.mcu2_l2b45_data_r2";     
    output [27:0]   mcu_l2b_ecc_r2_45 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW                hdl_node "tb_top.cpu.mcu2_l2b45_ecc_r2";      

    
    //l2t4 port
    //  read signals
    input           l2t_mcu_rd_req_4 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t4_mcu2_rd_req";       
    input  [39:0]   l2t_mcu_addr_4 MCU_INPUT_EDGE MCU_INPUT_SKEW               hdl_node "tb_top.cpu.l2t4_mcu2_addr";         
    input           l2t_mcu_addr_5_4 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t4_mcu2_addr_5";       
    input  [2:0]    l2t_mcu_rd_req_id_4 MCU_INPUT_EDGE MCU_INPUT_SKEW          hdl_node "tb_top.cpu.l2t4_mcu2_rd_req_id";    
    input           l2t_mcu_rd_dummy_req_4 MCU_INPUT_EDGE MCU_INPUT_SKEW       hdl_node "tb_top.cpu.l2t4_mcu2_rd_dummy_req"; 
    output          mcu_l2t_rd_ack_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu2_l2t4_rd_ack";       
    output [2:0]    mcu_l2t_rd_req_id_r0_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu2_l2t4_rd_req_id_r0"; 
    output          mcu_l2t_data_vld_r0_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu2_l2t4_data_vld_r0";  
    output [1:0]    mcu_l2t_qword_id_r0_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu2_l2t4_qword_id_r0";
    output          mcu_l2t_secc_err_r2_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu2_l2t4_secc_err_r2";  
    output          mcu_l2t_mecc_err_r2_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu2_l2t4_mecc_err_r2";  
    output          mcu_l2t_scb_secc_err_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu2_l2t4_scb_secc_err"; 
    output          mcu_l2t_scb_mecc_err_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu2_l2t4_scb_mecc_err"; 
                                                                                                                                                                        
    //  write signals                                                                                                                              
    input           l2t_mcu_wr_req_4 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t4_mcu2_wr_req";       
    output          mcu_l2t_wr_ack_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu2_l2t4_wr_ack";       
    input           evict_l2b_mcu_data_vld_r5_4 MCU_INPUT_EDGE MCU_INPUT_SKEW  hdl_node "tb_top.cpu.l2b4_mcu2_data_vld_r5";  
    input  [63:0]   evict_l2b_mcu_wr_data_r5_4 MCU_INPUT_EDGE MCU_INPUT_SKEW   hdl_node "tb_top.cpu.l2b4_mcu2_wr_data_r5";   


    //l2t5 port
    //  read signals
    input           l2t_mcu_rd_req_5 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t5_mcu2_rd_req";       
    input  [39:0]   l2t_mcu_addr_5 MCU_INPUT_EDGE MCU_INPUT_SKEW               hdl_node "tb_top.cpu.l2t5_mcu2_addr";         
    input           l2t_mcu_addr_5_5 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t5_mcu2_addr_5";       
    input  [2:0]    l2t_mcu_rd_req_id_5 MCU_INPUT_EDGE MCU_INPUT_SKEW          hdl_node "tb_top.cpu.l2t5_mcu2_rd_req_id";    
    input           l2t_mcu_rd_dummy_req_5 MCU_INPUT_EDGE MCU_INPUT_SKEW       hdl_node "tb_top.cpu.l2t5_mcu2_rd_dummy_req"; 
    output          mcu_l2t_rd_ack_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu2_l2t5_rd_ack";       
    output [2:0]    mcu_l2t_rd_req_id_r0_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu2_l2t5_rd_req_id_r0"; 
    output          mcu_l2t_data_vld_r0_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu2_l2t5_data_vld_r0";  
    output [1:0]    mcu_l2t_qword_id_r0_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu2_l2t5_qword_id_r0";  
    output          mcu_l2t_secc_err_r2_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu2_l2t5_secc_err_r2";  
    output          mcu_l2t_mecc_err_r2_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu2_l2t5_mecc_err_r2";  
    output          mcu_l2t_scb_secc_err_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu2_l2t5_scb_secc_err"; 
    output          mcu_l2t_scb_mecc_err_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu2_l2t5_scb_mecc_err"; 
                                                                                                                                                                        
    //  write signals                                                                                                                              
    input           l2t_mcu_wr_req_5 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t5_mcu2_wr_req";       
    output          mcu_l2t_wr_ack_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu2_l2t5_wr_ack";       
    input           evict_l2b_mcu_data_vld_r5_5 MCU_INPUT_EDGE MCU_INPUT_SKEW  hdl_node "tb_top.cpu.l2b5_mcu2_data_vld_r5";  
    input  [63:0]   evict_l2b_mcu_wr_data_r5_5 MCU_INPUT_EDGE MCU_INPUT_SKEW   hdl_node "tb_top.cpu.l2b5_mcu2_wr_data_r5";   

#endif


#ifndef RTL_NO_BNK67    
    /////// MCU 3

    // shared signals. shared by 2 BFM instances.
    output [127:0]  mcu_l2b_data_r2_67 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW               hdl_node "tb_top.cpu.mcu3_l2b67_data_r2";     
    output [27:0]   mcu_l2b_ecc_r2_67 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW                hdl_node "tb_top.cpu.mcu3_l2b67_ecc_r2";      


    //l2t6 port
    //  read signals
    input           l2t_mcu_rd_req_6 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t6_mcu3_rd_req";       
    input  [39:0]   l2t_mcu_addr_6 MCU_INPUT_EDGE MCU_INPUT_SKEW               hdl_node "tb_top.cpu.l2t6_mcu3_addr";         
    input           l2t_mcu_addr_5_6 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t6_mcu3_addr_5";       
    input  [2:0]    l2t_mcu_rd_req_id_6 MCU_INPUT_EDGE MCU_INPUT_SKEW          hdl_node "tb_top.cpu.l2t6_mcu3_rd_req_id";    
    input           l2t_mcu_rd_dummy_req_6 MCU_INPUT_EDGE MCU_INPUT_SKEW       hdl_node "tb_top.cpu.l2t6_mcu3_rd_dummy_req"; 
    output          mcu_l2t_rd_ack_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu3_l2t6_rd_ack";       
    output [2:0]    mcu_l2t_rd_req_id_r0_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu3_l2t6_rd_req_id_r0"; 
    output          mcu_l2t_data_vld_r0_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu3_l2t6_data_vld_r0";  
    output [1:0]    mcu_l2t_qword_id_r0_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu3_l2t6_qword_id_r0";  
    output          mcu_l2t_secc_err_r2_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu3_l2t6_secc_err_r2";  
    output          mcu_l2t_mecc_err_r2_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu3_l2t6_mecc_err_r2";  
    output          mcu_l2t_scb_secc_err_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu3_l2t6_scb_secc_err"; 
    output          mcu_l2t_scb_mecc_err_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu3_l2t6_scb_mecc_err"; 
                                                                                                                                                                        
    //  write signals                                                                                                                              
    input           l2t_mcu_wr_req_6 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t6_mcu3_wr_req";       
    output          mcu_l2t_wr_ack_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu3_l2t6_wr_ack";       
    input           evict_l2b_mcu_data_vld_r5_6 MCU_INPUT_EDGE MCU_INPUT_SKEW  hdl_node "tb_top.cpu.l2b6_mcu3_data_vld_r5";  
    input  [63:0]   evict_l2b_mcu_wr_data_r5_6 MCU_INPUT_EDGE MCU_INPUT_SKEW   hdl_node "tb_top.cpu.l2b6_mcu3_wr_data_r5";   


    //l2t7 port
    //  read signals
    input           l2t_mcu_rd_req_7 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t7_mcu3_rd_req";       
    input  [39:0]   l2t_mcu_addr_7 MCU_INPUT_EDGE MCU_INPUT_SKEW               hdl_node "tb_top.cpu.l2t7_mcu3_addr";         
    input           l2t_mcu_addr_5_7 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t7_mcu3_addr_5";       
    input  [2:0]    l2t_mcu_rd_req_id_7 MCU_INPUT_EDGE MCU_INPUT_SKEW          hdl_node "tb_top.cpu.l2t7_mcu3_rd_req_id";    
    input           l2t_mcu_rd_dummy_req_7 MCU_INPUT_EDGE MCU_INPUT_SKEW       hdl_node "tb_top.cpu.l2t7_mcu3_rd_dummy_req"; 
    output          mcu_l2t_rd_ack_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu3_l2t7_rd_ack";       
    output [2:0]    mcu_l2t_rd_req_id_r0_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu3_l2t7_rd_req_id_r0"; 
    output          mcu_l2t_data_vld_r0_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu3_l2t7_data_vld_r0";  
    output [1:0]    mcu_l2t_qword_id_r0_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu3_l2t7_qword_id_r0";  
    output          mcu_l2t_secc_err_r2_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu3_l2t7_secc_err_r2";  
    output          mcu_l2t_mecc_err_r2_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu3_l2t7_mecc_err_r2";  
    output          mcu_l2t_scb_secc_err_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu3_l2t7_scb_secc_err"; 
    output          mcu_l2t_scb_mecc_err_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu3_l2t7_scb_mecc_err"; 
                                                                                                                                                                        
    //  write signals                                                                                                                              
    input           l2t_mcu_wr_req_7 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t7_mcu3_wr_req";       
    output          mcu_l2t_wr_ack_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu3_l2t7_wr_ack";       
    input           evict_l2b_mcu_data_vld_r5_7 MCU_INPUT_EDGE MCU_INPUT_SKEW  hdl_node "tb_top.cpu.l2b7_mcu3_data_vld_r5";  
    input  [63:0]   evict_l2b_mcu_wr_data_r5_7 MCU_INPUT_EDGE MCU_INPUT_SKEW   hdl_node "tb_top.cpu.l2b7_mcu3_wr_data_r5";   

#endif
    
}

#endif
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: MCUStub.if.vrh
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	#ifndef INC__MCUSTUB_IF_VRH
	36	#define INC__MCUSTUB_IF_VRH
	37
	38	#include <defines.vri>
	39
	40	#define MCU_OUTPUT_SKEW #0
	41	#define MCU_INPUT_SKEW #-0
	42	#define MCU_OUTPUT_EDGE NHOLD
	43	#define MCU_INPUT_EDGE NSAMPLE
	44
	45	interface mcustub_if {
	46
	47	input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c4_mcu0";
	48
	49
	50	#ifndef RTL_NO_BNK01
	51	/////// MCU 0
	52
	53	// shared signals. shared by 2 BFM instances.
	54	output [127:0] mcu_l2b_data_r2_01 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu0_l2b01_data_r2";
	55	output [27:0] mcu_l2b_ecc_r2_01 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu0_l2b01_ecc_r2";
	56
	57	//l2t0 port
	58	// read signals
	59	input l2t_mcu_rd_req_0 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t0_mcu0_rd_req";
	60	input [39:0] l2t_mcu_addr_0 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t0_mcu0_addr";
	61	input l2t_mcu_addr_5_0 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t0_mcu0_addr_5";
	62	input [2:0] l2t_mcu_rd_req_id_0 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t0_mcu0_rd_req_id";
	63	input l2t_mcu_rd_dummy_req_0 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t0_mcu0_rd_dummy_req";
	64	output mcu_l2t_rd_ack_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu0_l2t0_rd_ack";
65	output [2:0] mcu_l2t_rd_req_id_r0_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu0_l2t0_rd_req_id_r0";
66	output mcu_l2t_data_vld_r0_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu0_l2t0_data_vld_r0";
67	output [1:0] mcu_l2t_qword_id_r0_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu0_l2t0_qword_id_r0";
68	output mcu_l2t_secc_err_r2_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu0_l2t0_secc_err_r2";
69	output mcu_l2t_mecc_err_r2_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu0_l2t0_mecc_err_r2";
70	output mcu_l2t_scb_secc_err_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu0_l2t0_scb_secc_err";
71	output mcu_l2t_scb_mecc_err_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu0_l2t0_scb_mecc_err";
72
73	// write signals
74	input l2t_mcu_wr_req_0 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t0_mcu0_wr_req";
75	output mcu_l2t_wr_ack_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu0_l2t0_wr_ack";
76	input evict_l2b_mcu_data_vld_r5_0 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2b0_mcu0_data_vld_r5";
77	input [63:0] evict_l2b_mcu_wr_data_r5_0 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2b0_mcu0_wr_data_r5";
78
79
80	//l2t1 port
81	// read signals
82	input l2t_mcu_rd_req_1 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t1_mcu0_rd_req";
83	input [39:0] l2t_mcu_addr_1 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t1_mcu0_addr";
84	input l2t_mcu_addr_5_1 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t1_mcu0_addr_5";
85	input [2:0] l2t_mcu_rd_req_id_1 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t1_mcu0_rd_req_id";
86	input l2t_mcu_rd_dummy_req_1 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t1_mcu0_rd_dummy_req";
87	output mcu_l2t_rd_ack_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu0_l2t1_rd_ack";
88	output [2:0] mcu_l2t_rd_req_id_r0_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu0_l2t1_rd_req_id_r0";
89	output mcu_l2t_data_vld_r0_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu0_l2t1_data_vld_r0";
90	output [1:0] mcu_l2t_qword_id_r0_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu0_l2t1_qword_id_r0";
91	output mcu_l2t_secc_err_r2_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu0_l2t1_secc_err_r2";
92	output mcu_l2t_mecc_err_r2_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu0_l2t1_mecc_err_r2";
93	output mcu_l2t_scb_secc_err_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu0_l2t1_scb_secc_err";
94	output mcu_l2t_scb_mecc_err_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu0_l2t1_scb_mecc_err";
95
96	// write signals
97	input l2t_mcu_wr_req_1 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t1_mcu0_wr_req";
98	output mcu_l2t_wr_ack_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu0_l2t1_wr_ack";
99	input evict_l2b_mcu_data_vld_r5_1 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2b1_mcu0_data_vld_r5";
100	input [63:0] evict_l2b_mcu_wr_data_r5_1 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2b1_mcu0_wr_data_r5";
101
102	#endif
103
104
105	#ifndef RTL_NO_BNK23
106	/////// MCU 1
107
108	// shared signals. shared by 2 BFM instances.
109	output [127:0] mcu_l2b_data_r2_23 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu1_l2b23_data_r2";
110	output [27:0] mcu_l2b_ecc_r2_23 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu1_l2b23_ecc_r2";
111
112
113	//l2t2 port
114	// read signals
115	input l2t_mcu_rd_req_2 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t2_mcu1_rd_req";
116	input [39:0] l2t_mcu_addr_2 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t2_mcu1_addr";
117	input l2t_mcu_addr_5_2 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t2_mcu1_addr_5";
118	input [2:0] l2t_mcu_rd_req_id_2 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t2_mcu1_rd_req_id";
119	input l2t_mcu_rd_dummy_req_2 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t2_mcu1_rd_dummy_req";
120	output mcu_l2t_rd_ack_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu1_l2t2_rd_ack";
121	output [2:0] mcu_l2t_rd_req_id_r0_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu1_l2t2_rd_req_id_r0";
122	output mcu_l2t_data_vld_r0_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu1_l2t2_data_vld_r0";
123	output [1:0] mcu_l2t_qword_id_r0_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu1_l2t2_qword_id_r0";
124	output mcu_l2t_secc_err_r2_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu1_l2t2_secc_err_r2";
125	output mcu_l2t_mecc_err_r2_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu1_l2t2_mecc_err_r2";
126	output mcu_l2t_scb_secc_err_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu1_l2t2_scb_secc_err";
127	output mcu_l2t_scb_mecc_err_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu1_l2t2_scb_mecc_err";
128
129	// write signals
130	input l2t_mcu_wr_req_2 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t2_mcu1_wr_req";
131	output mcu_l2t_wr_ack_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu1_l2t2_wr_ack";
132	input evict_l2b_mcu_data_vld_r5_2 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2b2_mcu1_data_vld_r5";
133	input [63:0] evict_l2b_mcu_wr_data_r5_2 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2b2_mcu1_wr_data_r5";
134
135
136
137	//l2t3 port
138	// read signals
139	input l2t_mcu_rd_req_3 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t3_mcu1_rd_req";
140	input [39:0] l2t_mcu_addr_3 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t3_mcu1_addr";
141	input l2t_mcu_addr_5_3 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t3_mcu1_addr_5";
142	input [2:0] l2t_mcu_rd_req_id_3 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t3_mcu1_rd_req_id";
143	input l2t_mcu_rd_dummy_req_3 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t3_mcu1_rd_dummy_req";
144	output mcu_l2t_rd_ack_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu1_l2t3_rd_ack";
145	output [2:0] mcu_l2t_rd_req_id_r0_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu1_l2t3_rd_req_id_r0";
146	output mcu_l2t_data_vld_r0_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu1_l2t3_data_vld_r0";
147	output [1:0] mcu_l2t_qword_id_r0_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu1_l2t3_qword_id_r0";
148	output mcu_l2t_secc_err_r2_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu1_l2t3_secc_err_r2";
149	output mcu_l2t_mecc_err_r2_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu1_l2t3_mecc_err_r2";
150	output mcu_l2t_scb_secc_err_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu1_l2t3_scb_secc_err";
151	output mcu_l2t_scb_mecc_err_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu1_l2t3_scb_mecc_err";
152
153	// write signals
154	input l2t_mcu_wr_req_3 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t3_mcu1_wr_req";
155	output mcu_l2t_wr_ack_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu1_l2t3_wr_ack";
156	input evict_l2b_mcu_data_vld_r5_3 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2b3_mcu1_data_vld_r5";
157	input [63:0] evict_l2b_mcu_wr_data_r5_3 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2b3_mcu1_wr_data_r5";
158
159	#endif
160
161
162	#ifndef RTL_NO_BNK45
163	/////// MCU 2
164
165	// shared signals. shared by 2 BFM instances.
166	output [127:0] mcu_l2b_data_r2_45 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu2_l2b45_data_r2";
167	output [27:0] mcu_l2b_ecc_r2_45 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu2_l2b45_ecc_r2";
168
169
170	//l2t4 port
171	// read signals
172	input l2t_mcu_rd_req_4 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t4_mcu2_rd_req";
173	input [39:0] l2t_mcu_addr_4 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t4_mcu2_addr";
174	input l2t_mcu_addr_5_4 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t4_mcu2_addr_5";
175	input [2:0] l2t_mcu_rd_req_id_4 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t4_mcu2_rd_req_id";
176	input l2t_mcu_rd_dummy_req_4 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t4_mcu2_rd_dummy_req";
177	output mcu_l2t_rd_ack_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu2_l2t4_rd_ack";
178	output [2:0] mcu_l2t_rd_req_id_r0_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu2_l2t4_rd_req_id_r0";
179	output mcu_l2t_data_vld_r0_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu2_l2t4_data_vld_r0";
180	output [1:0] mcu_l2t_qword_id_r0_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu2_l2t4_qword_id_r0";
181	output mcu_l2t_secc_err_r2_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu2_l2t4_secc_err_r2";
182	output mcu_l2t_mecc_err_r2_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu2_l2t4_mecc_err_r2";
183	output mcu_l2t_scb_secc_err_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu2_l2t4_scb_secc_err";
184	output mcu_l2t_scb_mecc_err_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu2_l2t4_scb_mecc_err";
185
186	// write signals
187	input l2t_mcu_wr_req_4 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t4_mcu2_wr_req";
188	output mcu_l2t_wr_ack_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu2_l2t4_wr_ack";
189	input evict_l2b_mcu_data_vld_r5_4 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2b4_mcu2_data_vld_r5";
190	input [63:0] evict_l2b_mcu_wr_data_r5_4 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2b4_mcu2_wr_data_r5";
191
192
193	//l2t5 port
194	// read signals
195	input l2t_mcu_rd_req_5 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t5_mcu2_rd_req";
196	input [39:0] l2t_mcu_addr_5 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t5_mcu2_addr";
197	input l2t_mcu_addr_5_5 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t5_mcu2_addr_5";
198	input [2:0] l2t_mcu_rd_req_id_5 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t5_mcu2_rd_req_id";
199	input l2t_mcu_rd_dummy_req_5 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t5_mcu2_rd_dummy_req";
200	output mcu_l2t_rd_ack_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu2_l2t5_rd_ack";
201	output [2:0] mcu_l2t_rd_req_id_r0_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu2_l2t5_rd_req_id_r0";
202	output mcu_l2t_data_vld_r0_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu2_l2t5_data_vld_r0";
203	output [1:0] mcu_l2t_qword_id_r0_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu2_l2t5_qword_id_r0";
204	output mcu_l2t_secc_err_r2_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu2_l2t5_secc_err_r2";
205	output mcu_l2t_mecc_err_r2_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu2_l2t5_mecc_err_r2";
206	output mcu_l2t_scb_secc_err_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu2_l2t5_scb_secc_err";
207	output mcu_l2t_scb_mecc_err_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu2_l2t5_scb_mecc_err";
208
209	// write signals
210	input l2t_mcu_wr_req_5 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t5_mcu2_wr_req";
211	output mcu_l2t_wr_ack_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu2_l2t5_wr_ack";
212	input evict_l2b_mcu_data_vld_r5_5 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2b5_mcu2_data_vld_r5";
213	input [63:0] evict_l2b_mcu_wr_data_r5_5 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2b5_mcu2_wr_data_r5";
214
215	#endif
216
217
218	#ifndef RTL_NO_BNK67
219	/////// MCU 3
220
221	// shared signals. shared by 2 BFM instances.
222	output [127:0] mcu_l2b_data_r2_67 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu3_l2b67_data_r2";
223	output [27:0] mcu_l2b_ecc_r2_67 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu3_l2b67_ecc_r2";
224
225
226	//l2t6 port
227	// read signals
228	input l2t_mcu_rd_req_6 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t6_mcu3_rd_req";
229	input [39:0] l2t_mcu_addr_6 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t6_mcu3_addr";
230	input l2t_mcu_addr_5_6 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t6_mcu3_addr_5";
231	input [2:0] l2t_mcu_rd_req_id_6 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t6_mcu3_rd_req_id";
232	input l2t_mcu_rd_dummy_req_6 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t6_mcu3_rd_dummy_req";
233	output mcu_l2t_rd_ack_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu3_l2t6_rd_ack";
234	output [2:0] mcu_l2t_rd_req_id_r0_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu3_l2t6_rd_req_id_r0";
235	output mcu_l2t_data_vld_r0_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu3_l2t6_data_vld_r0";
236	output [1:0] mcu_l2t_qword_id_r0_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu3_l2t6_qword_id_r0";
237	output mcu_l2t_secc_err_r2_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu3_l2t6_secc_err_r2";
238	output mcu_l2t_mecc_err_r2_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu3_l2t6_mecc_err_r2";
239	output mcu_l2t_scb_secc_err_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu3_l2t6_scb_secc_err";
240	output mcu_l2t_scb_mecc_err_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu3_l2t6_scb_mecc_err";
241
242	// write signals
243	input l2t_mcu_wr_req_6 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t6_mcu3_wr_req";
244	output mcu_l2t_wr_ack_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu3_l2t6_wr_ack";
245	input evict_l2b_mcu_data_vld_r5_6 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2b6_mcu3_data_vld_r5";
246	input [63:0] evict_l2b_mcu_wr_data_r5_6 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2b6_mcu3_wr_data_r5";
247
248
249
250	//l2t7 port
251	// read signals
252	input l2t_mcu_rd_req_7 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t7_mcu3_rd_req";
253	input [39:0] l2t_mcu_addr_7 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t7_mcu3_addr";
254	input l2t_mcu_addr_5_7 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t7_mcu3_addr_5";
255	input [2:0] l2t_mcu_rd_req_id_7 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t7_mcu3_rd_req_id";
256	input l2t_mcu_rd_dummy_req_7 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t7_mcu3_rd_dummy_req";
257	output mcu_l2t_rd_ack_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu3_l2t7_rd_ack";
258	output [2:0] mcu_l2t_rd_req_id_r0_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu3_l2t7_rd_req_id_r0";
259	output mcu_l2t_data_vld_r0_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu3_l2t7_data_vld_r0";
260	output [1:0] mcu_l2t_qword_id_r0_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu3_l2t7_qword_id_r0";
261	output mcu_l2t_secc_err_r2_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu3_l2t7_secc_err_r2";
262	output mcu_l2t_mecc_err_r2_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu3_l2t7_mecc_err_r2";
263	output mcu_l2t_scb_secc_err_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu3_l2t7_scb_secc_err";
264	output mcu_l2t_scb_mecc_err_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu3_l2t7_scb_mecc_err";
265
266	// write signals
267	input l2t_mcu_wr_req_7 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2t7_mcu3_wr_req";
268	output mcu_l2t_wr_ack_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW hdl_node "tb_top.cpu.mcu3_l2t7_wr_ack";
269	input evict_l2b_mcu_data_vld_r5_7 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2b7_mcu3_data_vld_r5";
270	input [63:0] evict_l2b_mcu_wr_data_r5_7 MCU_INPUT_EDGE MCU_INPUT_SKEW hdl_node "tb_top.cpu.l2b7_mcu3_wr_data_r5";
271
272	#endif
273
274	}
275
276	#endif