verif/env/common/vera/classes/MCUStub.if.vrh

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: MCUStub.if.vrh
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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// it under the terms of the GNU General Public License as published by
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
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// along with this program; if not, write to the Free Software
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// ========== Copyright Header End ============================================
#ifndef INC__MCUSTUB_IF_VRH
#define INC__MCUSTUB_IF_VRH

#include <defines.vri>

#define MCU_OUTPUT_SKEW  #0
#define MCU_INPUT_SKEW   #-0
#define MCU_OUTPUT_EDGE  NHOLD
#define MCU_INPUT_EDGE   NSAMPLE

interface mcustub_if {

    input       clk      CLOCK    hdl_node "tb_top.cpu.cmp_gclk_c4_mcu0";


#ifndef RTL_NO_BNK01
    /////// MCU 0

    // shared signals. shared by 2 BFM instances.
    output [127:0]  mcu_l2b_data_r2_01 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW               hdl_node "tb_top.cpu.mcu0_l2b01_data_r2";
    output [27:0]   mcu_l2b_ecc_r2_01 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW                hdl_node "tb_top.cpu.mcu0_l2b01_ecc_r2";

    //l2t0 port
    //  read signals
    input           l2t_mcu_rd_req_0 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t0_mcu0_rd_req";
    input  [39:0]   l2t_mcu_addr_0 MCU_INPUT_EDGE MCU_INPUT_SKEW               hdl_node "tb_top.cpu.l2t0_mcu0_addr";
    input           l2t_mcu_addr_5_0 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t0_mcu0_addr_5";
    input  [2:0]    l2t_mcu_rd_req_id_0 MCU_INPUT_EDGE MCU_INPUT_SKEW          hdl_node "tb_top.cpu.l2t0_mcu0_rd_req_id";
    input           l2t_mcu_rd_dummy_req_0 MCU_INPUT_EDGE MCU_INPUT_SKEW       hdl_node "tb_top.cpu.l2t0_mcu0_rd_dummy_req";
    output          mcu_l2t_rd_ack_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu0_l2t0_rd_ack";
    output [2:0]    mcu_l2t_rd_req_id_r0_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu0_l2t0_rd_req_id_r0";
    output          mcu_l2t_data_vld_r0_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu0_l2t0_data_vld_r0";
    output [1:0]    mcu_l2t_qword_id_r0_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu0_l2t0_qword_id_r0";
    output          mcu_l2t_secc_err_r2_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu0_l2t0_secc_err_r2";
    output          mcu_l2t_mecc_err_r2_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu0_l2t0_mecc_err_r2";
    output          mcu_l2t_scb_secc_err_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu0_l2t0_scb_secc_err";
    output          mcu_l2t_scb_mecc_err_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu0_l2t0_scb_mecc_err";

    //  write signals
    input           l2t_mcu_wr_req_0 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t0_mcu0_wr_req";
    output          mcu_l2t_wr_ack_0 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu0_l2t0_wr_ack";
    input           evict_l2b_mcu_data_vld_r5_0 MCU_INPUT_EDGE MCU_INPUT_SKEW  hdl_node "tb_top.cpu.l2b0_mcu0_data_vld_r5";
    input  [63:0]   evict_l2b_mcu_wr_data_r5_0 MCU_INPUT_EDGE MCU_INPUT_SKEW   hdl_node "tb_top.cpu.l2b0_mcu0_wr_data_r5";


    //l2t1 port
    //  read signals
    input           l2t_mcu_rd_req_1 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t1_mcu0_rd_req";
    input  [39:0]   l2t_mcu_addr_1 MCU_INPUT_EDGE MCU_INPUT_SKEW               hdl_node "tb_top.cpu.l2t1_mcu0_addr";
    input           l2t_mcu_addr_5_1 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t1_mcu0_addr_5";
    input  [2:0]    l2t_mcu_rd_req_id_1 MCU_INPUT_EDGE MCU_INPUT_SKEW          hdl_node "tb_top.cpu.l2t1_mcu0_rd_req_id";
    input           l2t_mcu_rd_dummy_req_1 MCU_INPUT_EDGE MCU_INPUT_SKEW       hdl_node "tb_top.cpu.l2t1_mcu0_rd_dummy_req";
    output          mcu_l2t_rd_ack_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu0_l2t1_rd_ack";
    output [2:0]    mcu_l2t_rd_req_id_r0_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu0_l2t1_rd_req_id_r0";
    output          mcu_l2t_data_vld_r0_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu0_l2t1_data_vld_r0";
    output [1:0]    mcu_l2t_qword_id_r0_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu0_l2t1_qword_id_r0";
    output          mcu_l2t_secc_err_r2_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu0_l2t1_secc_err_r2";
    output          mcu_l2t_mecc_err_r2_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu0_l2t1_mecc_err_r2";
    output          mcu_l2t_scb_secc_err_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu0_l2t1_scb_secc_err";
    output          mcu_l2t_scb_mecc_err_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu0_l2t1_scb_mecc_err";

    //  write signals
    input           l2t_mcu_wr_req_1 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t1_mcu0_wr_req";
    output          mcu_l2t_wr_ack_1 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu0_l2t1_wr_ack";
    input           evict_l2b_mcu_data_vld_r5_1 MCU_INPUT_EDGE MCU_INPUT_SKEW  hdl_node "tb_top.cpu.l2b1_mcu0_data_vld_r5";
    input  [63:0]   evict_l2b_mcu_wr_data_r5_1 MCU_INPUT_EDGE MCU_INPUT_SKEW   hdl_node "tb_top.cpu.l2b1_mcu0_wr_data_r5";

#endif


#ifndef RTL_NO_BNK23
    /////// MCU 1

    // shared signals. shared by 2 BFM instances.
    output [127:0]  mcu_l2b_data_r2_23 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW               hdl_node "tb_top.cpu.mcu1_l2b23_data_r2";
    output [27:0]   mcu_l2b_ecc_r2_23 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW                hdl_node "tb_top.cpu.mcu1_l2b23_ecc_r2";


    //l2t2 port
    //  read signals
    input           l2t_mcu_rd_req_2 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t2_mcu1_rd_req";
    input  [39:0]   l2t_mcu_addr_2 MCU_INPUT_EDGE MCU_INPUT_SKEW               hdl_node "tb_top.cpu.l2t2_mcu1_addr";
    input           l2t_mcu_addr_5_2 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t2_mcu1_addr_5";
    input  [2:0]    l2t_mcu_rd_req_id_2 MCU_INPUT_EDGE MCU_INPUT_SKEW          hdl_node "tb_top.cpu.l2t2_mcu1_rd_req_id";
    input           l2t_mcu_rd_dummy_req_2 MCU_INPUT_EDGE MCU_INPUT_SKEW       hdl_node "tb_top.cpu.l2t2_mcu1_rd_dummy_req";
    output          mcu_l2t_rd_ack_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu1_l2t2_rd_ack";
    output [2:0]    mcu_l2t_rd_req_id_r0_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu1_l2t2_rd_req_id_r0";
    output          mcu_l2t_data_vld_r0_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu1_l2t2_data_vld_r0";
    output [1:0]    mcu_l2t_qword_id_r0_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu1_l2t2_qword_id_r0";
    output          mcu_l2t_secc_err_r2_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu1_l2t2_secc_err_r2";
    output          mcu_l2t_mecc_err_r2_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu1_l2t2_mecc_err_r2";
    output          mcu_l2t_scb_secc_err_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu1_l2t2_scb_secc_err";
    output          mcu_l2t_scb_mecc_err_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu1_l2t2_scb_mecc_err";

    //  write signals
    input           l2t_mcu_wr_req_2 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t2_mcu1_wr_req";
    output          mcu_l2t_wr_ack_2 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu1_l2t2_wr_ack";
    input           evict_l2b_mcu_data_vld_r5_2 MCU_INPUT_EDGE MCU_INPUT_SKEW  hdl_node "tb_top.cpu.l2b2_mcu1_data_vld_r5";
    input  [63:0]   evict_l2b_mcu_wr_data_r5_2 MCU_INPUT_EDGE MCU_INPUT_SKEW   hdl_node "tb_top.cpu.l2b2_mcu1_wr_data_r5";


    //l2t3 port
    //  read signals
    input           l2t_mcu_rd_req_3 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t3_mcu1_rd_req";
    input  [39:0]   l2t_mcu_addr_3 MCU_INPUT_EDGE MCU_INPUT_SKEW               hdl_node "tb_top.cpu.l2t3_mcu1_addr";
    input           l2t_mcu_addr_5_3 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t3_mcu1_addr_5";
    input  [2:0]    l2t_mcu_rd_req_id_3 MCU_INPUT_EDGE MCU_INPUT_SKEW          hdl_node "tb_top.cpu.l2t3_mcu1_rd_req_id";
    input           l2t_mcu_rd_dummy_req_3 MCU_INPUT_EDGE MCU_INPUT_SKEW       hdl_node "tb_top.cpu.l2t3_mcu1_rd_dummy_req";
    output          mcu_l2t_rd_ack_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu1_l2t3_rd_ack";
    output [2:0]    mcu_l2t_rd_req_id_r0_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu1_l2t3_rd_req_id_r0";
    output          mcu_l2t_data_vld_r0_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu1_l2t3_data_vld_r0";
    output [1:0]    mcu_l2t_qword_id_r0_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu1_l2t3_qword_id_r0";
    output          mcu_l2t_secc_err_r2_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu1_l2t3_secc_err_r2";
    output          mcu_l2t_mecc_err_r2_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu1_l2t3_mecc_err_r2";
    output          mcu_l2t_scb_secc_err_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu1_l2t3_scb_secc_err";
    output          mcu_l2t_scb_mecc_err_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu1_l2t3_scb_mecc_err";

    //  write signals
    input           l2t_mcu_wr_req_3 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t3_mcu1_wr_req";
    output          mcu_l2t_wr_ack_3 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu1_l2t3_wr_ack";
    input           evict_l2b_mcu_data_vld_r5_3 MCU_INPUT_EDGE MCU_INPUT_SKEW  hdl_node "tb_top.cpu.l2b3_mcu1_data_vld_r5";
    input  [63:0]   evict_l2b_mcu_wr_data_r5_3 MCU_INPUT_EDGE MCU_INPUT_SKEW   hdl_node "tb_top.cpu.l2b3_mcu1_wr_data_r5";

#endif


#ifndef RTL_NO_BNK45
    /////// MCU 2

    // shared signals. shared by 2 BFM instances.
    output [127:0]  mcu_l2b_data_r2_45 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW               hdl_node "tb_top.cpu.mcu2_l2b45_data_r2";
    output [27:0]   mcu_l2b_ecc_r2_45 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW                hdl_node "tb_top.cpu.mcu2_l2b45_ecc_r2";


    //l2t4 port
    //  read signals
    input           l2t_mcu_rd_req_4 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t4_mcu2_rd_req";
    input  [39:0]   l2t_mcu_addr_4 MCU_INPUT_EDGE MCU_INPUT_SKEW               hdl_node "tb_top.cpu.l2t4_mcu2_addr";
    input           l2t_mcu_addr_5_4 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t4_mcu2_addr_5";
    input  [2:0]    l2t_mcu_rd_req_id_4 MCU_INPUT_EDGE MCU_INPUT_SKEW          hdl_node "tb_top.cpu.l2t4_mcu2_rd_req_id";
    input           l2t_mcu_rd_dummy_req_4 MCU_INPUT_EDGE MCU_INPUT_SKEW       hdl_node "tb_top.cpu.l2t4_mcu2_rd_dummy_req";
    output          mcu_l2t_rd_ack_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu2_l2t4_rd_ack";
    output [2:0]    mcu_l2t_rd_req_id_r0_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu2_l2t4_rd_req_id_r0";
    output          mcu_l2t_data_vld_r0_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu2_l2t4_data_vld_r0";
    output [1:0]    mcu_l2t_qword_id_r0_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu2_l2t4_qword_id_r0";
    output          mcu_l2t_secc_err_r2_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu2_l2t4_secc_err_r2";
    output          mcu_l2t_mecc_err_r2_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu2_l2t4_mecc_err_r2";
    output          mcu_l2t_scb_secc_err_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu2_l2t4_scb_secc_err";
    output          mcu_l2t_scb_mecc_err_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu2_l2t4_scb_mecc_err";

    //  write signals
    input           l2t_mcu_wr_req_4 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t4_mcu2_wr_req";
    output          mcu_l2t_wr_ack_4 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu2_l2t4_wr_ack";
    input           evict_l2b_mcu_data_vld_r5_4 MCU_INPUT_EDGE MCU_INPUT_SKEW  hdl_node "tb_top.cpu.l2b4_mcu2_data_vld_r5";
    input  [63:0]   evict_l2b_mcu_wr_data_r5_4 MCU_INPUT_EDGE MCU_INPUT_SKEW   hdl_node "tb_top.cpu.l2b4_mcu2_wr_data_r5";


    //l2t5 port
    //  read signals
    input           l2t_mcu_rd_req_5 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t5_mcu2_rd_req";
    input  [39:0]   l2t_mcu_addr_5 MCU_INPUT_EDGE MCU_INPUT_SKEW               hdl_node "tb_top.cpu.l2t5_mcu2_addr";
    input           l2t_mcu_addr_5_5 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t5_mcu2_addr_5";
    input  [2:0]    l2t_mcu_rd_req_id_5 MCU_INPUT_EDGE MCU_INPUT_SKEW          hdl_node "tb_top.cpu.l2t5_mcu2_rd_req_id";
    input           l2t_mcu_rd_dummy_req_5 MCU_INPUT_EDGE MCU_INPUT_SKEW       hdl_node "tb_top.cpu.l2t5_mcu2_rd_dummy_req";
    output          mcu_l2t_rd_ack_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu2_l2t5_rd_ack";
    output [2:0]    mcu_l2t_rd_req_id_r0_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu2_l2t5_rd_req_id_r0";
    output          mcu_l2t_data_vld_r0_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu2_l2t5_data_vld_r0";
    output [1:0]    mcu_l2t_qword_id_r0_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu2_l2t5_qword_id_r0";
    output          mcu_l2t_secc_err_r2_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu2_l2t5_secc_err_r2";
    output          mcu_l2t_mecc_err_r2_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu2_l2t5_mecc_err_r2";
    output          mcu_l2t_scb_secc_err_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu2_l2t5_scb_secc_err";
    output          mcu_l2t_scb_mecc_err_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu2_l2t5_scb_mecc_err";

    //  write signals
    input           l2t_mcu_wr_req_5 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t5_mcu2_wr_req";
    output          mcu_l2t_wr_ack_5 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu2_l2t5_wr_ack";
    input           evict_l2b_mcu_data_vld_r5_5 MCU_INPUT_EDGE MCU_INPUT_SKEW  hdl_node "tb_top.cpu.l2b5_mcu2_data_vld_r5";
    input  [63:0]   evict_l2b_mcu_wr_data_r5_5 MCU_INPUT_EDGE MCU_INPUT_SKEW   hdl_node "tb_top.cpu.l2b5_mcu2_wr_data_r5";

#endif


#ifndef RTL_NO_BNK67
    /////// MCU 3

    // shared signals. shared by 2 BFM instances.
    output [127:0]  mcu_l2b_data_r2_67 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW               hdl_node "tb_top.cpu.mcu3_l2b67_data_r2";
    output [27:0]   mcu_l2b_ecc_r2_67 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW                hdl_node "tb_top.cpu.mcu3_l2b67_ecc_r2";


    //l2t6 port
    //  read signals
    input           l2t_mcu_rd_req_6 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t6_mcu3_rd_req";
    input  [39:0]   l2t_mcu_addr_6 MCU_INPUT_EDGE MCU_INPUT_SKEW               hdl_node "tb_top.cpu.l2t6_mcu3_addr";
    input           l2t_mcu_addr_5_6 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t6_mcu3_addr_5";
    input  [2:0]    l2t_mcu_rd_req_id_6 MCU_INPUT_EDGE MCU_INPUT_SKEW          hdl_node "tb_top.cpu.l2t6_mcu3_rd_req_id";
    input           l2t_mcu_rd_dummy_req_6 MCU_INPUT_EDGE MCU_INPUT_SKEW       hdl_node "tb_top.cpu.l2t6_mcu3_rd_dummy_req";
    output          mcu_l2t_rd_ack_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu3_l2t6_rd_ack";
    output [2:0]    mcu_l2t_rd_req_id_r0_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu3_l2t6_rd_req_id_r0";
    output          mcu_l2t_data_vld_r0_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu3_l2t6_data_vld_r0";
    output [1:0]    mcu_l2t_qword_id_r0_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu3_l2t6_qword_id_r0";
    output          mcu_l2t_secc_err_r2_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu3_l2t6_secc_err_r2";
    output          mcu_l2t_mecc_err_r2_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu3_l2t6_mecc_err_r2";
    output          mcu_l2t_scb_secc_err_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu3_l2t6_scb_secc_err";
    output          mcu_l2t_scb_mecc_err_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu3_l2t6_scb_mecc_err";

    //  write signals
    input           l2t_mcu_wr_req_6 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t6_mcu3_wr_req";
    output          mcu_l2t_wr_ack_6 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu3_l2t6_wr_ack";
    input           evict_l2b_mcu_data_vld_r5_6 MCU_INPUT_EDGE MCU_INPUT_SKEW  hdl_node "tb_top.cpu.l2b6_mcu3_data_vld_r5";
    input  [63:0]   evict_l2b_mcu_wr_data_r5_6 MCU_INPUT_EDGE MCU_INPUT_SKEW   hdl_node "tb_top.cpu.l2b6_mcu3_wr_data_r5";


    //l2t7 port
    //  read signals
    input           l2t_mcu_rd_req_7 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t7_mcu3_rd_req";
    input  [39:0]   l2t_mcu_addr_7 MCU_INPUT_EDGE MCU_INPUT_SKEW               hdl_node "tb_top.cpu.l2t7_mcu3_addr";
    input           l2t_mcu_addr_5_7 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t7_mcu3_addr_5";
    input  [2:0]    l2t_mcu_rd_req_id_7 MCU_INPUT_EDGE MCU_INPUT_SKEW          hdl_node "tb_top.cpu.l2t7_mcu3_rd_req_id";
    input           l2t_mcu_rd_dummy_req_7 MCU_INPUT_EDGE MCU_INPUT_SKEW       hdl_node "tb_top.cpu.l2t7_mcu3_rd_dummy_req";
    output          mcu_l2t_rd_ack_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu3_l2t7_rd_ack";
    output [2:0]    mcu_l2t_rd_req_id_r0_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu3_l2t7_rd_req_id_r0";
    output          mcu_l2t_data_vld_r0_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu3_l2t7_data_vld_r0";
    output [1:0]    mcu_l2t_qword_id_r0_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu3_l2t7_qword_id_r0";
    output          mcu_l2t_secc_err_r2_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu3_l2t7_secc_err_r2";
    output          mcu_l2t_mecc_err_r2_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW      hdl_node "tb_top.cpu.mcu3_l2t7_mecc_err_r2";
    output          mcu_l2t_scb_secc_err_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu3_l2t7_scb_secc_err";
    output          mcu_l2t_scb_mecc_err_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW     hdl_node "tb_top.cpu.mcu3_l2t7_scb_mecc_err";

    //  write signals
    input           l2t_mcu_wr_req_7 MCU_INPUT_EDGE MCU_INPUT_SKEW             hdl_node "tb_top.cpu.l2t7_mcu3_wr_req";
    output          mcu_l2t_wr_ack_7 MCU_OUTPUT_EDGE MCU_OUTPUT_SKEW           hdl_node "tb_top.cpu.mcu3_l2t7_wr_ack";
    input           evict_l2b_mcu_data_vld_r5_7 MCU_INPUT_EDGE MCU_INPUT_SKEW  hdl_node "tb_top.cpu.l2b7_mcu3_data_vld_r5";
    input  [63:0]   evict_l2b_mcu_wr_data_r5_7 MCU_INPUT_EDGE MCU_INPUT_SKEW   hdl_node "tb_top.cpu.l2b7_mcu3_wr_data_r5";

#endif

}

#endif