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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / vera / niu_intr / include / niu_intr_mon.if.vri
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_intr_mon.if.vri
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#ifdef NIU_GATE
36 // Do nothing
37#else
38
39#ifndef NIU_INT_IF
40#define NIU_INT_IF
41
42#define OUTPUT_EDGE PHOLD
43#define INPUT_EDGE PSAMPLE #-1
44#define OUTPUT_SKEW #1
45
46#define NIU_PIO_IC_PATH NIU_DUV_PATH.rdp.niu_pio.niu_pio_ic
47#define NIU_PIO NIU_DUV_PATH.rdp.niu_pio
48
49
50interface int_mon_ports_if
51{
52 input activate_ig_sm INPUT_EDGE verilog_node NIU_PIO_IC_PATH.niu_pio_ig_sm.activate_ig_sm";
53 input activate_ig_sm_rel INPUT_EDGE verilog_node NIU_PIO_IC_PATH.niu_pio_ig_sm.activate_ig_sm_rel";
54 input ibusy INPUT_EDGE verilog_node NIU_PIO.ibusy";
55 input [63:0] intr_rel_group INPUT_EDGE verilog_node NIU_PIO_IC_PATH.intr_rel_group";
56
57
58 input req_rel_hit_skew0_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew0_noibusy";
59 input req_rel_hit_skew1_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew1_noibusy";
60 input req_rel_hit_skew2_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew2_noibusy";
61 input req_rel_hit_skew3_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew3_noibusy";
62 input req_rel_hit_skew4_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew4_noibusy";
63 input req_rel_hit_skew5_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew5_noibusy";
64
65 input req_rel_hit_skew0_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew0_ibusy";
66 input req_rel_hit_skew1_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew1_ibusy";
67 input req_rel_hit_skew2_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew2_ibusy";
68 input req_rel_hit_skew3_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew3_ibusy";
69 input req_rel_hit_skew4_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew4_ibusy";
70 input req_rel_hit_skew5_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew5_ibusy";
71
72 input rel_req_hit_skew1_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_hit_skew1_noibusy";
73 input rel_req_hit_skew2_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_hit_skew2_noibusy";
74 input rel_req_hit_skew3_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_hit_skew3_noibusy";
75 input rel_req_hit_skew4_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_hit_skew4_noibusy";
76 input rel_req_hit_skew5_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_hit_skew5_noibusy";
77
78 input rel_req_hit_skew1_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_hit_skew1_ibusy";
79 input rel_req_hit_skew2_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_hit_skew2_ibusy";
80 input rel_req_hit_skew3_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_hit_skew3_ibusy";
81 input rel_req_hit_skew4_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_hit_skew4_ibusy";
82 input rel_req_hit_skew5_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_hit_skew5_ibusy";
83
84 input req_rel_cov_en INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_cov_en";
85 input rel_req_cov_en INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_cov_en";
86
87}
88
89
90port int_mon_port
91{
92
93 activate_ig_sm;
94 activate_ig_sm_rel;
95 ibusy;
96 intr_rel_group;
97
98 req_rel_cov_en;
99 rel_req_cov_en;
100
101 req_rel_hit_skew0_noibusy;
102 req_rel_hit_skew1_noibusy;
103 req_rel_hit_skew2_noibusy;
104 req_rel_hit_skew3_noibusy;
105 req_rel_hit_skew4_noibusy;
106 req_rel_hit_skew5_noibusy;
107
108 req_rel_hit_skew0_ibusy;
109 req_rel_hit_skew1_ibusy;
110 req_rel_hit_skew2_ibusy;
111 req_rel_hit_skew3_ibusy;
112 req_rel_hit_skew4_ibusy;
113 req_rel_hit_skew5_ibusy;
114
115 rel_req_hit_skew1_noibusy;
116 rel_req_hit_skew2_noibusy;
117 rel_req_hit_skew3_noibusy;
118 rel_req_hit_skew4_noibusy;
119 rel_req_hit_skew5_noibusy;
120
121 rel_req_hit_skew1_ibusy;
122 rel_req_hit_skew2_ibusy;
123 rel_req_hit_skew3_ibusy;
124 rel_req_hit_skew4_ibusy;
125 rel_req_hit_skew5_ibusy;
126
127
128}
129
130
131bind int_mon_port int_mon_port_bind
132{
133 activate_ig_sm int_mon_ports_if.activate_ig_sm;
134 activate_ig_sm_rel int_mon_ports_if.activate_ig_sm_rel;
135 ibusy int_mon_ports_if.ibusy;
136 intr_rel_group int_mon_ports_if.intr_rel_group;
137
138
139 req_rel_cov_en int_mon_ports_if.req_rel_cov_en;
140 rel_req_cov_en int_mon_ports_if.rel_req_cov_en;
141
142 req_rel_hit_skew0_noibusy int_mon_ports_if.req_rel_hit_skew0_noibusy;
143 req_rel_hit_skew1_noibusy int_mon_ports_if.req_rel_hit_skew1_noibusy;
144 req_rel_hit_skew2_noibusy int_mon_ports_if.req_rel_hit_skew2_noibusy;
145 req_rel_hit_skew3_noibusy int_mon_ports_if.req_rel_hit_skew3_noibusy;
146 req_rel_hit_skew4_noibusy int_mon_ports_if.req_rel_hit_skew4_noibusy;
147 req_rel_hit_skew5_noibusy int_mon_ports_if.req_rel_hit_skew5_noibusy;
148
149 req_rel_hit_skew0_ibusy int_mon_ports_if.req_rel_hit_skew0_ibusy;
150 req_rel_hit_skew1_ibusy int_mon_ports_if.req_rel_hit_skew1_ibusy;
151 req_rel_hit_skew2_ibusy int_mon_ports_if.req_rel_hit_skew2_ibusy;
152 req_rel_hit_skew3_ibusy int_mon_ports_if.req_rel_hit_skew3_ibusy;
153 req_rel_hit_skew4_ibusy int_mon_ports_if.req_rel_hit_skew4_ibusy;
154 req_rel_hit_skew5_ibusy int_mon_ports_if.req_rel_hit_skew5_ibusy;
155
156 rel_req_hit_skew1_noibusy int_mon_ports_if.rel_req_hit_skew1_noibusy;
157 rel_req_hit_skew2_noibusy int_mon_ports_if.rel_req_hit_skew2_noibusy;
158 rel_req_hit_skew3_noibusy int_mon_ports_if.rel_req_hit_skew3_noibusy;
159 rel_req_hit_skew4_noibusy int_mon_ports_if.rel_req_hit_skew4_noibusy;
160 rel_req_hit_skew5_noibusy int_mon_ports_if.rel_req_hit_skew5_noibusy;
161
162 rel_req_hit_skew1_ibusy int_mon_ports_if.rel_req_hit_skew1_ibusy;
163 rel_req_hit_skew2_ibusy int_mon_ports_if.rel_req_hit_skew2_ibusy;
164 rel_req_hit_skew3_ibusy int_mon_ports_if.rel_req_hit_skew3_ibusy;
165 rel_req_hit_skew4_ibusy int_mon_ports_if.rel_req_hit_skew4_ibusy;
166 rel_req_hit_skew5_ibusy int_mon_ports_if.rel_req_hit_skew5_ibusy;
167
168
169}
170
171#endif // NIU_RXC_IF
172#endif // if NIU_GATE... else...endif
173
174// End
175
176
177
178
179
Full OpenSPARC design & verification tarball including full HDL.