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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mcu.config | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #include "defaults.config" | |
36 | #ifdef DRAMX8 | |
37 | #define DRAMX8 DRAMX8 | |
38 | #endif | |
39 | ||
40 | <mcu> | |
41 | #ifdef AXIS_BUILD | |
42 | -config_rtl=AXIS | |
43 | -sunv_args=-keepSectionSym=AXIS_SMEM | |
44 | -sunv_args=-keepSectionSym=EMUL_COSIM | |
45 | -vcs_build_args=-P $VERA_HOME/lib/vera_pli.tab | |
46 | -vcs_build_args=$VERA_HOME/lib/libSysSciTask.a | |
47 | -vcs_build_args=-pl -lsocket -pl -lnsl -pl -lintl -pl -ldl | |
48 | -vcs_build_args=+v2000 | |
49 | -vcs_build_args=+define+AXIS | |
50 | //-axis_build_args="-scope n2_fc -check_synth " | |
51 | //-vcs_build_args=" +dutexcl+pll_core+cl_a1_blatch_4x+cl_sc1_blatch_4x " | |
52 | //-vcs_build_args=" +define+AXIS_FBDIMM_HW " | |
53 | //-vcs_build_args=" +dut+amb_top" | |
54 | -axis_build_args="-scope n2_fc " | |
55 | -vcs_build_args=+define+DISABLE_ERR_MON | |
56 | -vcs_build_args=+define+FSR_NOATPG | |
57 | -vcs_run_args=+NO_DUMMY_READ | |
58 | -vcs_run_args=+BYPASS_L0_STATE_WAIT | |
59 | -vcs_build_args=+define+OTHER_FBDIMM | |
60 | -diaglist_cpp_args=-DAXIS_BUILD | |
61 | #ifdef AXIS_COSIM | |
62 | -vcs_build_args="+define+AXIS_SMEM+EMUL_COSIM+AXIS_EMUL_COSIM aaaaa" | |
63 | -axis_build_args="-hwtype xs -model_type axis_cs -comp_64" | |
64 | -vcs_build_args=" +dut+mcu+mcusat_fbdimm" | |
65 | -axis_build_args=-fpga_compile | |
66 | #else | |
67 | -vcs_build_args=" +dut+cpu" | |
68 | #endif | |
69 | -vcs_build_args=+define+AXIS_FBDIMM_HW | |
70 | -vcs_build_args=+define+FBDIMM_NUM_1+ | |
71 | #else | |
72 | #ifdef DRAMX8 | |
73 | -flist=$DV_ROOT/verif/model/verilog/mem/dram/infineon_x8_ddr2.flist | |
74 | #else | |
75 | -flist=$DV_ROOT/verif/model/verilog/mem/dram/infineon_ddr2.flist | |
76 | #endif | |
77 | #endif | |
78 | -asm_diag_root=$DV_ROOT/verif/diag | |
79 | -vera_diag_root=$DV_ROOT/verif/diag | |
80 | -vera_config_root=$DV_ROOT/verif | |
81 | -image_diag_root=$DV_ROOT/verif | |
82 | -wait_cycle_to_kill=10 | |
83 | -post_process_cmd="regreport -1 > status.log" | |
84 | -model=mcu | |
85 | #ifdef INPHI_AMB | |
86 | -flist=$DV_ROOT/verif/model/inphi/inphi_amb.flist | |
87 | -flist=$DV_ROOT/verif/model/sun/sun_misc.flist | |
88 | #elif MICRON_AMB | |
89 | -flist=$DV_ROOT/verif/model/micron/micron_amb.flist | |
90 | -flist=$DV_ROOT/verif/model/sun/sun_misc.flist | |
91 | #elif IDT_AMB | |
92 | -flist=$DV_ROOT/verif/model/idt/idt_amb.flist | |
93 | -flist=$DV_ROOT/verif/model/sun/sun_misc.flist | |
94 | #elif NEC_AMB | |
95 | -flist=$DV_ROOT/verif/model/nec/nec_amb.flist | |
96 | -flist=$DV_ROOT/verif/model/sun/sun_misc.flist | |
97 | -vcs_build_args=+define+ASSERTS_OFF | |
98 | -vcs_build_args=+nospecify | |
99 | -vcs_build_args=+access+rwc | |
100 | -vcs_build_args=+no_tchkmsg | |
101 | -vcs_build_args=+notimingcheck | |
102 | -vcs_build_args=+libext+.vp+ | |
103 | -vcs_build_args=+warn=noTMR | |
104 | #else | |
105 | -flist=$DV_ROOT/verif/model/sun/sun_amb.flist | |
106 | #endif | |
107 | -flist=$DV_ROOT/verif/env/mcu/mcu.flist | |
108 | -flist=$DV_ROOT/verif/env/tcu/ccu_rtl.flist | |
109 | #ifdef AXIS_BUILD | |
110 | -flist=$DV_ROOT/verif/env/mcu/fbd_serdes_axis.flist | |
111 | -vera_build_args="VFLAGS=-DAXIS_DDR2_MODEL" | |
112 | -vcs_build_args=+define+AXIS_DDR2_MODEL | |
113 | -flist=$DV_ROOT/verif/env/fc/axis_dimm.flist | |
114 | -vcs_run_args=+ddr2_way_err_enable=0 | |
115 | -vcs_run_args=+ddr2_way_warn_enable=1 | |
116 | ||
117 | #elif FSR_RTL | |
118 | -flist=$DV_ROOT/verif/env/mcu/fbd_serdes.flist | |
119 | #else | |
120 | -flist=$DV_ROOT/verif/env/mcu/fbd_serdes_axis.flist | |
121 | #endif | |
122 | ||
123 | #ifdef AXIS_NO_FSR | |
124 | -vcs_build_args=+define+AXIS_FBDIMM_NO_FSR | |
125 | -vcs_build_args="-Z $DV_ROOT/verif/env/mcu/axis_hack_fsr.v " | |
126 | #ifdef AXIS_TL | |
127 | -vcs_build_args=+dut+no_fsr_for_axis | |
128 | #endif | |
129 | #endif | |
130 | ||
131 | -config_rtl=MCU | |
132 | -vera_vcon_file=mcu_top.vcon | |
133 | -env_base=$DV_ROOT/verif/env/mcu | |
134 | #ifndef AXIS_BUILD | |
135 | // NCR:enabled in the diags directly -vcs_run_args=+slam_init_value | |
136 | -vcs_build_args=-v $DV_ROOT/verif/env/common/verilog/monitors/ddr2_monitor.v | |
137 | -vcs_build_args=-v $DV_ROOT/verif/env/mcu/amb_dram_err_inject.v | |
138 | -vcs_build_args=-v $DV_ROOT/verif/env/common/verilog/monitors/mcu_errmon.v | |
139 | -vcs_build_args="-Xpae=0x20" | |
140 | -vcs_build_args="+v2k" | |
141 | -vcs_build_args=+rad | |
142 | -vcs_build_args="-notice" | |
143 | -vcs_build_args=-M | |
144 | -vcs_build_args=-Mupdate | |
145 | -vcs_build_args=-vera | |
146 | -vcs_build_args=+define+ZEROIN_DDR2_DRAM_MONITOR | |
147 | #endif | |
148 | -vera_build_args=PAL_OPTS="sys=DRAM" | |
149 | -vcs_build_args=+define+BWSIM_SAME_GCLK_RCLK+ | |
150 | -vcs_build_args=+define+DRAM_SAT+ | |
151 | -vcs_build_args=+define+MODEL_DRAM+ | |
152 | #ifdef IDT_AMB | |
153 | -vcs_build_args=+define+DDR2_0IN_SIM_MON+ | |
154 | -vcs_build_args=+define+DDR2_MONITOR_ON+ | |
155 | #endif | |
156 | ||
157 | #ifdef DRAMX8 | |
158 | -vcs_build_args=+define+X8+ | |
159 | -vera_build_args="VFLAGS=-DX8 -DDRAM" | |
160 | -zeroIn_build_args=+define+X8 | |
161 | -vcs_run_args=+X8 | |
162 | #else | |
163 | -vcs_build_args=+define+X4+ | |
164 | -vera_build_args="VFLAGS=-DDRAM" | |
165 | #endif | |
166 | -vcs_build_args=+define+MCUSAT | |
167 | -vcs_build_args=+define+FSR_NOATPG | |
168 | #ifdef AXIS_BUILD | |
169 | -vcs_build_args=+define+NO_Ill_cmd_before_init_CHECK | |
170 | -vcs_build_args=+define+NO_err_cke | |
171 | -vcs_build_args=+define+NO_err_cke_diasserted_when_not_pwr_down_CHECK | |
172 | -vcs_build_args=+define+NO_err_dqs_and_dqsbar_not_in_sync_CHECK | |
173 | -vcs_build_args=+define+NO_Ill_bank_state_CHECK | |
174 | -vcs_build_args=+define+NO_Ill_cmd_while_bank_active_CHECK | |
175 | -vcs_build_args=+define+NO_err_rd_dqs_not_asserted_when_rd_data_ready_CHECK | |
176 | -vcs_build_args=+define+NO_Ill_cmd_after_pre_CHECK | |
177 | -vcs_build_args=+define+NO_Ill_cmd_during_init_cke_not_low_for_200ns_CHECK | |
178 | -vcs_build_args=+define+NO_Ill_cmd_during_init_pre_all_issued_early_CHECK | |
179 | -vcs_build_args=+define+NO_Ill_cmd_during_init_MRS_with_DLL_disable_expected_CHECK | |
180 | -vcs_build_args=+define+NO_err_clk_and_clkbar_not_in_sync_CHECK | |
181 | #endif | |
182 | // NCR -vcs_build_args=+define+NO_err_invalid_cmd_CHECK | |
183 | -vcs_build_args=+define+DISABLE_tMRD_VIOLATION_AT_PD_ENTRY | |
184 | -vcs_build_args=+define+DISABLE_TID_CHKR | |
185 | // NCR -vcs_build_args="-P /import/datools/vendor/denali/3.100-0008/verilog/pli.tab" | |
186 | // NCR -vcs_build_args=/import/datools/vendor/denali/3.100-0008/verilog/denverlib.o | |
187 | -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/bwsocket/bwsocket_pli.tab" | |
188 | -vcs_build_args=$DV_ROOT/verif/env/common/pli/bwutility/libdummy.a | |
189 | -vcs_build_args=$DV_ROOT/verif/env/common/pli/bwsocket/libbwsocket_pli.a | |
190 | -vcs_build_args="-P $DV_ROOT/verif/model/infineon/bwmem_pli.tab" | |
191 | -vcs_build_args=$DV_ROOT/verif/model/infineon/libbwmem_pli.a | |
192 | -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/bwutility/bwutility_pli.tab" | |
193 | -vcs_build_args=$DV_ROOT/verif/env/common/pli/bwutility/libbwutility_pli.a | |
194 | -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/monitor/monitor_pli.tab" | |
195 | -vcs_build_args=$DV_ROOT/verif/env/common/pli/monitor/libmonitor_pli.a | |
196 | -vcs_build_args=$DV_ROOT/verif/model/verilog/mem/fbdimm/monitor/hasher.o | |
197 | #ifdef INPHI_AMB | |
198 | -vcs_build_args=+define+INPHI_FBDIMM | |
199 | -vcs_build_args=+define+VERBOSE | |
200 | -vcs_run_args=+nospecify | |
201 | -vcs_run_args=+notimingcheck | |
202 | #endif | |
203 | -drm_disk=[/export/home/bw=30] | |
204 | -drm_type=vcs | |
205 | -drm_freeprocessor=1.0 | |
206 | ||
207 | SUNVFORCEOPTS | |
208 | -sunv_args=-topcell=cpu | |
209 | -sunv_args=-define=PAD_NIAGARA | |
210 | -sunv_args=-define=sim | |
211 | -sunv_args=-flattencell='_macro$' | |
212 | -sunv_args=-define=SIM | |
213 | -sunv_args=-define=LIB | |
214 | //-sunv_args=-define=INITLATZERO | |
215 | -sunv_args=-define=SCAN_MODE | |
216 | -sunv_args=-showCompiledOutCode=off | |
217 | -sunv_use_nonprim | |
218 | -sunv_nonprim_list=$DV_ROOT/verif/env/mcu/mcu_nonprimitive.list | |
219 | -sunv_args=-excludepreload | |
220 | -sunv_args=-excludecell=\^fsr_left\$ | |
221 | -sunv_args=-excludecell=\^fsr_right\$ | |
222 | -sunv_args=-excludecell=\^fsr_bottom\$ | |
223 | -sunv_args=-excludecell=\^ccu\$ | |
224 | -sunv_args=-out=cpu.v | |
225 | -sunv_args=-path=SUNV_RTL_PATH | |
226 | -sunv_args=-path=SUNVMACROS | |
227 | -sunv_args=-preload=SUNVLIBS_SUNV | |
228 | -sunv_args=-perlinclude=SUNVPERLINC | |
229 | -sunv_args=-strict | |
230 | #ifdef INPHI_AMB | |
231 | -sunv_args=-define=FBD_LAT_DELAY_2 | |
232 | #endif | |
233 | #ifdef MICRON_AMB | |
234 | -sunv_args=-define=FBD_LAT_DELAY_1 | |
235 | #endif | |
236 | #ifdef IDT_AMB | |
237 | -sunv_args=-define=FBD_LAT_DELAY_1 | |
238 | #endif | |
239 | #ifdef NEC_AMB | |
240 | -sunv_args=-define=FBD_LAT_DELAY_1 | |
241 | #endif | |
242 | ||
243 | -vlint_top=cpu | |
244 | -vlint_args=+define+TOP=cpu | |
245 | -vlint_args=-merge_bus_report | |
246 | -vlint_args=-turn_unspecified_off | |
247 | -vlint_args=-binary | |
248 | -vlint_args=-vlint | |
249 | -vlint_args=-depth 999 | |
250 | -vlint_args=-vr $DV_ROOT/verif/env/config/vlint.rc | |
251 | -vlint_args=-turn_unspecified_off | |
252 | -vlint_args=SUNVLIBS_OTHER | |
253 | -illust_run | |
254 | -illust_args=-b -c $DV_ROOT/verif/env/config/filter_vlint.rc | |
255 | -zeroIn_build_args=+define+TOP=tb_top | |
256 | -zeroIn_build_args=+define+MCUSAT | |
257 | -zeroIn_build_args=+define+FSR_NOATPG | |
258 | -zeroIn_build_args=-d cpu | |
259 | #ifdef AXIS_BUILD | |
260 | -drm_freeram=1500 | |
261 | -zeroIn_build_args=-sim axis | |
262 | #else | |
263 | #ifdef NEC_AMB | |
264 | -drm_freeram=512 | |
265 | #else | |
266 | -drm_freeram=200 | |
267 | #endif | |
268 | -zeroIn_build_args=+define+ZEROIN_DDR2_DRAM_MONITOR | |
269 | -zeroIn_build_args=-sim vcs | |
270 | -zeroIn_build_args="-fastmod mcu" | |
271 | //-zeroIn_build_args="-fastsim turbo" | |
272 | -zeroIn_build_args=+error+command-19 | |
273 | -zeroIn_build_args=+error+command-46 | |
274 | -zeroIn_build_args=+error+command-6 | |
275 | -zeroIn_build_args=+error+command-7 | |
276 | #endif | |
277 | -zeroIn_build_args=-exit_on_directive_errors | |
278 | -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/mcu/mcu_zeroIn_cfg.v | |
279 | -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/common/verilog/checkers/mcu/mcul2_intf_chkr.v | |
280 | -zeroIn_build_args=-v SUNV_PATH/library/cl_rtl_ext.v | |
281 | -zeroIn_build_args=-v LAVA_LIB_PATH/cl_dp1/compiled/cl_dp1.v | |
282 | -zeroIn_build_args=-v LAVA_LIB_PATH/cl_u1/compiled/cl_u1.v | |
283 | -zeroIn_build_args=-v LAVA_LIB_PATH/cl_sc1/compiled/cl_sc1.v | |
284 | -vcs_run_args=+0in_checker_finish_delay+3000 | |
285 | -vcs_build_args=+define+LIB | |
286 | //-vcs_build_args=+define+INITLATZERO | |
287 | -vcs_build_args=+define+SCAN_MODE | |
288 | -vcs_build_args=SUNVLIBS_OTHER | |
289 | -sas_run_args=-DSP0 | |
290 | -sas_run_args=-DMEM_TEST | |
291 | -sas_run_args=-DINTR_TEST | |
292 | -sas_run_args=-DMEM_DEBUG | |
293 | -sas_run_args=-DNIAGARA | |
294 | -vcs_run_args=+vera_disable_final_report | |
295 | -vcs_run_args=+plusarg_save | |
296 | -vcs_run_args=+vera_exit_on_error | |
297 | -vcs_run_args=+DRAM | |
298 | -vcs_run_args=+vera_exit_on_error | |
299 | -vcs_run_args=+no_slam_init | |
300 | -pre_process_cmd="\rm -f *.gz" | |
301 | ||
302 | #ifdef DCH_8DIMM | |
303 | -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_mem_data/dch_8dm*.data ." | |
304 | -post_process_cmd="gzip dch*.data" | |
305 | #endif | |
306 | #ifdef DCH_4DIMM | |
307 | -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_mem_data/dch_4dm*.data ." | |
308 | -post_process_cmd="gzip dch*.data" | |
309 | #endif | |
310 | #ifdef DCH_2DIMM | |
311 | -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_mem_data/dch_2dm*.data ." | |
312 | -post_process_cmd="gzip dch*.data" | |
313 | #endif | |
314 | #ifdef DCH_1DIMM | |
315 | -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_mem_data/dch_1dm*.data ." | |
316 | -post_process_cmd="gzip dch*.data" | |
317 | #endif | |
318 | #ifdef SCH_8DIMM | |
319 | -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_mem_data/sch_8dm*.data ." | |
320 | -post_process_cmd="gzip sch*.data" | |
321 | #endif | |
322 | #ifdef SCH_4DIMM | |
323 | -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_mem_data/sch_4dm*.data ." | |
324 | -post_process_cmd="gzip sch*.data" | |
325 | #endif | |
326 | #ifdef SCH_2DIMM | |
327 | -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_mem_data/sch_2dm*.data ." | |
328 | -post_process_cmd="gzip sch*.data" | |
329 | #endif | |
330 | #ifdef SCH_1DIMM | |
331 | -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_mem_data/sch_1dm*.data ." | |
332 | -post_process_cmd="gzip sch*.data" | |
333 | #endif | |
334 | -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_register.data ." | |
335 | -post_process_cmd="regreport -1 > status.log" | |
336 | -post_process_cmd="gzip vcs.log" | |
337 | -post_process_cmd="gzip sims.log" | |
338 | -asm_diag_root=$DV_ROOT/verif | |
339 | -tpt_diag_root=$DV_ROOT/verif | |
340 | -spis_diag_root=$DV_ROOT/verif | |
341 | -vera_diag_root=$DV_ROOT/verif | |
342 | -vera_config_root=$DV_ROOT/verif | |
343 | -vcs_cm_config=$DV_ROOT/verif/env/mcu/mcu.cm_config | |
344 | -image_diag_root=$DV_ROOT/verif | |
345 | -drm_freeswap=1000 | |
346 | -drm_freeram=1000 | |
347 | #ifdef AXIS_BUILD | |
348 | //AXIS model only works with one size of dram.. so assume this and call axis_conver script to buil dream data based on this size | |
349 | -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_mem_data/dch_1dm_rk1_2Gb_mem.data mem.image" | |
350 | -axis_run_args=-runpresim '"$DV_ROOT/verif/env/mcu/axis_convert -s -m 0x800000000 "' | |
351 | #endif | |
352 | #ifndef ZEROINCOV | |
353 | -zeroIn_build_args="-fastsim turbo" | |
354 | #else | |
355 | -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/common/coverage/mcusat/mcuras_0in_cov.v | |
356 | // This arg creates a 0in_coverage_bitmap.txt in the 0in build dir | |
357 | -zeroIn_dbg_args=+0in_debug+display_stats_in_binary+coverage_bit_map | |
358 | #endif | |
359 | </mcu> |