projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / config / spc2_common.config
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: spc2_common.config
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include "defaults.config"
36
37//
38// Keep consistant with other SPARC benches
39//
40//
41// -flist= order matters!
42//
43
44
45 -pal_use_tgseed
46 -asm_diag_root=$DV_ROOT/verif/diag/assembly
47 -config_rtl=CORE_0
48 -config_rtl=SPC
49 -config_rtl=SPC_BENCH
50 // Generic define for all core Benches (SPC2,CMPn,CCMn,FCn). Not set in SATs.
51 -config_rtl=CORE_BENCH
52
53#ifdef AXIS_BUILD
54 -config_rtl=AXIS
55 -sunv_args=-keepSectionSym=AXIS_SMEM
56 -sunv_args=-keepSectionSym=EMUL_COSIM
57 -sunv_args=-keepSectionSym=AXIS_EMUL_COSIM
58 -vcs_build_args=-P $VERA_HOME/lib/vera_pli.tab
59 -vcs_build_args=$VERA_HOME/lib/libSysSciTask.a
60 -vcs_build_args=-pl -lsocket -pl -lnsl -pl -lintl -pl -ldl
61 -vcs_build_args=+v2000
62 -axis_build_args=" -scope n2_spc "
63 -novcs_use_vcsd
64 -vera_build_args="NO_0INMGR=1"
65#endif
66 -diaglist_cpp_args=-DALL_THREADS=8
67 -drm_disk=[/export/home/bw=30]
68 -drm_freeprocessor=1.0
69 -drm_freeram=1000
70 -drm_type=vcs
71 -env_base=$DV_ROOT/verif/env/spc2
72 -flist=$DV_ROOT/verif/env/common/verilog/misc/misc.flist
73// #ifndef SPC_DFT_BENCH
74 -flist=$DV_ROOT/verif/env/common/verilog/monitors/monitors.flist
75 -flist=$DV_ROOT/verif/env/common/verilog/nas_car/nas_car.flist
76 -flist=$DV_ROOT/verif/env/common/verilog/tlb_sync/tlb_sync.flist
77 -flist=$DV_ROOT/verif/env/common/verilog/int_sync/int_sync.flist
78 -flist=$DV_ROOT/verif/env/common/verilog/err_sync/err_sync.flist
79 -flist=$DV_ROOT/verif/env/common/verilog/ldst_sync/ldst_sync.flist
80 -flist=$DV_ROOT/verif/env/common/verilog/ras/ras.flist
81 -flist=$DV_ROOT/verif/env/common/verilog/reg_slam/reg_slam.flist
82// #endif
83 -flist=$DV_ROOT/verif/env/spc2/spc2.flist
84 -fsdbfile=spc_top.fsdb
85 -hcs_build_args=+hcs+atf $DV_ROOT/verif/env/config/spc2.hcsrc_comp
86 -hcs_build_args=+hcs+v2k
87 -hcs_drm_tokens=6
88 -illust_args=-b -c $DV_ROOT/verif/env/config/filter_vlint.rc
89 -illust_run
90 -image_diag_root=$DV_ROOT/verif/diag/
91 -midas_args=-tsbtagfmt=tagtarget
92 -midas_args=-cpp_args=-traditional-cpp
93 -midas_args=-DSPC
94 -midas_args=-DALL_THREADS=0xff
95 -midas_args=-DMAX_THREADS=8
96 -post_process_cmd="regreport -1 | tee status.log"
97 -sas_run_args=-DTSO_CHECKER
98 -sas_run_args=-DINTR_TEST
99 -sas_run_args=-DMEM_DISABLE
100 -sas_run_args=-DSP0
101 -sas_run_args=-DFORCE_PC
102 -sas_run_args=-DTHREAD_STATUS_ADDR=0x9a00000000
103 SUNVFORCEOPTS
104 -sunv_args=-out=spc.v
105 -sunv_args=-topcell=spc
106 -sunv_args=-showCompiledOutCode=off
107 -sunv_args=-filter=400010,300012
108 -sunv_args=-n2verify
109 -sunv_args=-define=SIM
110 -sunv_args=-define=LIB
111#ifdef NO_INITLATZERO
112#else
113 -sunv_args=-define=INITLATZERO
114 -vcs_build_args=+define+INITLATZERO
115#endif
116 -sunv_args=-define=NOL2RTL
117 -sunv_args=-excludepreload
118 -sunv_args=-ignorepartial
119 -sunv_args=-path=SUNV_RTL_PATH
120 -sunv_args=-perlinclude=SUNV_PATH/include
121 -sunv_args=-preload=SUNVLIBS_SUNV
122 -sunv_args=-unusednet='unused$:unused\[[0-9]+\]$'
123 -sunv_args=-version
124 -sunv_args=-warn=2000
125 -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/monitor/monitor_pli.tab"
126 -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/socket/socket_pli.tab"
127 -vcs_build_args=$DV_ROOT/verif/env/common/pli/monitor/libmonitor_pli.a
128 -vcs_build_args=$DV_ROOT/verif/env/common/pli/socket/libsocket_pli.a
129
130 -vcs_build_args=+define+LIB
131 -vcs_build_args=+define+SIM
132 -vcs_build_args=+define+NOL2RTL
133 -vcs_build_args=+define+TOP=tb_top
134 -vcs_build_args=+nospecify
135 -vcs_build_args=+notimingcheck
136#ifdef GATES
137 #define GATES_LIBS -v LAVA_LIB_PATH/cl_dp1lvt/compiled/cl_dp1lvt.v -v LAVA_LIB_PATH/cl_u1lvt/compiled/cl_u1lvt.v -v LAVA_LIB_PATH/cl_sc1lvt/compiled/cl_sc1lvt.v
138 -vcs_build_args=GATES_LIBS
139 -vcs_build_args=+define+GATESIM
140 -vcs_build_args=+define+GATES_FLAT
141 -flist=$DV_ROOT/verif/env/spc2/spc2_gates.flist
142#endif
143#ifdef AXIS_BUILD
144 -novcs_use_ntb
145 -vcs_run_args=+unforcePORstate
146#else
147 -vcs_build_args="+delay_mode_zero "
148 -vcs_build_args=+v2k
149 -vcs_build_args=+rad
150 -vcs_build_args=-Mupdate
151 -vcs_build_args="-Xstrict=0x1 -syslib -lpthread +nbaopt -O4 "
152 -vcs_use_vera
153 -vcs_use_ntb
154 -vcs_run_args=+ntb_exit_on_error=1
155 -vcs_run_args=+0in_checker_finish_delay+3000
156 -vcs_run_args=+0in_debug+no_auto_message_wrap
157#endif
158 -vcs_build_args=SUNVLIBS_OTHER
159 -vcs_run_args=+vera_disable_final_report
160 -vcs_run_args=+vera_exit_on_error
161 -vera_config_root=$DV_ROOT/verif
162 -vera_diag_root=$DV_ROOT/verif/diag/vera
163 -vera_vcon_file=spc2_top.vcon
164 -vcs_run_args=+vera_new_debugger
165 -vlint_args=+define+TOP=tb_top
166 -vlint_args=-binary
167 -vlint_args=-binary_only
168 -vlint_args=-depth 999
169 -vlint_args=-turn_unspecified_off
170 -vlint_args=SUNVLIBS_OTHER
171 -vlint_args=-vlint
172 -vlint_args=-vr $DV_ROOT/verif/env/config/vlint.rc
173 -vlint_args=-merge_bus_report
174 -vlint_top=spc
175 -wait_cycle_to_kill=15
176 -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/common/coverage/0in_coverages.v
177 -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/common/verilog/checkers/0in_checkers.v
178 -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/spc2/spc2_zeroIn_cfg.v
179 -zeroIn_build_args=-d spc
180 -zeroIn_build_args=-exit_on_directive_errors
181 -zeroIn_build_args=+error+command-19
182 -zeroIn_build_args=+error+command-46
183 -zeroIn_build_args=+error+command-6
184 -zeroIn_build_args=+error+command-7
185 -zeroIn_build_args=+error+command-2
186 -zeroIn_build_args=-incr
187#ifdef AXIS_BUILD
188 -zeroIn_build_args=-sim axis
189#else
190 -zeroIn_build_args=-sim vcs
191#ifndef NOFASTMOD
192 -zeroIn_build_args=-fastmod
193#endif
194#ifndef ZEROINCOV
195 -zeroIn_build_args="-fastsim turbo"
196#else
197 // This arg creates a 0in_coverage_bitmap.txt in the 0in build dir
198 -zeroIn_dbg_args=+0in_debug+display_stats_in_binary+coverage_bit_map
199#endif
200#endif
201 -zeroIn_build_args=SUNVLIBS_OTHER
202
Full OpenSPARC design & verification tarball including full HDL.