verif/env/config/spc2_common.config

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: spc2_common.config
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// have any questions.
//
// ========== Copyright Header End ============================================
#include "defaults.config"

//
// Keep consistant with other SPARC benches
//
//
// -flist= order matters!
//


    -pal_use_tgseed
    -asm_diag_root=$DV_ROOT/verif/diag/assembly
    -config_rtl=CORE_0
    -config_rtl=SPC
    -config_rtl=SPC_BENCH
    // Generic define for all core Benches (SPC2,CMPn,CCMn,FCn).  Not set in SATs.
    -config_rtl=CORE_BENCH

#ifdef AXIS_BUILD
    -config_rtl=AXIS
    -sunv_args=-keepSectionSym=AXIS_SMEM
    -sunv_args=-keepSectionSym=EMUL_COSIM
    -sunv_args=-keepSectionSym=AXIS_EMUL_COSIM
    -vcs_build_args=-P $VERA_HOME/lib/vera_pli.tab
    -vcs_build_args=$VERA_HOME/lib/libSysSciTask.a
    -vcs_build_args=-pl -lsocket -pl -lnsl -pl -lintl -pl -ldl
    -vcs_build_args=+v2000
    -axis_build_args=" -scope n2_spc "
    -novcs_use_vcsd
    -vera_build_args="NO_0INMGR=1"
#endif
    -diaglist_cpp_args=-DALL_THREADS=8
    -drm_disk=[/export/home/bw=30]
    -drm_freeprocessor=1.0
    -drm_freeram=1000
    -drm_type=vcs
    -env_base=$DV_ROOT/verif/env/spc2
    -flist=$DV_ROOT/verif/env/common/verilog/misc/misc.flist
// #ifndef SPC_DFT_BENCH
    -flist=$DV_ROOT/verif/env/common/verilog/monitors/monitors.flist
    -flist=$DV_ROOT/verif/env/common/verilog/nas_car/nas_car.flist
    -flist=$DV_ROOT/verif/env/common/verilog/tlb_sync/tlb_sync.flist
    -flist=$DV_ROOT/verif/env/common/verilog/int_sync/int_sync.flist
    -flist=$DV_ROOT/verif/env/common/verilog/err_sync/err_sync.flist
    -flist=$DV_ROOT/verif/env/common/verilog/ldst_sync/ldst_sync.flist
    -flist=$DV_ROOT/verif/env/common/verilog/ras/ras.flist
    -flist=$DV_ROOT/verif/env/common/verilog/reg_slam/reg_slam.flist
// #endif
    -flist=$DV_ROOT/verif/env/spc2/spc2.flist
    -fsdbfile=spc_top.fsdb
    -hcs_build_args=+hcs+atf $DV_ROOT/verif/env/config/spc2.hcsrc_comp
    -hcs_build_args=+hcs+v2k
    -hcs_drm_tokens=6
    -illust_args=-b -c $DV_ROOT/verif/env/config/filter_vlint.rc
    -illust_run
    -image_diag_root=$DV_ROOT/verif/diag/
    -midas_args=-tsbtagfmt=tagtarget
    -midas_args=-cpp_args=-traditional-cpp
    -midas_args=-DSPC
    -midas_args=-DALL_THREADS=0xff
    -midas_args=-DMAX_THREADS=8
    -post_process_cmd="regreport -1 | tee status.log"
    -sas_run_args=-DTSO_CHECKER
    -sas_run_args=-DINTR_TEST
    -sas_run_args=-DMEM_DISABLE
    -sas_run_args=-DSP0
    -sas_run_args=-DFORCE_PC
    -sas_run_args=-DTHREAD_STATUS_ADDR=0x9a00000000
     SUNVFORCEOPTS
    -sunv_args=-out=spc.v
    -sunv_args=-topcell=spc
    -sunv_args=-showCompiledOutCode=off
    -sunv_args=-filter=400010,300012
    -sunv_args=-n2verify
    -sunv_args=-define=SIM
    -sunv_args=-define=LIB
#ifdef NO_INITLATZERO
#else
    -sunv_args=-define=INITLATZERO
    -vcs_build_args=+define+INITLATZERO
#endif
    -sunv_args=-define=NOL2RTL
    -sunv_args=-excludepreload
    -sunv_args=-ignorepartial
    -sunv_args=-path=SUNV_RTL_PATH
    -sunv_args=-perlinclude=SUNV_PATH/include
    -sunv_args=-preload=SUNVLIBS_SUNV
    -sunv_args=-unusednet='unused$:unused\[[0-9]+\]$'
    -sunv_args=-version
    -sunv_args=-warn=2000
    -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/monitor/monitor_pli.tab"
    -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/socket/socket_pli.tab"
    -vcs_build_args=$DV_ROOT/verif/env/common/pli/monitor/libmonitor_pli.a
    -vcs_build_args=$DV_ROOT/verif/env/common/pli/socket/libsocket_pli.a

    -vcs_build_args=+define+LIB
    -vcs_build_args=+define+SIM
    -vcs_build_args=+define+NOL2RTL
    -vcs_build_args=+define+TOP=tb_top
    -vcs_build_args=+nospecify
    -vcs_build_args=+notimingcheck
#ifdef GATES
    #define GATES_LIBS -v LAVA_LIB_PATH/cl_dp1lvt/compiled/cl_dp1lvt.v -v LAVA_LIB_PATH/cl_u1lvt/compiled/cl_u1lvt.v -v LAVA_LIB_PATH/cl_sc1lvt/compiled/cl_sc1lvt.v
    -vcs_build_args=GATES_LIBS
    -vcs_build_args=+define+GATESIM
    -vcs_build_args=+define+GATES_FLAT
    -flist=$DV_ROOT/verif/env/spc2/spc2_gates.flist
#endif
#ifdef AXIS_BUILD
    -novcs_use_ntb
    -vcs_run_args=+unforcePORstate
#else
    -vcs_build_args="+delay_mode_zero "
    -vcs_build_args=+v2k
    -vcs_build_args=+rad
    -vcs_build_args=-Mupdate
    -vcs_build_args="-Xstrict=0x1 -syslib -lpthread +nbaopt -O4 "
    -vcs_use_vera
    -vcs_use_ntb
    -vcs_run_args=+ntb_exit_on_error=1
    -vcs_run_args=+0in_checker_finish_delay+3000
    -vcs_run_args=+0in_debug+no_auto_message_wrap
#endif
    -vcs_build_args=SUNVLIBS_OTHER
    -vcs_run_args=+vera_disable_final_report
    -vcs_run_args=+vera_exit_on_error
    -vera_config_root=$DV_ROOT/verif
    -vera_diag_root=$DV_ROOT/verif/diag/vera
    -vera_vcon_file=spc2_top.vcon
    -vcs_run_args=+vera_new_debugger
    -vlint_args=+define+TOP=tb_top
    -vlint_args=-binary
    -vlint_args=-binary_only
    -vlint_args=-depth 999
    -vlint_args=-turn_unspecified_off
    -vlint_args=SUNVLIBS_OTHER
    -vlint_args=-vlint
    -vlint_args=-vr $DV_ROOT/verif/env/config/vlint.rc
    -vlint_args=-merge_bus_report
    -vlint_top=spc
    -wait_cycle_to_kill=15
    -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/common/coverage/0in_coverages.v
    -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/common/verilog/checkers/0in_checkers.v
    -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/spc2/spc2_zeroIn_cfg.v
    -zeroIn_build_args=-d spc
    -zeroIn_build_args=-exit_on_directive_errors
    -zeroIn_build_args=+error+command-19
    -zeroIn_build_args=+error+command-46
    -zeroIn_build_args=+error+command-6
    -zeroIn_build_args=+error+command-7
    -zeroIn_build_args=+error+command-2
    -zeroIn_build_args=-incr
#ifdef AXIS_BUILD
    -zeroIn_build_args=-sim axis
#else
    -zeroIn_build_args=-sim vcs
#ifndef NOFASTMOD
    -zeroIn_build_args=-fastmod
#endif
#ifndef ZEROINCOV
    -zeroIn_build_args="-fastsim turbo"
#else
      // This arg creates a 0in_coverage_bitmap.txt in the 0in build dir
      -zeroIn_dbg_args=+0in_debug+display_stats_in_binary+coverage_bit_map
#endif
#endif
    -zeroIn_build_args=SUNVLIBS_OTHER