Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: utilsClass.vr | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #include <vera_defines.vrh> | |
36 | #include <std_display_defines.vri> | |
37 | #include <ccxDevicesDefines.vri> | |
38 | ||
39 | #include <globals.vri> | |
40 | ||
41 | #include <std_display_class.vrh> | |
42 | #include <baseParamsClass.vrh> | |
43 | #include <sparcParams.vrh> | |
44 | #include <baseUtilsClass.vrh> | |
45 | #include <sparcBenchUtils.vrh> | |
46 | #include <memArray.vrh> | |
47 | #include <ccxPktMon.vrh> | |
48 | #include <sparcBenchUtils_if.vrh> | |
49 | ||
50 | #ifndef GATESIM | |
51 | extern verilog_task SetTrapCount(bit [8:0] count); | |
52 | #endif | |
53 | ||
54 | #define CLASSNAME Utils | |
55 | #define CLASSNAMEQ "Utils" | |
56 | ||
57 | class CLASSNAME extends SparcBenchUtils { | |
58 | ||
59 | local string className = "UtilsClass"; | |
60 | local StandardDisplay dbg; | |
61 | local integer clockPeriod; | |
62 | ||
63 | task new(StandardDisplay dbgHndl, integer clockPeriod = 100); | |
64 | ||
65 | task initTB(integer useMCUbfms = 0, | |
66 | reg useL1Tags = 0, | |
67 | reg useL2bfms = 0, | |
68 | reg loadOnlyIOmem = 1); | |
69 | ||
70 | task resetDut(); | |
71 | ||
72 | task initDut(integer wait = 0); | |
73 | ||
74 | task sendIntr(reg [5:0] tid, | |
75 | reg [1:0] type, | |
76 | reg [5:0] vect, | |
77 | integer sendPort = DEV_NCU); | |
78 | ||
79 | task l2_trap_count(integer count); | |
80 | ||
81 | } | |
82 | ||
83 | ||
84 | task CLASSNAME::new(StandardDisplay dbgHndl, integer clockPeriod = 100) { | |
85 | super.new(dbgHndl, clockPeriod); | |
86 | srandom(gSeed,this); | |
87 | this.dbg = dbgHndl; | |
88 | void = randomize(); // keep! | |
89 | } | |
90 | ||
91 | ||
92 | task CLASSNAME::resetDut() | |
93 | { | |
94 | super.resetDut(); | |
95 | } | |
96 | ||
97 | task CLASSNAME::initTB(integer useMCUbfms = 0, | |
98 | reg useL1Tags = 0, | |
99 | reg useL2bfms = 0, | |
100 | reg loadOnlyIOmem = 1) { | |
101 | ||
102 | // mem array. | |
103 | // 3rd param will return random data (in place of 0) from mem if set. | |
104 | gMem = new(0,gDbg,0); | |
105 | ||
106 | // Initialize main memory from mem.image | |
107 | gMem.loadMem("mem.image", loadOnlyIOmem); | |
108 | ||
109 | ||
110 | // Put all binds into global handles so that various objects | |
111 | // will have access to HW. | |
112 | ||
113 | // SPC | |
114 | gPcxPort[DEV_SPC0] = pcxBindDEV_SPC0; | |
115 | gCpxPort[DEV_SPC0] = cpxBindDEV_SPC0; | |
116 | gPcxPort[DEV_SPC1] = pcxBindDEV_SPC1; | |
117 | gCpxPort[DEV_SPC1] = cpxBindDEV_SPC1; | |
118 | gPcxPort[DEV_SPC2] = pcxBindDEV_SPC2; | |
119 | gCpxPort[DEV_SPC2] = cpxBindDEV_SPC2; | |
120 | gPcxPort[DEV_SPC3] = pcxBindDEV_SPC3; | |
121 | gCpxPort[DEV_SPC3] = cpxBindDEV_SPC3; | |
122 | gPcxPort[DEV_SPC4] = pcxBindDEV_SPC4; | |
123 | gCpxPort[DEV_SPC4] = cpxBindDEV_SPC4; | |
124 | gPcxPort[DEV_SPC5] = pcxBindDEV_SPC5; | |
125 | gCpxPort[DEV_SPC5] = cpxBindDEV_SPC5; | |
126 | gPcxPort[DEV_SPC6] = pcxBindDEV_SPC6; | |
127 | gCpxPort[DEV_SPC6] = cpxBindDEV_SPC6; | |
128 | gPcxPort[DEV_SPC7] = pcxBindDEV_SPC7; | |
129 | gCpxPort[DEV_SPC7] = cpxBindDEV_SPC7; | |
130 | ||
131 | // L2 | |
132 | #ifndef RTL_NO_BNK01 | |
133 | gPcxPort[DEV_MEM0] = pcxBindDEV_MEM0; | |
134 | gCpxPort[DEV_MEM0] = cpxBindDEV_MEM0; | |
135 | gPcxPort[DEV_MEM1] = pcxBindDEV_MEM1; | |
136 | gCpxPort[DEV_MEM1] = cpxBindDEV_MEM1; | |
137 | #endif | |
138 | #ifndef RTL_NO_BNK23 | |
139 | gPcxPort[DEV_MEM2] = pcxBindDEV_MEM2; | |
140 | gCpxPort[DEV_MEM2] = cpxBindDEV_MEM2; | |
141 | gPcxPort[DEV_MEM3] = pcxBindDEV_MEM3; | |
142 | gCpxPort[DEV_MEM3] = cpxBindDEV_MEM3; | |
143 | #endif | |
144 | #ifndef RTL_NO_BNK45 | |
145 | gPcxPort[DEV_MEM4] = pcxBindDEV_MEM4; | |
146 | gCpxPort[DEV_MEM4] = cpxBindDEV_MEM4; | |
147 | gPcxPort[DEV_MEM5] = pcxBindDEV_MEM5; | |
148 | gCpxPort[DEV_MEM5] = cpxBindDEV_MEM5; | |
149 | #endif | |
150 | #ifndef RTL_NO_BNK67 | |
151 | gPcxPort[DEV_MEM6] = pcxBindDEV_MEM6; | |
152 | gCpxPort[DEV_MEM6] = cpxBindDEV_MEM6; | |
153 | gPcxPort[DEV_MEM7] = pcxBindDEV_MEM7; | |
154 | gCpxPort[DEV_MEM7] = cpxBindDEV_MEM7; | |
155 | #endif | |
156 | ||
157 | // ncu | |
158 | gPcxPort[DEV_NCU] = pcxBindDEV_NCU; | |
159 | gCpxPort[DEV_NCU] = cpxBindDEV_NCU; | |
160 | ||
161 | // basic probes | |
162 | gProbesPort = probesBind; | |
163 | ||
164 | ||
165 | // if NCU RTL, ldStSync needs to look in RTL | |
166 | #ifndef NCURTL | |
167 | gLdStSyncPort[16] = ldStSync_bind_b8; | |
168 | #endif | |
169 | ||
170 | ||
171 | } | |
172 | ||
173 | ||
174 | task CLASSNAME::initDut(integer wait = 0) { | |
175 | ||
176 | integer i; | |
177 | VeraRandomState rstate; | |
178 | ||
179 | ||
180 | // wait for reset done | |
181 | if (probe_if.rst_l !== 1) @(posedge probe_if.rst_l); | |
182 | if (probe_if.flush_reset_complete !== 1) @(posedge probe_if.flush_reset_complete); | |
183 | ||
184 | ||
185 | // optional packet printing AFTER flush_reset_complete | |
186 | if (gParam.ccxPktPrintOn) { | |
187 | CCXpktMon pktMon[17]; | |
188 | ||
189 | ||
190 | getstate(rstate); | |
191 | vera_save_rng_state(this); | |
192 | ||
193 | for (i=DEV_SPC0;i<=DEV_SPC7; i++) { // 0-7 | |
194 | if (gParam.coreAvilable[i]) pktMon[i] = new(i, gPcxPort[i], gCpxPort[i]); | |
195 | else pktMon[i] = null; | |
196 | } | |
197 | for (i=DEV_MEM0;i<=DEV_MEM7; i++) { | |
198 | if (gParam.banksMask[i-8]) pktMon[i] = new(i, gPcxPort[i], gCpxPort[i]); | |
199 | else pktMon[i] = null; | |
200 | } | |
201 | pktMon[DEV_NCU] = new(DEV_NCU, gPcxPort[DEV_NCU], gCpxPort[DEV_NCU]); | |
202 | ||
203 | ||
204 | setstate(rstate); | |
205 | vera_restore_rng_state(this); | |
206 | } | |
207 | ||
208 | repeat (wait) @(posedge CLOCK); | |
209 | } | |
210 | ||
211 | //task for err injector L2 | |
212 | task CLASSNAME::l2_trap_count(integer count) | |
213 | { | |
214 | #ifndef GATESIM | |
215 | SetTrapCount(count); | |
216 | #endif | |
217 | } | |
218 | ||
219 | ||
220 | // generic call to send intr from NCU port. for $EV user events | |
221 | task CLASSNAME::sendIntr(reg [5:0] tid, | |
222 | reg [1:0] type, | |
223 | reg [5:0] vect, | |
224 | integer sendPort = DEV_NCU) | |
225 | { | |
226 | // CpxPkt reqPkt; | |
227 | // | |
228 | // reqPkt = new(); | |
229 | // reqPkt.createIntr(tid,type,vect); // INTR_RESET,INTR_POR | |
230 | // reqPkt.sendPorts = 1 << sendPort; | |
231 | // reqPkt.targetPorts = 1 << tid[5:3]; | |
232 | // PR_NORMAL(CLASSNAMEQ, MON_NORMAL, | |
233 | // psprintf ("Send Interrupt to C%0d T%0d type=%b vector=%b", | |
234 | // tid[5:3],tid[2:0],type,vect)); | |
235 | // reqPkt.send(1); | |
236 | } | |
237 |