// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: utilsClass.vr
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// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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// it under the terms of the GNU General Public License as published by
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// choice is available it will apply instead, Sun elects to use only
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// ========== Copyright Header End ============================================
#include <vera_defines.vrh>
#include <std_display_defines.vri>
#include <ccxDevicesDefines.vri>
#include <std_display_class.vrh>
#include <baseParamsClass.vrh>
#include <sparcParams.vrh>
#include <baseUtilsClass.vrh>
#include <sparcBenchUtils.vrh>
#include <sparcBenchUtils_if.vrh>
extern verilog_task SetTrapCount(bit [8:0] count);
#define CLASSNAMEQ "Utils"
class CLASSNAME extends SparcBenchUtils {
local string className = "UtilsClass";
local StandardDisplay dbg;
local integer clockPeriod;
task new(StandardDisplay dbgHndl, integer clockPeriod = 100);
task initTB(integer useMCUbfms = 0,
task initDut(integer wait = 0);
task sendIntr(reg [5:0] tid,
integer sendPort = DEV_NCU);
task l2_trap_count(integer count);
task CLASSNAME::new(StandardDisplay dbgHndl, integer clockPeriod = 100) {
super.new(dbgHndl, clockPeriod);
void = randomize(); // keep!
task CLASSNAME::resetDut()
task CLASSNAME::initTB(integer useMCUbfms = 0,
// 3rd param will return random data (in place of 0) from mem if set.
// Initialize main memory from mem.image
gMem.loadMem("mem.image", loadOnlyIOmem);
// Put all binds into global handles so that various objects
// will have access to HW.
gPcxPort[DEV_SPC0] = pcxBindDEV_SPC0;
gCpxPort[DEV_SPC0] = cpxBindDEV_SPC0;
gPcxPort[DEV_SPC1] = pcxBindDEV_SPC1;
gCpxPort[DEV_SPC1] = cpxBindDEV_SPC1;
gPcxPort[DEV_SPC2] = pcxBindDEV_SPC2;
gCpxPort[DEV_SPC2] = cpxBindDEV_SPC2;
gPcxPort[DEV_SPC3] = pcxBindDEV_SPC3;
gCpxPort[DEV_SPC3] = cpxBindDEV_SPC3;
gPcxPort[DEV_SPC4] = pcxBindDEV_SPC4;
gCpxPort[DEV_SPC4] = cpxBindDEV_SPC4;
gPcxPort[DEV_SPC5] = pcxBindDEV_SPC5;
gCpxPort[DEV_SPC5] = cpxBindDEV_SPC5;
gPcxPort[DEV_SPC6] = pcxBindDEV_SPC6;
gCpxPort[DEV_SPC6] = cpxBindDEV_SPC6;
gPcxPort[DEV_SPC7] = pcxBindDEV_SPC7;
gCpxPort[DEV_SPC7] = cpxBindDEV_SPC7;
gPcxPort[DEV_MEM0] = pcxBindDEV_MEM0;
gCpxPort[DEV_MEM0] = cpxBindDEV_MEM0;
gPcxPort[DEV_MEM1] = pcxBindDEV_MEM1;
gCpxPort[DEV_MEM1] = cpxBindDEV_MEM1;
gPcxPort[DEV_MEM2] = pcxBindDEV_MEM2;
gCpxPort[DEV_MEM2] = cpxBindDEV_MEM2;
gPcxPort[DEV_MEM3] = pcxBindDEV_MEM3;
gCpxPort[DEV_MEM3] = cpxBindDEV_MEM3;
gPcxPort[DEV_MEM4] = pcxBindDEV_MEM4;
gCpxPort[DEV_MEM4] = cpxBindDEV_MEM4;
gPcxPort[DEV_MEM5] = pcxBindDEV_MEM5;
gCpxPort[DEV_MEM5] = cpxBindDEV_MEM5;
gPcxPort[DEV_MEM6] = pcxBindDEV_MEM6;
gCpxPort[DEV_MEM6] = cpxBindDEV_MEM6;
gPcxPort[DEV_MEM7] = pcxBindDEV_MEM7;
gCpxPort[DEV_MEM7] = cpxBindDEV_MEM7;
gPcxPort[DEV_NCU] = pcxBindDEV_NCU;
gCpxPort[DEV_NCU] = cpxBindDEV_NCU;
gProbesPort = probesBind;
// if NCU RTL, ldStSync needs to look in RTL
gLdStSyncPort[16] = ldStSync_bind_b8;
task CLASSNAME::initDut(integer wait = 0) {
if (probe_if.rst_l !== 1) @(posedge probe_if.rst_l);
if (probe_if.flush_reset_complete !== 1) @(posedge probe_if.flush_reset_complete);
// optional packet printing AFTER flush_reset_complete
if (gParam.ccxPktPrintOn) {
vera_save_rng_state(this);
for (i=DEV_SPC0;i<=DEV_SPC7; i++) { // 0-7
if (gParam.coreAvilable[i]) pktMon[i] = new(i, gPcxPort[i], gCpxPort[i]);
for (i=DEV_MEM0;i<=DEV_MEM7; i++) {
if (gParam.banksMask[i-8]) pktMon[i] = new(i, gPcxPort[i], gCpxPort[i]);
pktMon[DEV_NCU] = new(DEV_NCU, gPcxPort[DEV_NCU], gCpxPort[DEV_NCU]);
vera_restore_rng_state(this);
repeat (wait) @(posedge CLOCK);
//task for err injector L2
task CLASSNAME::l2_trap_count(integer count)
// generic call to send intr from NCU port. for $EV user events
task CLASSNAME::sendIntr(reg [5:0] tid,
integer sendPort = DEV_NCU)
// reqPkt.createIntr(tid,type,vect); // INTR_RESET,INTR_POR
// reqPkt.sendPorts = 1 << sendPort;
// reqPkt.targetPorts = 1 << tid[5:3];
// PR_NORMAL(CLASSNAMEQ, MON_NORMAL,
// psprintf ("Send Interrupt to C%0d T%0d type=%b vector=%b",
// tid[5:3],tid[2:0],type,vect));