Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / ilu_peu / ilu_peu_rtl_encrypted.axis.flist

+incdir+$DV_ROOT/design/dmu/dmu_l/dmu/rtl
+incdir+$DV_ROOT/design/peu/peu_l/peu/rtl
+incdir+$DV_ROOT/design/pcie_common/include/rtl
+incdir+$DV_ROOT/design/pcie_common/csr/rtl

+incdir+$DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/
$DV_ROOT/design/peu/peu_l/peu/rtl/peu.h
$DV_ROOT/design/pcie_common/include/rtl/pcie.h
$DV_ROOT/design/pcie_common/csr/rtl/pcie_csr_defines.h

$DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/pcie_defs.vh
$DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/dlpl_defs.vh
$DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/dlpl_hdr.vh
$DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/dlpl_lib.vh
// AT, 12/20/04: Not needed  $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/adm_defs.vh
$DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/dlpl_user.vh
$DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/port_cfg.vh

$DV_ROOT/design/plp/plp_l/plp/rtl/plp.vp
$DV_ROOT/design/plp/plp_tlg_l/plp_tlg/rtl/plp_tlg.vp
// $DV_ROOT/design/plp/plp_cdm_l/plp_cdm/rtl/cdm.vp
// $DV_ROOT/design/plp/plp_cdm_l/plp_cdm/rtl/cdm_pl_reg.vp
// $DV_ROOT/design/plp/plp_cdm_l/plp_cdm/rtl/cdm_reg_decode.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_1sx16.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_deskew_1sx16.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_deskew_slv_1s.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_deskew_slv_1sx16.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_link_1sx16.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_pipe.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_pkt_finder_1sx16.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_seq_finder_1s.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_seq_finder_1sx16.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/scramble.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/scramble_x16.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/xmlh_1sx16.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/xmlh_byte_xmt_1sx16.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/xmlh_ltssm.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/xmlh_pipe.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/rdlh_128b.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/rdlh_dlp_extract.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/rdlh_link_cntrl.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/rdlh_tlp_extract_128b.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/xdlh_128b.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/xdlh_control_128b.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/xdlh_dllp_gen.vp
// Rmvd from Cascade 2.1 Rls: $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/xdlh_insert_crc.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/xdlh_retrybuf_128b.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/xdlh_tlp_gen_128b.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_tlh/rtl/rtlh_128b.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_tlh/rtl/rtlh_fc.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_tlh/rtl/rtlh_fc_arb.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_tlh/rtl/rtlh_fc_decode.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_tlh/rtl/rtlh_fc_gen.vp
$DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/loopback_1s.vp
$DV_ROOT/design/plp/plp_phy_l/plp_phy/rtl/phy_1s.vp
$DV_ROOT/verif/model/verilog/pcie/ept/phy_1sx16.v
$DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/pipe2phy_1s.vp
// $DV_ROOT/design/plp/plp_phy_l/plp_phy/rtl/pipe_multilane.vp
$DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/rphy_8b10b_1s.vp
$DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/rphy_cdet_1s.vp
$DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/rphy_elasbuf_1s.vp
$DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/sdm_1s.vp
$DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/xphy_8b10b_1s.vp
//$DV_ROOT/design/plp/plp_phy_l/plp_sds/rtl/serdes_1s.vp
//$DV_ROOT/design/plp/plp_phy_l/plp_sds/rtl/rphy_deser_1s.vp
//$DV_ROOT/design/plp/plp_phy_l/plp_sds/rtl/xphy_ser_1s.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/crc_128b.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/decode8b10b.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/delay_n.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/encode8b10b.vp
// $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/sync.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/cx_pl_16A.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_reverse.vp
$DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/xmlh_reverse.vp
$DV_ROOT/design/peu/peu_l/peu/rtl/peu.v


$DV_ROOT/libs/n2sram/async/n2_com_64x132async_dp_cust_l/n2_com_64x132async_dp_cust/rtl/n2_com_64x132async_dp_cust_array.v
$DV_ROOT/libs/n2sram/async/n2_com_64x132async_dp_cust_l/n2_com_64x132async_dp_cust/rtl/n2_com_64x132async_dp_cust.v
$DV_ROOT/libs/n2sram/async/n2_com_256x132async_dp_cust_l/n2_com_256x132async_dp_cust/rtl/n2_com_256x132async_dp_cust_array.v
$DV_ROOT/libs/n2sram/async/n2_com_256x132async_dp_cust_l/n2_com_256x132async_dp_cust/rtl/n2_com_256x132async_dp_cust.v
$DV_ROOT/libs/n2sram/dp/n2_peu_dp_256x138s_cust_l/n2_peu_dp_256x138s_cust/rtl/n2_peu_dp_256x138s_cust_array.v
$DV_ROOT/libs/n2sram/dp/n2_peu_dp_256x138s_cust_l/n2_peu_dp_256x138s_cust/rtl/n2_peu_dp_256x138s_cust.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_defines.h
// $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_lpr_defines.h
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_ctl_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_ctl.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_sts_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_sts.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_trn_off_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_trn_off.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_ici_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_ici.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_diag_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_diag.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_oe_log_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_oe_log.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_oe_int_en_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_oe_int_en.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_oe_err_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_oe_err.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_roe_hdr1_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_roe_hdr1.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_roe_hdr2_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_roe_hdr2.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_toe_hdr1_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_toe_hdr1.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_toe_hdr2_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_toe_hdr2.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prfc_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prfc.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prf0_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prf0.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prf1_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prf1.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prf2_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prf2.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_dbg_sel_a_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_dbg_sel_a.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_dbg_sel_b_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_dbg_sel_b.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_dev_cap_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_dev_cap.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_dev_ctl_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_dev_ctl.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_dev_sts_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_dev_sts.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lnk_cap_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lnk_cap.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lnk_ctl_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lnk_ctl.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lnk_sts_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lnk_sts.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ue_log_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ue_log.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ue_int_en_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ue_int_en.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ue_err_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ue_err.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_rue_hdr1_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_rue_hdr1.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_rue_hdr2_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_rue_hdr2.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tue_hdr1_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tue_hdr1.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tue_hdr2_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tue_hdr2.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ce_log_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ce_log.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ce_int_en_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ce_int_en.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ce_err_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ce_err.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csrpipe_50.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csrpipe_5.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_peu_dlpl_serdes_rev_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_peu_dlpl_serdes_rev.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_acknak_thresh_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_acknak_thresh.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_acknak_timer_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_acknak_timer.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_replay_tim_thresh_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_replay_tim_thresh.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_replay_timer_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_replay_timer.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ven_dllp_msg_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ven_dllp_msg.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_force_ltssm_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_force_ltssm.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_link_cfg_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_link_cfg.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_link_ctl_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_link_ctl.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lane_skew_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lane_skew.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_symbol_num_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_symbol_num.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_symbol_timer_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_symbol_timer.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_pll_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_pll.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_receiver_lane_ctl_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_receiver_lane_ctl.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_receiver_lane_status_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_receiver_lane_status.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_xmitter_lane_ctl_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_xmitter_lane_ctl.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_xmitter_lane_status_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_xmitter_lane_status.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_macro_test_cfg_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_macro_test_cfg.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_core_status_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_core_status.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_event_err_int_en_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_event_err_int_en.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_event_err_log_en_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_event_err_log_en.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_event_err_sts_clr_entry.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_event_err_sts_clr.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_default_grp.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_stage_mux_only.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_addr_decode.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr.v
// $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_lpr_csr.v
$DV_ROOT/design/ptl/ptl_l/ptl/rtl/ptl.h
$DV_ROOT/design/ptl/ptl_l/ptl/rtl/ptl.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb.v
// $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_lpr.v
// $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_lpr_ahb.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr.v
$DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_rio.v
$DV_ROOT/design/ptl/ptl_sbs_l/ptl_sbs/rtl/ptl_sbs.v
$DV_ROOT/design/ptl/ptl_mb0_l/ptl_mb0/rtl/ptl_mb0.v
$DV_ROOT/design/ptl/ptl_edb_l/ptl_edb/rtl/ptl_edb.v
$DV_ROOT/design/ptl/ptl_ehb_l/ptl_ehb/rtl/ptl_ehb.v
$DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl.h
$DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl.v
$DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl_hcs.v
$DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl_hps.v
$DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl_fcs.v
$DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl_rcs.v
$DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl_lcs.v
$DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl_dbg.v
$DV_ROOT/design/ptl/ptl_idb_l/ptl_idb/rtl/ptl_idb.v
$DV_ROOT/design/ptl/ptl_ihb_l/ptl_ihb/rtl/ptl_ihb.v
$DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl.h
$DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl.v
$DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl_idc.v
$DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl_ifc.v
$DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl_ihc.v
$DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl_ihp.v
$DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl_ipp.v
$DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl_itc.v
$DV_ROOT/design/ptl/ptl_pmc_l/ptl_pmc/rtl/ptl_pmc.v
$DV_ROOT/design/ptl/ptl_pmc_l/ptl_pmc/rtl/ptl_pmc_tpm.v
$DV_ROOT/design/ptl/ptl_pmc_l/ptl_pmc/rtl/ptl_pmc_lpm.v
$DV_ROOT/design/ptl/ptl_rsb_l/ptl_rsb/rtl/ptl_rsb.h
$DV_ROOT/design/ptl/ptl_rsb_l/ptl_rsb/rtl/ptl_rsb.v
$DV_ROOT/design/ptl/ptl_rsb_l/ptl_rsb/rtl/ptl_rsb_rar.v
$DV_ROOT/design/ptl/ptl_rsb_l/ptl_rsb/rtl/ptl_rsb_ctrl.v

//
$DV_ROOT/design/psr/psr_l/psr/rtl/psr.v
//make serdes files libraries, so they disappear when using PEP
-v $DV_ROOT/design/psr/psr_l/psr/rtl/wiz6c2b8n5d2t.v
-v $DV_ROOT/design/psr/psr_l/psr/rtl/WIZ6C2XXN5X2.vp
-v $DV_ROOT/design/psr/psr_l/psr/rtl/NIAGARA2_REFCLK_BOTTOM1.v
-v $DV_ROOT/libs/serdes/ljcb/ljcb_l/iclkrx18gat/rtl/iclkrx18gat.v