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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / ilu_peu / soma_fastlink.soma
CommitLineData
86530b38
AT		 1<soma original.input.version="0.001">
2 <!--
3======================================================================
4Copyright 1999-2003 by Denali Software, Inc. All rights reserved.
5======================================================================
6
7This SOMA file describes a memory model, using Denali Software's
8proprietary SOMA language. By using this SOMA file, you agree to the
9following terms. If you do not agree to these terms, you may not use
10this SOMA file.
11
12Subject to the restrictions set forth below, Denali Software grants
13you a non-exclusive, non-transferable license only to use this SOMA
14file to simulate the memory described in it using tools supplied by
15Denali Software.
16
17You may not:
18
19 (1) Use this SOMA file to create software programs or tools that use
20 SOMA files as either input or output.
21
22 (2) Modify this SOMA file or the SOMA language in any manner.
23
24 (3) Use this SOMA file to create other languages for describing
25 memory models.
26
27 (4) Distribute this SOMA file to others.
28
29This SOMA file is based on information received by Denali Software
30from third parties. DENALI SOFTWARE PROVIDES THIS SOMA FILE "AS IS"
31AND EXPRESSLY DISCLAIMS ALL REPRESENTATIONS, WARRANTIES AND
32CONDITIONS, INCLUDING BUT NOT LIMITED TO WARRANTIES AND CONDITIONS OF
33MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND
34NONINFRINGEMENT. DENALI SOFTWARE'S AGGREGATE LIABILITY ARISING FROM
35YOUR USE OF THIS SOMA FILE IS LIMITED TO ONE U.S. DOLLAR.
36
37If you have any questions or if you would like to inquire about
38obtaining additional or different rights in SOMA files or the SOMA
39language, please contact Denali Software, at www.denali.com or at
40info@denalisoft.com.
41
42Written on 03 Apr 2003
43PureView version: 3.100 $DENALI: /home/scratch/guoqing/work/main/platform/SunOS/denali-->
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1601 <value>0</value>
1602 </feature>
1603 <feature name="PCIEXpbDrail7">
1604 <value>0</value>
1605 </feature>
1606 <feature name="PCIEXpbC">
1607 <value>0</value>
1608 </feature>
1609 <feature name="PCIEXpbCsys">
1610 <value>0</value>
1611 </feature>
1612 <feature name="prot">
1613 <value>1</value>
1614 </feature>
1615 <feature name="PL">
1616 <value>1</value>
1617 </feature>
1618 <feature name="supportLaneReversal">
1619 <value>1</value>
1620 </feature>
1621 <feature name="reverseLanes">
1622 <value>0</value>
1623 </feature>
1624 <feature name="elecIdleValue">
1625 <value>1</value>
1626 </feature>
1627 <feature name="elecIdleValue0">
1628 <value>0</value>
1629 </feature>
1630 <feature name="elecIdleValue1">
1631 <value>1</value>
1632 </feature>
1633 <feature name="elecIdleValueZ">
1634 <value>0</value>
1635 </feature>
1636 <feature name="usePosSKP">
1637 <value>0</value>
1638 </feature>
1639 <feature name="DLL">
1640 <value>0</value>
1641 </feature>
1642 <feature name="TL">
1643 <value>1</value>
1644 </feature>
1645 <feature name="application">
1646 <value>0</value>
1647 </feature>
1648 <feature name="Sideband">
1649 <value>1</value>
1650 </feature>
1651 <feature name="sbWake">
1652 <value>0</value>
1653 </feature>
1654 <feature name="sbReset">
1655 <value>1</value>
1656 </feature>
1657 <feature name="PCIEXvcR2">
1658 <value>1</value>
1659 </feature>
1660 <feature name="PCIEXvcR2FC">
1661 <value>1</value>
1662 </feature>
1663 <feature name="PCIEXvcR2Ca">
1664 <value>0</value>
1665 </feature>
1666 <feature name="PCIEXvcR2Arb">
1667 <value>0</value>
1668 </feature>
1669 <feature name="PCIEXvcR2Arb0">
1670 <value>1</value>
1671 </feature>
1672 <feature name="PCIEXvcR2Arb1">
1673 <value>0</value>
1674 </feature>
1675 <feature name="PCIEXvcR2Arb2">
1676 <value>0</value>
1677 </feature>
1678 <feature name="PCIEXvcR2Arb3">
1679 <value>0</value>
1680 </feature>
1681 <feature name="PCIEXvcR2Arb4">
1682 <value>0</value>
1683 </feature>
1684 <feature name="PCIEXvcR2Arb5">
1685 <value>0</value>
1686 </feature>
1687 <feature name="PCIEXvcR2APS">
1688 <value>0</value>
1689 </feature>
1690 <feature name="PCIEXvcR2snoop">
1691 <value>0</value>
1692 </feature>
1693 <feature name="PCIEXvcR2CT">
1694 <value>0</value>
1695 </feature>
1696 <feature name="PCIEXvcR3">
1697 <value>1</value>
1698 </feature>
1699 <feature name="PCIEXvcR3FC">
1700 <value>1</value>
1701 </feature>
1702 <feature name="PCIEXvcR3Ca">
1703 <value>0</value>
1704 </feature>
1705 <feature name="PCIEXvcR3Arb">
1706 <value>0</value>
1707 </feature>
1708 <feature name="PCIEXvcR3Arb0">
1709 <value>1</value>
1710 </feature>
1711 <feature name="PCIEXvcR3Arb1">
1712 <value>0</value>
1713 </feature>
1714 <feature name="PCIEXvcR3Arb2">
1715 <value>0</value>
1716 </feature>
1717 <feature name="PCIEXvcR3Arb3">
1718 <value>0</value>
1719 </feature>
1720 <feature name="PCIEXvcR3Arb4">
1721 <value>0</value>
1722 </feature>
1723 <feature name="PCIEXvcR3Arb5">
1724 <value>0</value>
1725 </feature>
1726 <feature name="PCIEXvcR3APS">
1727 <value>0</value>
1728 </feature>
1729 <feature name="PCIEXvcR3snoop">
1730 <value>0</value>
1731 </feature>
1732 <feature name="PCIEXvcR3CT">
1733 <value>0</value>
1734 </feature>
1735 <feature name="PCIEXvcR4">
1736 <value>1</value>
1737 </feature>
1738 <feature name="PCIEXvcR4FC">
1739 <value>1</value>
1740 </feature>
1741 <feature name="PCIEXvcR4Ca">
1742 <value>0</value>
1743 </feature>
1744 <feature name="PCIEXvcR4Arb">
1745 <value>0</value>
1746 </feature>
1747 <feature name="PCIEXvcR4Arb0">
1748 <value>1</value>
1749 </feature>
1750 <feature name="PCIEXvcR4Arb1">
1751 <value>0</value>
1752 </feature>
1753 <feature name="PCIEXvcR4Arb2">
1754 <value>0</value>
1755 </feature>
1756 <feature name="PCIEXvcR4Arb3">
1757 <value>0</value>
1758 </feature>
1759 <feature name="PCIEXvcR4Arb4">
1760 <value>0</value>
1761 </feature>
1762 <feature name="PCIEXvcR4Arb5">
1763 <value>0</value>
1764 </feature>
1765 <feature name="PCIEXvcR4APS">
1766 <value>0</value>
1767 </feature>
1768 <feature name="PCIEXvcR4snoop">
1769 <value>0</value>
1770 </feature>
1771 <feature name="PCIEXvcR4CT">
1772 <value>0</value>
1773 </feature>
1774 <feature name="PCIEXvcR5">
1775 <value>1</value>
1776 </feature>
1777 <feature name="PCIEXvcR5FC">
1778 <value>1</value>
1779 </feature>
1780 <feature name="PCIEXvcR5Ca">
1781 <value>0</value>
1782 </feature>
1783 <feature name="PCIEXvcR5Arb">
1784 <value>0</value>
1785 </feature>
1786 <feature name="PCIEXvcR5Arb0">
1787 <value>1</value>
1788 </feature>
1789 <feature name="PCIEXvcR5Arb1">
1790 <value>0</value>
1791 </feature>
1792 <feature name="PCIEXvcR5Arb2">
1793 <value>0</value>
1794 </feature>
1795 <feature name="PCIEXvcR5Arb3">
1796 <value>0</value>
1797 </feature>
1798 <feature name="PCIEXvcR5Arb4">
1799 <value>0</value>
1800 </feature>
1801 <feature name="PCIEXvcR5Arb5">
1802 <value>0</value>
1803 </feature>
1804 <feature name="PCIEXvcR5APS">
1805 <value>0</value>
1806 </feature>
1807 <feature name="PCIEXvcR5snoop">
1808 <value>0</value>
1809 </feature>
1810 <feature name="PCIEXvcR5CT">
1811 <value>0</value>
1812 </feature>
1813 <feature name="PCIEXvcR6">
1814 <value>1</value>
1815 </feature>
1816 <feature name="PCIEXvcR6FC">
1817 <value>1</value>
1818 </feature>
1819 <feature name="PCIEXvcR6Ca">
1820 <value>0</value>
1821 </feature>
1822 <feature name="PCIEXvcR6Arb">
1823 <value>0</value>
1824 </feature>
1825 <feature name="PCIEXvcR6Arb0">
1826 <value>1</value>
1827 </feature>
1828 <feature name="PCIEXvcR6Arb1">
1829 <value>0</value>
1830 </feature>
1831 <feature name="PCIEXvcR6Arb2">
1832 <value>0</value>
1833 </feature>
1834 <feature name="PCIEXvcR6Arb3">
1835 <value>0</value>
1836 </feature>
1837 <feature name="PCIEXvcR6Arb4">
1838 <value>0</value>
1839 </feature>
1840 <feature name="PCIEXvcR6Arb5">
1841 <value>0</value>
1842 </feature>
1843 <feature name="PCIEXvcR6APS">
1844 <value>0</value>
1845 </feature>
1846 <feature name="PCIEXvcR6snoop">
1847 <value>0</value>
1848 </feature>
1849 <feature name="PCIEXvcR6CT">
1850 <value>0</value>
1851 </feature>
1852 <feature name="PCIEXvcR7">
1853 <value>1</value>
1854 </feature>
1855 <feature name="PCIEXvcR7FC">
1856 <value>1</value>
1857 </feature>
1858 <feature name="PCIEXvcR7Ca">
1859 <value>0</value>
1860 </feature>
1861 <feature name="PCIEXvcR7Arb">
1862 <value>0</value>
1863 </feature>
1864 <feature name="PCIEXvcR7Arb0">
1865 <value>1</value>
1866 </feature>
1867 <feature name="PCIEXvcR7Arb1">
1868 <value>0</value>
1869 </feature>
1870 <feature name="PCIEXvcR7Arb2">
1871 <value>0</value>
1872 </feature>
1873 <feature name="PCIEXvcR7Arb3">
1874 <value>0</value>
1875 </feature>
1876 <feature name="PCIEXvcR7Arb4">
1877 <value>0</value>
1878 </feature>
1879 <feature name="PCIEXvcR7Arb5">
1880 <value>0</value>
1881 </feature>
1882 <feature name="PCIEXvcR7APS">
1883 <value>0</value>
1884 </feature>
1885 <feature name="PCIEXvcR7snoop">
1886 <value>0</value>
1887 </feature>
1888 <feature name="PCIEXvcR7CT">
1889 <value>0</value>
1890 </feature>
1891 <feature name="pipeDevice">
1892 <value>0</value>
1893 </feature>
1894 <feature name="pipeMacro">
1895 <value>0</value>
1896 </feature>
1897 <feature name="pipe8bit">
1898 <value>1</value>
1899 </feature>
1900 <feature name="pipe16bit">
1901 <value>0</value>
1902 </feature>
1903 <feature name="RCRB">
1904 <value>0</value>
1905 </feature>
1906 <feature name="BARspec">
1907 <value>1</value>
1908 </feature>
1909 <feature name="ROMbase0">
1910 <value>0</value>
1911 </feature>
1912 <feature name="BrSecLat">
1913 <value>1</value>
1914 </feature>
1915 <feature name="BrSLTBurst2">
1916 <value>1</value>
1917 </feature>
1918 <feature name="BrSLT8">
1919 <value>0</value>
1920 </feature>
1921 <feature name="BrSLThardW">
1922 <value>0</value>
1923 </feature>
1924 <feature name="BrSecSt">
1925 <value>0</value>
1926 </feature>
1927 <feature name="BrSecSt66">
1928 <value>0</value>
1929 </feature>
1930 <feature name="BrSecStB2B">
1931 <value>0</value>
1932 </feature>
1933 <feature name="BrSecStDev">
1934 <value>0</value>
1935 </feature>
1936 <feature name="BrSecStDev0">
1937 <value>1</value>
1938 </feature>
1939 <feature name="BrSecStDev1">
1940 <value>0</value>
1941 </feature>
1942 <feature name="BrSecStDev2">
1943 <value>0</value>
1944 </feature>
1945 <feature name="ROMbase1">
1946 <value>0</value>
1947 </feature>
1948 <feature name="BrISA">
1949 <value>0</value>
1950 </feature>
1951 <feature name="BrVGA">
1952 <value>0</value>
1953 </feature>
1954 <feature name="BrVGA16">
1955 <value>0</value>
1956 </feature>
1957 <feature name="BrMasterAbort">
1958 <value>0</value>
1959 </feature>
1960 <feature name="BrFastB2B">
1961 <value>0</value>
1962 </feature>
1963 <feature name="BrSecDCTimer">
1964 <value>0</value>
1965 </feature>
1966 <feature name="BrTimerSerrEn">
1967 <value>0</value>
1968 </feature>
1969 <feature name="PMEsupport">
1970 <value>0</value>
1971 </feature>
1972 <feature name="PMEd0">
1973 <value>1</value>
1974 </feature>
1975 <feature name="PMEd1">
1976 <value>1</value>
1977 </feature>
1978 <feature name="PMEd2">
1979 <value>1</value>
1980 </feature>
1981 <feature name="MSIen">
1982 <value>0</value>
1983 </feature>
1984 <feature name="AGP">
1985 <value>0</value>
1986 </feature>
1987 <feature name="VPD">
1988 <value>0</value>
1989 </feature>
1990 <feature name="SLOT">
1991 <value>0</value>
1992 </feature>
1993 <feature name="HS">
1994 <value>0</value>
1995 </feature>
1996 <feature name="PCIX">
1997 <value>0</value>
1998 </feature>
1999 <feature name="AMD">
2000 <value>0</value>
2001 </feature>
2002 <feature name="VS">
2003 <value>0</value>
2004 </feature>
2005 <feature name="DP">
2006 <value>0</value>
2007 </feature>
2008 <feature name="CRC">
2009 <value>0</value>
2010 </feature>
2011 <feature name="HotPlug">
2012 <value>0</value>
2013 </feature>
2014 <feature name="PCIElcAspmDis">
2015 <value>1</value>
2016 </feature>
2017 <feature name="PCIEXae2UM">
2018 <value>0</value>
2019 </feature>
2020 <feature name="PCIEXae2UMta">
2021 <value>0</value>
2022 </feature>
2023 <feature name="PCIEXae2UMma">
2024 <value>0</value>
2025 </feature>
2026 <feature name="PCIEXae2UMrta">
2027 <value>0</value>
2028 </feature>
2029 <feature name="PCIEXae2UMrma">
2030 <value>1</value>
2031 </feature>
2032 <feature name="PCIEXae2UMue">
2033 <value>1</value>
2034 </feature>
2035 <feature name="PCIEXae2UMucMsg">
2036 <value>0</value>
2037 </feature>
2038 <feature name="PCIEXae2UMucData">
2039 <value>1</value>
2040 </feature>
2041 <feature name="PCIEXae2UMucAttr">
2042 <value>1</value>
2043 </feature>
2044 <feature name="PCIEXae2UMucAddr">
2045 <value>1</value>
2046 </feature>
2047 <feature name="PCIEXae2UMdelay">
2048 <value>1</value>
2049 </feature>
2050 <feature name="PCIEXae2UMperr">
2051 <value>0</value>
2052 </feature>
2053 <feature name="PCIEXae2UMserr">
2054 <value>1</value>
2055 </feature>
2056 <feature name="PCIEXae2UMint">
2057 <value>0</value>
2058 </feature>
2059 <feature name="PCIEXae2US">
2060 <value>0</value>
2061 </feature>
2062 <feature name="PCIEXae2USta">
2063 <value>0</value>
2064 </feature>
2065 <feature name="PCIEXae2USma">
2066 <value>0</value>
2067 </feature>
2068 <feature name="PCIEXae2USrta">
2069 <value>0</value>
2070 </feature>
2071 <feature name="PCIEXae2USrma">
2072 <value>0</value>
2073 </feature>
2074 <feature name="PCIEXae2USue">
2075 <value>0</value>
2076 </feature>
2077 <feature name="PCIEXae2USucMsg">
2078 <value>1</value>
2079 </feature>
2080 <feature name="PCIEXae2USucData">
2081 <value>0</value>
2082 </feature>
2083 <feature name="PCIEXae2USucAttr">
2084 <value>1</value>
2085 </feature>
2086 <feature name="PCIEXae2USucAddr">
2087 <value>1</value>
2088 </feature>
2089 <feature name="PCIEXae2USdelay">
2090 <value>0</value>
2091 </feature>
2092 <feature name="PCIEXae2USperr">
2093 <value>0</value>
2094 </feature>
2095 <feature name="PCIEXae2USserr">
2096 <value>1</value>
2097 </feature>
2098 <feature name="PCIEXae2USint">
2099 <value>0</value>
2100 </feature>
2101 <feature name="reverseLaneNumbers">
2102 <value>0</value>
2103 </feature>
2104 <feature name="skipInterval">
2105 <value>0</value>
2106 </feature>
2107 <feature name="mergeErrMsgs">
2108 <value>0</value>
2109 </feature>
2110 <feature name="disVDMsg0">
2111 <value>0</value>
2112 </feature>
2113 <feature name="disVDMsg1">
2114 <value>0</value>
2115 </feature>
2116 <feature name="disPoisonTX">
2117 <value>0</value>
2118 </feature>
2119 <feature name="AS_EP">
2120 <value>0</value>
2121 </feature>
2122 <feature name="capSLOT1st">
2123 <value>0</value>
2124 </feature>
2125 <feature name="SSID">
2126 <value>0</value>
2127 </feature>
2128 <pin name="TX">
2129 <username>TX</username>
2130 <bits>8</bits>
2131 </pin>
2132 <pin name="TX_">
2133 <username>TX_</username>
2134 <bits>8</bits>
2135 </pin>
2136 <pin name="RX">
2137 <username>RX</username>
2138 <bits>8</bits>
2139 </pin>
2140 <pin name="RX_">
2141 <username>RX_</username>
2142 <bits>8</bits>
2143 </pin>
2144 <pin name="CLK_TX">
2145 <username>CLK_TX</username>
2146 <bits>1</bits>
2147 </pin>
2148 <pin name="CLK_RX">
2149 <username>CLK_RX</username>
2150 <bits>1</bits>
2151 </pin>
2152 <pin name="TxData">
2153 <username>TxData</username>
2154 <bits>8</bits>
2155 </pin>
2156 <pin name="TxDataK">
2157 <username>TxDataK</username>
2158 <bits>1</bits>
2159 </pin>
2160 <pin name="RxData">
2161 <username>RxData</username>
2162 <bits>8</bits>
2163 </pin>
2164 <pin name="RxDataK">
2165 <username>RxDataK</username>
2166 <bits>1</bits>
2167 </pin>
2168 <pin name="PCLK">
2169 <username>PCLK</username>
2170 <bits>1</bits>
2171 </pin>
2172 <pin name="WAKE_">
2173 <username>WAKE_</username>
2174 <bits>1</bits>
2175 </pin>
2176 <pin name="PERST_">
2177 <username>PERST_</username>
2178 <bits>1</bits>
2179 </pin>
2180 <pin name="TxDetectRx">
2181 <username>TxDetectRx</username>
2182 <bits>1</bits>
2183 </pin>
2184 <pin name="TxElecIdle">
2185 <username>TxElecIdle</username>
2186 <bits>1</bits>
2187 </pin>
2188 <pin name="TxCompliance">
2189 <username>TxCompliance</username>
2190 <bits>1</bits>
2191 </pin>
2192 <pin name="RxPolarity">
2193 <username>RxPolarity</username>
2194 <bits>1</bits>
2195 </pin>
2196 <pin name="Reset_">
2197 <username>Reset_</username>
2198 <bits>1</bits>
2199 </pin>
2200 <pin name="PowerDown">
2201 <username>PowerDown</username>
2202 <bits>2</bits>
2203 </pin>
2204 <pin name="RxValid">
2205 <username>RxValid</username>
2206 <bits>1</bits>
2207 </pin>
2208 <pin name="PhyStatus">
2209 <username>PhyStatus</username>
2210 <bits>1</bits>
2211 </pin>
2212 <pin name="RxElecIdle">
2213 <username>RxElecIdle</username>
2214 <bits>1</bits>
2215 </pin>
2216 <pin name="RxStatus">
2217 <username>RxStatus</username>
2218 <bits>3</bits>
2219 </pin>
2220 <feature name="PcieVersion">
2221 <value>1</value>
2222 </feature>
2223 <feature name="Gen1">
2224 <value>1</value>
2225 </feature>
2226 <feature name="PcieSpecVersion">
2227 <value>1</value>
2228 </feature>
2229 <feature name="SpecVersion_1_0a2">
2230 <value>1</value>
2231 </feature>
2232 <feature name="SpecVersion_1_1">
2233 <value>0</value>
2234 </feature>
2235 <feature name="RelativeOrderOnlyInitDllps">
2236 <value>0</value>
2237 </feature>
2238 <feature name="fwdErrMsgEnSerr">
2239 <value>0</value>
2240 </feature>
2241 <feature name="Gen2">
2242 <value>0</value>
2243 </feature>
2244 <feature name="EIisEIES">
2245 <value>0</value>
2246 </feature>
2247 <feature name="minK28_7L0sExit">
2248 <value>4</value>
2249 </feature>
2250 <feature name="maxK28_7L0sExit">
2251 <value>8</value>
2252 </feature>
2253 <feature name="autoChgSpd">
2254 <value>1</value>
2255 </feature>
2256 <feature name="upconfigure">
2257 <value>1</value>
2258 </feature>
2259 <feature name="discardReqFLR">
2260 <value>1</value>
2261 </feature>
2262 <feature name="discardCplFLR">
2263 <value>1</value>
2264 </feature>
2265 <feature name="sendCplFLR">
2266 <value>1</value>
2267 </feature>
2268 <feature name="waitFLR">
2269 <value>0</value>
2270 </feature>
2271 <feature name="brPciBus">
2272 <value>0</value>
2273 </feature>
2274 <feature name="brPciXBus">
2275 <value>1</value>
2276 </feature>
2277 <feature name="EPVF">
2278 <value>0</value>
2279 </feature>
2280 <feature name="RCIEP">
2281 <value>0</value>
2282 </feature>
2283 <feature name="RCEC">
2284 <value>0</value>
2285 </feature>
2286 <feature name="PHY">
2287 <value>0</value>
2288 </feature>
2289 <feature name="intLpinOrPacket">
2290 <value>1</value>
2291 </feature>
2292 <feature name="intLpin">
2293 <value>1</value>
2294 </feature>
2295 <feature name="pipeDIW8G1">
2296 <value>0</value>
2297 </feature>
2298 <feature name="pipeDIW16G1">
2299 <value>1</value>
2300 </feature>
2301 <feature name="pipeDIW8G2">
2302 <value>0</value>
2303 </feature>
2304 <feature name="pipeDIW16G2">
2305 <value>1</value>
2306 </feature>
2307 <feature name="ImTxDeemph">
2308 <value>0</value>
2309 </feature>
2310 <feature name="ImTxMargin">
2311 <value>0</value>
2312 </feature>
2313 <feature name="ImTxSwing">
2314 <value>0</value>
2315 </feature>
2316 <feature name="PL_PHY">
2317 <value>0</value>
2318 </feature>
2319 <feature name="phyLaneCount">
2320 <value>0</value>
2321 </feature>
2322 <feature name="refClkMultiplier">
2323 <value>1</value>
2324 </feature>
2325 <feature name="NFTSWithCommonClock">
2326 <value>1</value>
2327 </feature>
2328 <feature name="NFTSWithoutCommonClock">
2329 <value>4</value>
2330 </feature>
2331 <feature name="diffNFTSGen2">
2332 <value>0</value>
2333 </feature>
2334 <feature name="NFTSWithCommonClockGen2">
2335 <value>1</value>
2336 </feature>
2337 <feature name="NFTSWithoutCommonClockGen2">
2338 <value>4</value>
2339 </feature>
2340 <feature name="useMaxFtsTimeout">
2341 <value>0</value>
2342 </feature>
2343 <feature name="txBitSkewValues">
2344 <value>random</value>
2345 </feature>
2346 <feature name="unknownValue">
2347 <value>0</value>
2348 </feature>
2349 <feature name="unknownValue0">
2350 <value>0</value>
2351 </feature>
2352 <feature name="unknownValue1">
2353 <value>0</value>
2354 </feature>
2355 <feature name="unknownValueZ">
2356 <value>0</value>
2357 </feature>
2358 <feature name="unknownValueX">
2359 <value>1</value>
2360 </feature>
2361 <feature name="unknownTimingWindow">
2362 <value>0</value>
2363 </feature>
2364 <feature name="fifoRxSize">
2365 <value>26</value>
2366 </feature>
2367 <feature name="fifoTxSize">
2368 <value>26</value>
2369 </feature>
2370 <feature name="recoveryFinishesCurrentPkt">
2371 <value>0</value>
2372 </feature>
2373 <feature name="txSymbolSkewValues">
2374 <value>random</value>
2375 </feature>
2376 <feature name="capBeacon">
2377 <value>1</value>
2378 </feature>
2379 <feature name="beaconLanes">
2380 <value>0x1</value>
2381 </feature>
2382 <feature name="capLBmaster">
2383 <value>1</value>
2384 </feature>
2385 <feature name="laneLBSlaveOnly">
2386 <value>0</value>
2387 </feature>
2388 <feature name="capXLink">
2389 <value>0</value>
2390 </feature>
2391 <feature name="capFrameErr">
2392 <value>1</value>
2393 </feature>
2394 <feature name="capSymLossErr">
2395 <value>0</value>
2396 </feature>
2397 <feature name="capLnDeskewErr">
2398 <value>0</value>
2399 </feature>
2400 <feature name="capElasErr">
2401 <value>0</value>
2402 </feature>
2403 <feature name="dis8b10bCfg">
2404 <value>0</value>
2405 </feature>
2406 <feature name="dis8b10bDisabled">
2407 <value>0</value>
2408 </feature>
2409 <feature name="dis8b10bHotReset">
2410 <value>0</value>
2411 </feature>
2412 <feature name="inL0NoEIOS">
2413 <value>0</value>
2414 </feature>
2415 <feature name="ttxLoopbackDelay">
2416 <value>0</value>
2417 </feature>
2418 <feature name="ttxLoopbackUnder">
2419 <value>0</value>
2420 </feature>
2421 <feature name="ttxLoopbackOver">
2422 <value>25</value>
2423 </feature>
2424 <feature name="pollActiveLnCnt">
2425 <value>0</value>
2426 </feature>
2427 <feature name="eiesInterval">
2428 <value>32</value>
2429 </feature>
2430 <feature name="chkRsvDrate">
2431 <value>0</value>
2432 </feature>
2433 <feature name="enPollSpd">
2434 <value>0</value>
2435 </feature>
2436 <feature name="mfEcrcTlp">
2437 <value>0</value>
2438 </feature>
2439 <feature name="turnOffLane">
2440 <value>0</value>
2441 </feature>
2442 <feature name="minPLTlpBytes">
2443 <value>7500</value>
2444 </feature>
2445 <feature name="maxPLTlpBytes">
2446 <value>15000</value>
2447 </feature>
2448 <feature name="addlTS1Cfg">
2449 <value>0</value>
2450 </feature>
2451 <feature name="resetSkpTimerEItx">
2452 <value>0</value>
2453 </feature>
2454 <feature name="resetSkpTimerEIrx">
2455 <value>0</value>
2456 </feature>
2457 <feature name="sameSpeedPowerChg">
2458 <value>1</value>
2459 </feature>
2460 <feature name="multiLinkPerPort">
2461 <value>0</value>
2462 </feature>
2463 <feature name="noPipeP0s">
2464 <value>0</value>
2465 </feature>
2466 <feature name="noPipeP1">
2467 <value>0</value>
2468 </feature>
2469 <feature name="noPipeP2">
2470 <value>0</value>
2471 </feature>
2472 <feature name="pipeP2inL1">
2473 <value>0</value>
2474 </feature>
2475 <feature name="UImargin">
2476 <value>15</value>
2477 </feature>
2478 <feature name="ReEnterRecovery">
2479 <value>0</value>
2480 </feature>
2481 <feature name="assertDisScram">
2482 <value>1</value>
2483 </feature>
2484 <feature name="delayComplSymX1">
2485 <value>0</value>
2486 </feature>
2487 <feature name="suppLowSwing">
2488 <value>0</value>
2489 </feature>
2490 <feature name="deemphasis">
2491 <value>1</value>
2492 </feature>
2493 <feature name="PCIElc2SelDeem">
2494 <value>0</value>
2495 </feature>
2496 <feature name="PCIElc2SelDeemLB">
2497 <value>0</value>
2498 </feature>
2499 <feature name="PCIElc2SelDeemCompl">
2500 <value>0</value>
2501 </feature>
2502 <feature name="useDefaultTxL0sAdjustment">
2503 <value>1</value>
2504 </feature>
2505 <feature name="useDefaultRxL0sAdjustment">
2506 <value>1</value>
2507 </feature>
2508 <feature name="fcTimeout">
2509 <value>0</value>
2510 </feature>
2511 <feature name="fcTimeoutAnyDllp">
2512 <value>0</value>
2513 </feature>
2514 <feature name="TLpmeSize">
2515 <value>32</value>
2516 </feature>
2517 <feature name="TLCRSCnt">
2518 <value>1</value>
2519 </feature>
2520 <feature name="TLTxQDelay">
2521 <value>0</value>
2522 </feature>
2523 <feature name="oneErrPerRxTlp">
2524 <value>0</value>
2525 </feature>
2526 <feature name="accPoisonRX">
2527 <value>0</value>
2528 </feature>
2529 <feature name="accPoisonUR">
2530 <value>0</value>
2531 </feature>
2532 <feature name="noURPoison">
2533 <value>0</value>
2534 </feature>
2535 <feature name="retryNPReq">
2536 <value>0</value>
2537 </feature>
2538 <feature name="implRCMEM">
2539 <value>0</value>
2540 </feature>
2541 <feature name="implRCIO">
2542 <value>0</value>
2543 </feature>
2544 <feature name="pmL1Gap">
2545 <value>4</value>
2546 </feature>
2547 <feature name="pmL1aspmGap">
2548 <value>4</value>
2549 </feature>
2550 <feature name="pmL23Gap">
2551 <value>4</value>
2552 </feature>
2553 <feature name="pmAckGap">
2554 <value>4</value>
2555 </feature>
2556 <feature name="msgSlotPwr">
2557 <value>0</value>
2558 </feature>
2559 <feature name="txPLuse">
2560 <value>1</value>
2561 </feature>
2562 <feature name="txPLuseSelf">
2563 <value>1</value>
2564 </feature>
2565 <feature name="txPLuseMin">
2566 <value>0</value>
2567 </feature>
2568 <feature name="txPLuseMax">
2569 <value>0</value>
2570 </feature>
2571 <feature name="rxPLuse">
2572 <value>1</value>
2573 </feature>
2574 <feature name="rxPLuseSelf">
2575 <value>1</value>
2576 </feature>
2577 <feature name="rxPLuseMin">
2578 <value>0</value>
2579 </feature>
2580 <feature name="rxPLuseMax">
2581 <value>0</value>
2582 </feature>
2583 <feature name="sameSrcOrd">
2584 <value>0</value>
2585 </feature>
2586 <feature name="mfCRS">
2587 <value>1</value>
2588 </feature>
2589 <feature name="bcUnlockMsg">
2590 <value>1</value>
2591 </feature>
2592 <feature name="disBEchk">
2593 <value>0</value>
2594 </feature>
2595 <feature name="dis4Kchk">
2596 <value>0</value>
2597 </feature>
2598 <feature name="disIOchk">
2599 <value>0</value>
2600 </feature>
2601 <feature name="disCFGchk">
2602 <value>0</value>
2603 </feature>
2604 <feature name="disINTXchk">
2605 <value>0</value>
2606 </feature>
2607 <feature name="disRCBchk">
2608 <value>0</value>
2609 </feature>
2610 <feature name="enMFTlpFC">
2611 <value>0</value>
2612 </feature>
2613 <feature name="disINTXRXchk">
2614 <value>0</value>
2615 </feature>
2616 <feature name="disFCMaxchk">
2617 <value>0</value>
2618 </feature>
2619 <feature name="autoMsiMask">
2620 <value>0</value>
2621 </feature>
2622 <feature name="CplMatchAttr">
2623 <value>0</value>
2624 </feature>
2625 <feature name="CplMatchTc">
2626 <value>0</value>
2627 </feature>
2628 <feature name="CplEndMemReq">
2629 <value>1</value>
2630 </feature>
2631 <feature name="splitMemTrans">
2632 <value>0</value>
2633 </feature>
2634 <feature name="iovMaxNumVF">
2635 <value>0</value>
2636 </feature>
2637 <feature name="disP2P">
2638 <value>0</value>
2639 </feature>
2640 <feature name="ImInterruptLine">
2641 <value>1</value>
2642 </feature>
2643 <feature name="ImIOspace">
2644 <value>1</value>
2645 </feature>
2646 <feature name="ImMEMspace">
2647 <value>1</value>
2648 </feature>
2649 <feature name="ImMasEn">
2650 <value>1</value>
2651 </feature>
2652 <feature name="MasEn">
2653 <value>1</value>
2654 </feature>
2655 <feature name="ImDisINT">
2656 <value>1</value>
2657 </feature>
2658 <feature name="ImMwrInv">
2659 <value>1</value>
2660 </feature>
2661 <feature name="ROMen0">
2662 <value>1</value>
2663 </feature>
2664 <feature name="ROMen1">
2665 <value>1</value>
2666 </feature>
2667 <feature name="PMversion">
2668 <value>2</value>
2669 </feature>
2670 <feature name="PMEclk">
2671 <value>0</value>
2672 </feature>
2673 <feature name="PMEnoSoftRst">
2674 <value>0</value>
2675 </feature>
2676 <feature name="B2B3">
2677 <value>0</value>
2678 </feature>
2679 <feature name="BPCCen">
2680 <value>0</value>
2681 </feature>
2682 <feature name="PMEd3cold">
2683 <value>1</value>
2684 </feature>
2685 <feature name="PMEd3hot">
2686 <value>1</value>
2687 </feature>
2688 <feature name="PMEImEn">
2689 <value>1</value>
2690 </feature>
2691 <feature name="MSIPVMen">
2692 <value>0</value>
2693 </feature>
2694 <feature name="MSIX">
2695 <value>0</value>
2696 </feature>
2697 <feature name="MSIXaddr">
2698 <value>0</value>
2699 </feature>
2700 <feature name="capMSIXPtr">
2701 <value>0</value>
2702 </feature>
2703 <feature name="MSIXts">
2704 <value>1</value>
2705 </feature>
2706 <feature name="MSIXtblOS">
2707 <value>0</value>
2708 </feature>
2709 <feature name="MSIXtblBIR">
2710 <value>0</value>
2711 </feature>
2712 <feature name="MSIXpbaOS">
2713 <value>0</value>
2714 </feature>
2715 <feature name="MSIXpbaBIR">
2716 <value>0</value>
2717 </feature>
2718 <feature name="PCIXversion">
2719 <value>0</value>
2720 </feature>
2721 <feature name="PCIX64bit">
2722 <value>0</value>
2723 </feature>
2724 <feature name="PCIX133Cap">
2725 <value>0</value>
2726 </feature>
2727 <feature name="PCIX266Cap">
2728 <value>0</value>
2729 </feature>
2730 <feature name="PCIX533Cap">
2731 <value>0</value>
2732 </feature>
2733 <feature name="PCIXtype0">
2734 <value>1</value>
2735 </feature>
2736 <feature name="PCIXbridge">
2737 <value>0</value>
2738 </feature>
2739 <feature name="PCIXmaxRd">
2740 <value>512</value>
2741 </feature>
2742 <feature name="PCIXmaxSplit">
2743 <value>1</value>
2744 </feature>
2745 <feature name="PCIXmaxCuRd">
2746 <value>1</value>
2747 </feature>
2748 <feature name="PCIXtype1">
2749 <value>0</value>
2750 </feature>
2751 <feature name="PCIXbrFreq">
2752 <value>0</value>
2753 </feature>
2754 <feature name="PCIXbrParity">
2755 <value>0</value>
2756 </feature>
2757 <feature name="PCIXbr">
2758 <value>1</value>
2759 </feature>
2760 <feature name="PCIXbrFN">
2761 <value>0</value>
2762 </feature>
2763 <feature name="PCIXbrDN">
2764 <value>0</value>
2765 </feature>
2766 <feature name="PCIXbrBN">
2767 <value>0</value>
2768 </feature>
2769 <feature name="PCIXbrIdMsg">
2770 <value>0</value>
2771 </feature>
2772 <feature name="PCIXbrSplitCapUp">
2773 <value>0</value>
2774 </feature>
2775 <feature name="PCIXbrSplitCapDn">
2776 <value>0</value>
2777 </feature>
2778 <feature name="PCIErev">
2779 <value>1</value>
2780 </feature>
2781 <feature name="PCIEmsiIntxNum">
2782 <value>0</value>
2783 </feature>
2784 <feature name="PCIEmsixIntxNum">
2785 <value>0</value>
2786 </feature>
2787 <feature name="PCIEtcs">
2788 <value>0</value>
2789 </feature>
2790 <feature name="PCIEdevRole">
2791 <value>0</value>
2792 </feature>
2793 <feature name="PCIEdevFLR">
2794 <value>0</value>
2795 </feature>
2796 <feature name="PCIEdcImRelOrder">
2797 <value>1</value>
2798 </feature>
2799 <feature name="PCIEdcImEtag">
2800 <value>1</value>
2801 </feature>
2802 <feature name="PCIEdcImPF">
2803 <value>1</value>
2804 </feature>
2805 <feature name="PCIEdcImAux">
2806 <value>1</value>
2807 </feature>
2808 <feature name="PCIEdcImNoSnoop">
2809 <value>1</value>
2810 </feature>
2811 <feature name="PCIEdcImMaxPL">
2812 <value>1</value>
2813 </feature>
2814 <feature name="PCIEdcImMaxRead">
2815 <value>1</value>
2816 </feature>
2817 <feature name="PCIEdev2">
2818 <value>0</value>
2819 </feature>
2820 <feature name="PCIEdev2Range">
2821 <value>0</value>
2822 </feature>
2823 <feature name="PCIEdev2RangeA">
2824 <value>0</value>
2825 </feature>
2826 <feature name="PCIEdev2RangeB">
2827 <value>0</value>
2828 </feature>
2829 <feature name="PCIEdev2RangeAB">
2830 <value>0</value>
2831 </feature>
2832 <feature name="PCIEdev2RangeBC">
2833 <value>0</value>
2834 </feature>
2835 <feature name="PCIEdev2RangeABC">
2836 <value>0</value>
2837 </feature>
2838 <feature name="PCIEdev2RangeBCD">
2839 <value>0</value>
2840 </feature>
2841 <feature name="PCIEdev2RangeABCD">
2842 <value>0</value>
2843 </feature>
2844 <feature name="cplRngReq">
2845 <value>0</value>
2846 </feature>
2847 <feature name="cplRngReqNow">
2848 <value>0</value>
2849 </feature>
2850 <feature name="PCIEdev2CplDis">
2851 <value>1</value>
2852 </feature>
2853 <feature name="cplDisReq">
2854 <value>0</value>
2855 </feature>
2856 <feature name="cplDisReqNow">
2857 <value>0</value>
2858 </feature>
2859 <feature name="PCIEariSupp">
2860 <value>0</value>
2861 </feature>
2862 <feature name="PCIEiovSRemuEROM">
2863 <value>0</value>
2864 </feature>
2865 <feature name="PCIEds">
2866 <value>0</value>
2867 </feature>
2868 <feature name="PCIEdsOwnNP">
2869 <value>1</value>
2870 </feature>
2871 <feature name="PCIElkSpd2">
2872 <value>1</value>
2873 </feature>
2874 <feature name="PCIElkBandWidth">
2875 <value>1</value>
2876 </feature>
2877 <feature name="PCIElkL07">
2878 <value>0</value>
2879 </feature>
2880 <feature name="PCIElkClkPowMgmt">
2881 <value>0</value>
2882 </feature>
2883 <feature name="PCIElkDnErrRepCap">
2884 <value>0</value>
2885 </feature>
2886 <feature name="PCIElkDlActRepCap">
2887 <value>0</value>
2888 </feature>
2889 <feature name="PCIElcL0s">
2890 <value>1</value>
2891 </feature>
2892 <feature name="PCIElcClkPowMgmt">
2893 <value>0</value>
2894 </feature>
2895 <feature name="PCIElc2">
2896 <value>1</value>
2897 </feature>
2898 <feature name="PCIElc2TgtSpdImpl">
2899 <value>1</value>
2900 </feature>
2901 <feature name="PCIElc2TgtSpd">
2902 <value>0</value>
2903 </feature>
2904 <feature name="PCIElc2EnCompImpl">
2905 <value>1</value>
2906 </feature>
2907 <feature name="PCIElc2HwAutoSpdDisImpl">
2908 <value>1</value>
2909 </feature>
2910 <feature name="PCIElc2SelDeImpl">
2911 <value>1</value>
2912 </feature>
2913 <feature name="PCIElc2TxMarginImpl">
2914 <value>1</value>
2915 </feature>
2916 <feature name="PCIElc2EnModCompImpl">
2917 <value>1</value>
2918 </feature>
2919 <feature name="PCIElc2CompSOSImpl">
2920 <value>1</value>
2921 </feature>
2922 <feature name="PCIElc2CompDeImpl">
2923 <value>1</value>
2924 </feature>
2925 <feature name="PCIEls2">
2926 <value>1</value>
2927 </feature>
2928 <feature name="PCIEls2CurrDeImpl">
2929 <value>1</value>
2930 </feature>
2931 <feature name="PCIEslPowFaultDet">
2932 <value>1</value>
2933 </feature>
2934 <feature name="PCIEslLock">
2935 <value>0</value>
2936 </feature>
2937 <feature name="PCIEslCmdCplSupp">
2938 <value>0</value>
2939 </feature>
2940 <feature name="PCIEscAIC">
2941 <value>0</value>
2942 </feature>
2943 <feature name="PCIEscAICdef">
2944 <value>3</value>
2945 </feature>
2946 <feature name="PCIEscPIC">
2947 <value>0</value>
2948 </feature>
2949 <feature name="PCIEscPICdef">
2950 <value>3</value>
2951 </feature>
2952 <feature name="PCIEscDLE">
2953 <value>0</value>
2954 </feature>
2955 <feature name="PCIEss">
2956 <value>0</value>
2957 </feature>
2958 <feature name="PCIErcCRS">
2959 <value>0</value>
2960 </feature>
2961 <feature name="PCIErcap">
2962 <value>0</value>
2963 </feature>
2964 <feature name="PCIErcapCRS">
2965 <value>0</value>
2966 </feature>
2967 <feature name="PCIEXaeImpTr">
2968 <value>1</value>
2969 </feature>
2970 <feature name="PCIEXaeImpFC">
2971 <value>1</value>
2972 </feature>
2973 <feature name="PCIEXaeImpCA">
2974 <value>1</value>
2975 </feature>
2976 <feature name="PCIEXaeImpRcvrOvf">
2977 <value>1</value>
2978 </feature>
2979 <feature name="PCIEXaeImpEcrc">
2980 <value>1</value>
2981 </feature>
2982 <feature name="PCIEXaeImpRcvr">
2983 <value>1</value>
2984 </feature>
2985 <feature name="PCIEXaeImpSurpDown">
2986 <value>0</value>
2987 </feature>
2988 <feature name="PCIEXaeUMSurpDown">
2989 <value>0</value>
2990 </feature>
2991 <feature name="PCIEXaeUVSurpDown">
2992 <value>1</value>
2993 </feature>
2994 <feature name="PCIEXaeCMrepANF">
2995 <value>1</value>
2996 </feature>
2997 <feature name="PCIEXmfvc">
2998 <value>0</value>
2999 </feature>
3000 <feature name="PCIEXMFVCaddr">
3001 <value>0</value>
3002 </feature>
3003 <feature name="capMFVCPtr">
3004 <value>0</value>
3005 </feature>
3006 <feature name="PCIEXmfvc1">
3007 <value>0</value>
3008 </feature>
3009 <feature name="PCIEXmfvc1Evc">
3010 <value>0</value>
3011 </feature>
3012 <feature name="PCIEXmfvc1LEvc">
3013 <value>0</value>
3014 </feature>
3015 <feature name="PCIEXmfvc1Arb">
3016 <value>0</value>
3017 </feature>
3018 <feature name="PCIEXmfvc2">
3019 <value>0</value>
3020 </feature>
3021 <feature name="PCIEXmfvc2arb1">
3022 <value>0</value>
3023 </feature>
3024 <feature name="PCIEXmfvc2arb2">
3025 <value>0</value>
3026 </feature>
3027 <feature name="PCIEXmfvc2arb4">
3028 <value>0</value>
3029 </feature>
3030 <feature name="PCIEXmfvc2arb8">
3031 <value>0</value>
3032 </feature>
3033 <feature name="PCIEXmfvcARsel">
3034 <value>0</value>
3035 </feature>
3036 <feature name="PCIEXmfvcARloc">
3037 <value>0</value>
3038 </feature>
3039 <feature name="PCIEXmfvcARtab">
3040 <value>0</value>
3041 </feature>
3042 <feature name="PCIEXmfvcR0">
3043 <value>1</value>
3044 </feature>
3045 <feature name="PCIEXmfvcR0FC">
3046 <value>1</value>
3047 </feature>
3048 <feature name="PCIEXmfvcR0FCPHun">
3049 <value>0</value>
3050 </feature>
3051 <feature name="PCIEXmfvcR0FCPH">
3052 <value>0</value>
3053 </feature>
3054 <feature name="PCIEXmfvcR0FCPDun">
3055 <value>0</value>
3056 </feature>
3057 <feature name="PCIEXmfvcR0FCPD">
3058 <value>0</value>
3059 </feature>
3060 <feature name="PCIEXmfvcR0FCNPHun">
3061 <value>0</value>
3062 </feature>
3063 <feature name="PCIEXmfvcR0FCNPH">
3064 <value>0</value>
3065 </feature>
3066 <feature name="PCIEXmfvcR0FCNPDun">
3067 <value>0</value>
3068 </feature>
3069 <feature name="PCIEXmfvcR0FCNPD">
3070 <value>0</value>
3071 </feature>
3072 <feature name="PCIEXmfvcR0FCCPLHun">
3073 <value>0</value>
3074 </feature>
3075 <feature name="PCIEXmfvcR0FCCPLH">
3076 <value>0</value>
3077 </feature>
3078 <feature name="PCIEXmfvcR0FCCPLDun">
3079 <value>0</value>
3080 </feature>
3081 <feature name="PCIEXmfvcR0FCCPLD">
3082 <value>0</value>
3083 </feature>
3084 <feature name="PCIEXmfvcR0Ca">
3085 <value>0</value>
3086 </feature>
3087 <feature name="PCIEXmfvcR0Arb">
3088 <value>0</value>
3089 </feature>
3090 <feature name="PCIEXmfvcR0Arb0">
3091 <value>1</value>
3092 </feature>
3093 <feature name="PCIEXmfvcR0Arb1">
3094 <value>0</value>
3095 </feature>
3096 <feature name="PCIEXmfvcR0Arb2">
3097 <value>0</value>
3098 </feature>
3099 <feature name="PCIEXmfvcR0Arb3">
3100 <value>0</value>
3101 </feature>
3102 <feature name="PCIEXmfvcR0Arb4">
3103 <value>0</value>
3104 </feature>
3105 <feature name="PCIEXmfvcR0Arb5">
3106 <value>0</value>
3107 </feature>
3108 <feature name="PCIEXmfvcR0time">
3109 <value>0</value>
3110 </feature>
3111 <feature name="PCIEXmfvcR0offset">
3112 <value>0</value>
3113 </feature>
3114 <feature name="PCIEXmfvcR0CT">
3115 <value>0</value>
3116 </feature>
3117 <feature name="PCIEXmfvcR0map">
3118 <value>0</value>
3119 </feature>
3120 <feature name="PCIEXmfvcR0sel">
3121 <value>0</value>
3122 </feature>
3123 <feature name="PCIEXmfvcR0tab">
3124 <value>0</value>
3125 </feature>
3126 <feature name="PCIEXmfvcR1">
3127 <value>1</value>
3128 </feature>
3129 <feature name="PCIEXmfvcR1FC">
3130 <value>1</value>
3131 </feature>
3132 <feature name="PCIEXmfvcR1FCPHun">
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3134 </feature>
3135 <feature name="PCIEXmfvcR1FCPH">
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3137 </feature>
3138 <feature name="PCIEXmfvcR1FCPDun">
3139 <value>0</value>
3140 </feature>
3141 <feature name="PCIEXmfvcR1FCPD">
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3143 </feature>
3144 <feature name="PCIEXmfvcR1FCNPHun">
3145 <value>0</value>
3146 </feature>
3147 <feature name="PCIEXmfvcR1FCNPH">
3148 <value>0</value>
3149 </feature>
3150 <feature name="PCIEXmfvcR1FCNPDun">
3151 <value>0</value>
3152 </feature>
3153 <feature name="PCIEXmfvcR1FCNPD">
3154 <value>0</value>
3155 </feature>
3156 <feature name="PCIEXmfvcR1FCCPLHun">
3157 <value>0</value>
3158 </feature>
3159 <feature name="PCIEXmfvcR1FCCPLH">
3160 <value>0</value>
3161 </feature>
3162 <feature name="PCIEXmfvcR1FCCPLDun">
3163 <value>0</value>
3164 </feature>
3165 <feature name="PCIEXmfvcR1FCCPLD">
3166 <value>0</value>
3167 </feature>
3168 <feature name="PCIEXmfvcR1Ca">
3169 <value>0</value>
3170 </feature>
3171 <feature name="PCIEXmfvcR1Arb">
3172 <value>0</value>
3173 </feature>
3174 <feature name="PCIEXmfvcR1Arb0">
3175 <value>1</value>
3176 </feature>
3177 <feature name="PCIEXmfvcR1Arb1">
3178 <value>0</value>
3179 </feature>
3180 <feature name="PCIEXmfvcR1Arb2">
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3182 </feature>
3183 <feature name="PCIEXmfvcR1Arb3">
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3185 </feature>
3186 <feature name="PCIEXmfvcR1Arb4">
3187 <value>0</value>
3188 </feature>
3189 <feature name="PCIEXmfvcR1Arb5">
3190 <value>0</value>
3191 </feature>
3192 <feature name="PCIEXmfvcR1time">
3193 <value>0</value>
3194 </feature>
3195 <feature name="PCIEXmfvcR1offset">
3196 <value>0</value>
3197 </feature>
3198 <feature name="PCIEXmfvcR1CT">
3199 <value>0</value>
3200 </feature>
3201 <feature name="PCIEXmfvcR1map">
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3203 </feature>
3204 <feature name="PCIEXmfvcR1sel">
3205 <value>0</value>
3206 </feature>
3207 <feature name="PCIEXmfvcR1vcID">
3208 <value>1</value>
3209 </feature>
3210 <feature name="PCIEXmfvcR1tab">
3211 <value>0</value>
3212 </feature>
3213 <feature name="PCIEXmfvcR2">
3214 <value>1</value>
3215 </feature>
3216 <feature name="PCIEXmfvcR2FC">
3217 <value>1</value>
3218 </feature>
3219 <feature name="PCIEXmfvcR2FCPHun">
3220 <value>0</value>
3221 </feature>
3222 <feature name="PCIEXmfvcR2FCPH">
3223 <value>0</value>
3224 </feature>
3225 <feature name="PCIEXmfvcR2FCPDun">
3226 <value>0</value>
3227 </feature>
3228 <feature name="PCIEXmfvcR2FCPD">
3229 <value>0</value>
3230 </feature>
3231 <feature name="PCIEXmfvcR2FCNPHun">
3232 <value>0</value>
3233 </feature>
3234 <feature name="PCIEXmfvcR2FCNPH">
3235 <value>0</value>
3236 </feature>
3237 <feature name="PCIEXmfvcR2FCNPDun">
3238 <value>0</value>
3239 </feature>
3240 <feature name="PCIEXmfvcR2FCNPD">
3241 <value>0</value>
3242 </feature>
3243 <feature name="PCIEXmfvcR2FCCPLHun">
3244 <value>0</value>
3245 </feature>
3246 <feature name="PCIEXmfvcR2FCCPLH">
3247 <value>0</value>
3248 </feature>
3249 <feature name="PCIEXmfvcR2FCCPLDun">
3250 <value>0</value>
3251 </feature>
3252 <feature name="PCIEXmfvcR2FCCPLD">
3253 <value>0</value>
3254 </feature>
3255 <feature name="PCIEXmfvcR2Ca">
3256 <value>0</value>
3257 </feature>
3258 <feature name="PCIEXmfvcR2Arb">
3259 <value>0</value>
3260 </feature>
3261 <feature name="PCIEXmfvcR2Arb0">
3262 <value>1</value>
3263 </feature>
3264 <feature name="PCIEXmfvcR2Arb1">
3265 <value>0</value>
3266 </feature>
3267 <feature name="PCIEXmfvcR2Arb2">
3268 <value>0</value>
3269 </feature>
3270 <feature name="PCIEXmfvcR2Arb3">
3271 <value>0</value>
3272 </feature>
3273 <feature name="PCIEXmfvcR2Arb4">
3274 <value>0</value>
3275 </feature>
3276 <feature name="PCIEXmfvcR2Arb5">
3277 <value>0</value>
3278 </feature>
3279 <feature name="PCIEXmfvcR2time">
3280 <value>0</value>
3281 </feature>
3282 <feature name="PCIEXmfvcR2offset">
3283 <value>0</value>
3284 </feature>
3285 <feature name="PCIEXmfvcR2CT">
3286 <value>0</value>
3287 </feature>
3288 <feature name="PCIEXmfvcR2map">
3289 <value>0</value>
3290 </feature>
3291 <feature name="PCIEXmfvcR2sel">
3292 <value>0</value>
3293 </feature>
3294 <feature name="PCIEXmfvcR2vcID">
3295 <value>1</value>
3296 </feature>
3297 <feature name="PCIEXmfvcR2tab">
3298 <value>0</value>
3299 </feature>
3300 <feature name="PCIEXmfvcR3">
3301 <value>1</value>
3302 </feature>
3303 <feature name="PCIEXmfvcR3FC">
3304 <value>1</value>
3305 </feature>
3306 <feature name="PCIEXmfvcR3FCPHun">
3307 <value>0</value>
3308 </feature>
3309 <feature name="PCIEXmfvcR3FCPH">
3310 <value>0</value>
3311 </feature>
3312 <feature name="PCIEXmfvcR3FCPDun">
3313 <value>0</value>
3314 </feature>
3315 <feature name="PCIEXmfvcR3FCPD">
3316 <value>0</value>
3317 </feature>
3318 <feature name="PCIEXmfvcR3FCNPHun">
3319 <value>0</value>
3320 </feature>
3321 <feature name="PCIEXmfvcR3FCNPH">
3322 <value>0</value>
3323 </feature>
3324 <feature name="PCIEXmfvcR3FCNPDun">
3325 <value>0</value>
3326 </feature>
3327 <feature name="PCIEXmfvcR3FCNPD">
3328 <value>0</value>
3329 </feature>
3330 <feature name="PCIEXmfvcR3FCCPLHun">
3331 <value>0</value>
3332 </feature>
3333 <feature name="PCIEXmfvcR3FCCPLH">
3334 <value>0</value>
3335 </feature>
3336 <feature name="PCIEXmfvcR3FCCPLDun">
3337 <value>0</value>
3338 </feature>
3339 <feature name="PCIEXmfvcR3FCCPLD">
3340 <value>0</value>
3341 </feature>
3342 <feature name="PCIEXmfvcR3Ca">
3343 <value>0</value>
3344 </feature>
3345 <feature name="PCIEXmfvcR3Arb">
3346 <value>0</value>
3347 </feature>
3348 <feature name="PCIEXmfvcR3Arb0">
3349 <value>1</value>
3350 </feature>
3351 <feature name="PCIEXmfvcR3Arb1">
3352 <value>0</value>
3353 </feature>
3354 <feature name="PCIEXmfvcR3Arb2">
3355 <value>0</value>
3356 </feature>
3357 <feature name="PCIEXmfvcR3Arb3">
3358 <value>0</value>
3359 </feature>
3360 <feature name="PCIEXmfvcR3Arb4">
3361 <value>0</value>
3362 </feature>
3363 <feature name="PCIEXmfvcR3Arb5">
3364 <value>0</value>
3365 </feature>
3366 <feature name="PCIEXmfvcR3time">
3367 <value>0</value>
3368 </feature>
3369 <feature name="PCIEXmfvcR3offset">
3370 <value>0</value>
3371 </feature>
3372 <feature name="PCIEXmfvcR3CT">
3373 <value>0</value>
3374 </feature>
3375 <feature name="PCIEXmfvcR3map">
3376 <value>0</value>
3377 </feature>
3378 <feature name="PCIEXmfvcR3sel">
3379 <value>0</value>
3380 </feature>
3381 <feature name="PCIEXmfvcR3vcID">
3382 <value>1</value>
3383 </feature>
3384 <feature name="PCIEXmfvcR3tab">
3385 <value>0</value>
3386 </feature>
3387 <feature name="PCIEXmfvcR4">
3388 <value>1</value>
3389 </feature>
3390 <feature name="PCIEXmfvcR4FC">
3391 <value>1</value>
3392 </feature>
3393 <feature name="PCIEXmfvcR4FCPHun">
3394 <value>0</value>
3395 </feature>
3396 <feature name="PCIEXmfvcR4FCPH">
3397 <value>0</value>
3398 </feature>
3399 <feature name="PCIEXmfvcR4FCPDun">
3400 <value>0</value>
3401 </feature>
3402 <feature name="PCIEXmfvcR4FCPD">
3403 <value>0</value>
3404 </feature>
3405 <feature name="PCIEXmfvcR4FCNPHun">
3406 <value>0</value>
3407 </feature>
3408 <feature name="PCIEXmfvcR4FCNPH">
3409 <value>0</value>
3410 </feature>
3411 <feature name="PCIEXmfvcR4FCNPDun">
3412 <value>0</value>
3413 </feature>
3414 <feature name="PCIEXmfvcR4FCNPD">
3415 <value>0</value>
3416 </feature>
3417 <feature name="PCIEXmfvcR4FCCPLHun">
3418 <value>0</value>
3419 </feature>
3420 <feature name="PCIEXmfvcR4FCCPLH">
3421 <value>0</value>
3422 </feature>
3423 <feature name="PCIEXmfvcR4FCCPLDun">
3424 <value>0</value>
3425 </feature>
3426 <feature name="PCIEXmfvcR4FCCPLD">
3427 <value>0</value>
3428 </feature>
3429 <feature name="PCIEXmfvcR4Ca">
3430 <value>0</value>
3431 </feature>
3432 <feature name="PCIEXmfvcR4Arb">
3433 <value>0</value>
3434 </feature>
3435 <feature name="PCIEXmfvcR4Arb0">
3436 <value>1</value>
3437 </feature>
3438 <feature name="PCIEXmfvcR4Arb1">
3439 <value>0</value>
3440 </feature>
3441 <feature name="PCIEXmfvcR4Arb2">
3442 <value>0</value>
3443 </feature>
3444 <feature name="PCIEXmfvcR4Arb3">
3445 <value>0</value>
3446 </feature>
3447 <feature name="PCIEXmfvcR4Arb4">
3448 <value>0</value>
3449 </feature>
3450 <feature name="PCIEXmfvcR4Arb5">
3451 <value>0</value>
3452 </feature>
3453 <feature name="PCIEXmfvcR4time">
3454 <value>0</value>
3455 </feature>
3456 <feature name="PCIEXmfvcR4offset">
3457 <value>0</value>
3458 </feature>
3459 <feature name="PCIEXmfvcR4CT">
3460 <value>0</value>
3461 </feature>
3462 <feature name="PCIEXmfvcR4map">
3463 <value>0</value>
3464 </feature>
3465 <feature name="PCIEXmfvcR4sel">
3466 <value>0</value>
3467 </feature>
3468 <feature name="PCIEXmfvcR4vcID">
3469 <value>1</value>
3470 </feature>
3471 <feature name="PCIEXmfvcR4tab">
3472 <value>0</value>
3473 </feature>
3474 <feature name="PCIEXmfvcR5">
3475 <value>1</value>
3476 </feature>
3477 <feature name="PCIEXmfvcR5FC">
3478 <value>1</value>
3479 </feature>
3480 <feature name="PCIEXmfvcR5FCPHun">
3481 <value>0</value>
3482 </feature>
3483 <feature name="PCIEXmfvcR5FCPH">
3484 <value>0</value>
3485 </feature>
3486 <feature name="PCIEXmfvcR5FCPDun">
3487 <value>0</value>
3488 </feature>
3489 <feature name="PCIEXmfvcR5FCPD">
3490 <value>0</value>
3491 </feature>
3492 <feature name="PCIEXmfvcR5FCNPHun">
3493 <value>0</value>
3494 </feature>
3495 <feature name="PCIEXmfvcR5FCNPH">
3496 <value>0</value>
3497 </feature>
3498 <feature name="PCIEXmfvcR5FCNPDun">
3499 <value>0</value>
3500 </feature>
3501 <feature name="PCIEXmfvcR5FCNPD">
3502 <value>0</value>
3503 </feature>
3504 <feature name="PCIEXmfvcR5FCCPLHun">
3505 <value>0</value>
3506 </feature>
3507 <feature name="PCIEXmfvcR5FCCPLH">
3508 <value>0</value>
3509 </feature>
3510 <feature name="PCIEXmfvcR5FCCPLDun">
3511 <value>0</value>
3512 </feature>
3513 <feature name="PCIEXmfvcR5FCCPLD">
3514 <value>0</value>
3515 </feature>
3516 <feature name="PCIEXmfvcR5Ca">
3517 <value>0</value>
3518 </feature>
3519 <feature name="PCIEXmfvcR5Arb">
3520 <value>0</value>
3521 </feature>
3522 <feature name="PCIEXmfvcR5Arb0">
3523 <value>1</value>
3524 </feature>
3525 <feature name="PCIEXmfvcR5Arb1">
3526 <value>0</value>
3527 </feature>
3528 <feature name="PCIEXmfvcR5Arb2">
3529 <value>0</value>
3530 </feature>
3531 <feature name="PCIEXmfvcR5Arb3">
3532 <value>0</value>
3533 </feature>
3534 <feature name="PCIEXmfvcR5Arb4">
3535 <value>0</value>
3536 </feature>
3537 <feature name="PCIEXmfvcR5Arb5">
3538 <value>0</value>
3539 </feature>
3540 <feature name="PCIEXmfvcR5time">
3541 <value>0</value>
3542 </feature>
3543 <feature name="PCIEXmfvcR5offset">
3544 <value>0</value>
3545 </feature>
3546 <feature name="PCIEXmfvcR5CT">
3547 <value>0</value>
3548 </feature>
3549 <feature name="PCIEXmfvcR5map">
3550 <value>0</value>
3551 </feature>
3552 <feature name="PCIEXmfvcR5sel">
3553 <value>0</value>
3554 </feature>
3555 <feature name="PCIEXmfvcR5vcID">
3556 <value>1</value>
3557 </feature>
3558 <feature name="PCIEXmfvcR5tab">
3559 <value>0</value>
3560 </feature>
3561 <feature name="PCIEXmfvcR6">
3562 <value>1</value>
3563 </feature>
3564 <feature name="PCIEXmfvcR6FC">
3565 <value>1</value>
3566 </feature>
3567 <feature name="PCIEXmfvcR6FCPHun">
3568 <value>0</value>
3569 </feature>
3570 <feature name="PCIEXmfvcR6FCPH">
3571 <value>0</value>
3572 </feature>
3573 <feature name="PCIEXmfvcR6FCPDun">
3574 <value>0</value>
3575 </feature>
3576 <feature name="PCIEXmfvcR6FCPD">
3577 <value>0</value>
3578 </feature>
3579 <feature name="PCIEXmfvcR6FCNPHun">
3580 <value>0</value>
3581 </feature>
3582 <feature name="PCIEXmfvcR6FCNPH">
3583 <value>0</value>
3584 </feature>
3585 <feature name="PCIEXmfvcR6FCNPDun">
3586 <value>0</value>
3587 </feature>
3588 <feature name="PCIEXmfvcR6FCNPD">
3589 <value>0</value>
3590 </feature>
3591 <feature name="PCIEXmfvcR6FCCPLHun">
3592 <value>0</value>
3593 </feature>
3594 <feature name="PCIEXmfvcR6FCCPLH">
3595 <value>0</value>
3596 </feature>
3597 <feature name="PCIEXmfvcR6FCCPLDun">
3598 <value>0</value>
3599 </feature>
3600 <feature name="PCIEXmfvcR6FCCPLD">
3601 <value>0</value>
3602 </feature>
3603 <feature name="PCIEXmfvcR6Ca">
3604 <value>0</value>
3605 </feature>
3606 <feature name="PCIEXmfvcR6Arb">
3607 <value>0</value>
3608 </feature>
3609 <feature name="PCIEXmfvcR6Arb0">
3610 <value>1</value>
3611 </feature>
3612 <feature name="PCIEXmfvcR6Arb1">
3613 <value>0</value>
3614 </feature>
3615 <feature name="PCIEXmfvcR6Arb2">
3616 <value>0</value>
3617 </feature>
3618 <feature name="PCIEXmfvcR6Arb3">
3619 <value>0</value>
3620 </feature>
3621 <feature name="PCIEXmfvcR6Arb4">
3622 <value>0</value>
3623 </feature>
3624 <feature name="PCIEXmfvcR6Arb5">
3625 <value>0</value>
3626 </feature>
3627 <feature name="PCIEXmfvcR6time">
3628 <value>0</value>
3629 </feature>
3630 <feature name="PCIEXmfvcR6offset">
3631 <value>0</value>
3632 </feature>
3633 <feature name="PCIEXmfvcR6CT">
3634 <value>0</value>
3635 </feature>
3636 <feature name="PCIEXmfvcR6map">
3637 <value>0</value>
3638 </feature>
3639 <feature name="PCIEXmfvcR6sel">
3640 <value>0</value>
3641 </feature>
3642 <feature name="PCIEXmfvcR6vcID">
3643 <value>1</value>
3644 </feature>
3645 <feature name="PCIEXmfvcR6tab">
3646 <value>0</value>
3647 </feature>
3648 <feature name="PCIEXmfvcR7">
3649 <value>0</value>
3650 </feature>
3651 <feature name="PCIEXmfvcR7FC">
3652 <value>1</value>
3653 </feature>
3654 <feature name="PCIEXmfvcR7FCPHun">
3655 <value>0</value>
3656 </feature>
3657 <feature name="PCIEXmfvcR7FCPH">
3658 <value>0</value>
3659 </feature>
3660 <feature name="PCIEXmfvcR7FCPDun">
3661 <value>0</value>
3662 </feature>
3663 <feature name="PCIEXmfvcR7FCPD">
3664 <value>0</value>
3665 </feature>
3666 <feature name="PCIEXmfvcR7FCNPHun">
3667 <value>0</value>
3668 </feature>
3669 <feature name="PCIEXmfvcR7FCNPH">
3670 <value>0</value>
3671 </feature>
3672 <feature name="PCIEXmfvcR7FCNPDun">
3673 <value>0</value>
3674 </feature>
3675 <feature name="PCIEXmfvcR7FCNPD">
3676 <value>0</value>
3677 </feature>
3678 <feature name="PCIEXmfvcR7FCCPLHun">
3679 <value>0</value>
3680 </feature>
3681 <feature name="PCIEXmfvcR7FCCPLH">
3682 <value>0</value>
3683 </feature>
3684 <feature name="PCIEXmfvcR7FCCPLDun">
3685 <value>0</value>
3686 </feature>
3687 <feature name="PCIEXmfvcR7FCCPLD">
3688 <value>0</value>
3689 </feature>
3690 <feature name="PCIEXmfvcR7Ca">
3691 <value>0</value>
3692 </feature>
3693 <feature name="PCIEXmfvcR7Arb">
3694 <value>0</value>
3695 </feature>
3696 <feature name="PCIEXmfvcR7Arb0">
3697 <value>1</value>
3698 </feature>
3699 <feature name="PCIEXmfvcR7Arb1">
3700 <value>0</value>
3701 </feature>
3702 <feature name="PCIEXmfvcR7Arb2">
3703 <value>0</value>
3704 </feature>
3705 <feature name="PCIEXmfvcR7Arb3">
3706 <value>0</value>
3707 </feature>
3708 <feature name="PCIEXmfvcR7Arb4">
3709 <value>0</value>
3710 </feature>
3711 <feature name="PCIEXmfvcR7Arb5">
3712 <value>0</value>
3713 </feature>
3714 <feature name="PCIEXmfvcR7time">
3715 <value>0</value>
3716 </feature>
3717 <feature name="PCIEXmfvcR7offset">
3718 <value>0</value>
3719 </feature>
3720 <feature name="PCIEXmfvcR7CT">
3721 <value>0</value>
3722 </feature>
3723 <feature name="PCIEXmfvcR7map">
3724 <value>0</value>
3725 </feature>
3726 <feature name="PCIEXmfvcR7sel">
3727 <value>0</value>
3728 </feature>
3729 <feature name="PCIEXmfvcR7vcID">
3730 <value>1</value>
3731 </feature>
3732 <feature name="PCIEXmfvcR7tab">
3733 <value>0</value>
3734 </feature>
3735 <feature name="PCIEXrclk">
3736 <value>0</value>
3737 </feature>
3738 <feature name="PCIEXRCLKaddr">
3739 <value>0</value>
3740 </feature>
3741 <feature name="capRCLKPtr">
3742 <value>0</value>
3743 </feature>
3744 <feature name="PCIEXrclkType">
3745 <value>1</value>
3746 </feature>
3747 <feature name="PCIEXrclkTypeCfg">
3748 <value>1</value>
3749 </feature>
3750 <feature name="PCIEXrclkTypeMem">
3751 <value>0</value>
3752 </feature>
3753 <feature name="PCIEXrclkTypeLK">
3754 <value>0</value>
3755 </feature>
3756 <feature name="PCIEXrclkNumLK">
3757 <value>1</value>
3758 </feature>
3759 <feature name="PCIEXrclkCompID">
3760 <value>1</value>
3761 </feature>
3762 <feature name="PCIEXrclkPortNum">
3763 <value>0</value>
3764 </feature>
3765 <feature name="PCIEXrclkLK0">
3766 <value>1</value>
3767 </feature>
3768 <feature name="PCIEXrclkLK0Valid">
3769 <value>1</value>
3770 </feature>
3771 <feature name="PCIEXrclkLK0Type">
3772 <value>1</value>
3773 </feature>
3774 <feature name="PCIEXrclkLK0RCRB">
3775 <value>0</value>
3776 </feature>
3777 <feature name="PCIEXrclkLK0CompID">
3778 <value>1</value>
3779 </feature>
3780 <feature name="PCIEXrclkLK0PortNum">
3781 <value>0</value>
3782 </feature>
3783 <feature name="PCIEXrclkLK0AddrLow">
3784 <value>0</value>
3785 </feature>
3786 <feature name="PCIEXrclkLK0AddrHigh">
3787 <value>0</value>
3788 </feature>
3789 <feature name="PCIEXrclkLKOther">
3790 <value>0</value>
3791 </feature>
3792 <feature name="PCIEXrclc">
3793 <value>0</value>
3794 </feature>
3795 <feature name="PCIEXRCLCaddr">
3796 <value>0</value>
3797 </feature>
3798 <feature name="capRCLCPtr">
3799 <value>0</value>
3800 </feature>
3801 <feature name="PCIEXrclcWidth">
3802 <value>1</value>
3803 </feature>
3804 <feature name="PCIEXrclcAspm">
3805 <value>1</value>
3806 </feature>
3807 <feature name="PCIEXrclcL0s">
3808 <value>1</value>
3809 </feature>
3810 <feature name="PCIEXrclcL1">
3811 <value>1</value>
3812 </feature>
3813 <feature name="PCIEXrclcL0sExit">
3814 <value>1</value>
3815 </feature>
3816 <feature name="PCIEXrclcL0sExit0">
3817 <value>1</value>
3818 </feature>
3819 <feature name="PCIEXrclcL0sExit1">
3820 <value>0</value>
3821 </feature>
3822 <feature name="PCIEXrclcL0sExit2">
3823 <value>0</value>
3824 </feature>
3825 <feature name="PCIEXrclcL0sExit3">
3826 <value>0</value>
3827 </feature>
3828 <feature name="PCIEXrclcL0sExit4">
3829 <value>0</value>
3830 </feature>
3831 <feature name="PCIEXrclcL0sExit5">
3832 <value>0</value>
3833 </feature>
3834 <feature name="PCIEXrclcL0sExit6">
3835 <value>0</value>
3836 </feature>
3837 <feature name="PCIEXrclcL0sExit7">
3838 <value>0</value>
3839 </feature>
3840 <feature name="PCIEXrclcL1Exit">
3841 <value>1</value>
3842 </feature>
3843 <feature name="PCIEXrclcL1Exit0">
3844 <value>1</value>
3845 </feature>
3846 <feature name="PCIEXrclcL1Exit1">
3847 <value>0</value>
3848 </feature>
3849 <feature name="PCIEXrclcL1Exit2">
3850 <value>0</value>
3851 </feature>
3852 <feature name="PCIEXrclcL1Exit3">
3853 <value>0</value>
3854 </feature>
3855 <feature name="PCIEXrclcL1Exit4">
3856 <value>0</value>
3857 </feature>
3858 <feature name="PCIEXrclcL1Exit5">
3859 <value>0</value>
3860 </feature>
3861 <feature name="PCIEXrclcL1Exit6">
3862 <value>0</value>
3863 </feature>
3864 <feature name="PCIEXrclcL1Exit7">
3865 <value>0</value>
3866 </feature>
3867 <feature name="PCIEXrcec">
3868 <value>0</value>
3869 </feature>
3870 <feature name="PCIEXRCECaddr">
3871 <value>0</value>
3872 </feature>
3873 <feature name="capRCECPtr">
3874 <value>0</value>
3875 </feature>
3876 <feature name="PCIEXrcecMap">
3877 <value>0</value>
3878 </feature>
3879 <feature name="PCIEXRCRB">
3880 <value>0</value>
3881 </feature>
3882 <feature name="PCIEXRCRBaddr">
3883 <value>0</value>
3884 </feature>
3885 <feature name="capRCRBPtr">
3886 <value>0</value>
3887 </feature>
3888 <feature name="PCIEXvcR0FCPHun">
3889 <value>0</value>
3890 </feature>
3891 <feature name="PCIEXvcR0FCPDun">
3892 <value>0</value>
3893 </feature>
3894 <feature name="PCIEXvcR0FCNPHun">
3895 <value>0</value>
3896 </feature>
3897 <feature name="PCIEXvcR0FCNPDun">
3898 <value>0</value>
3899 </feature>
3900 <feature name="PCIEXvcR0FCCPLHun">
3901 <value>0</value>
3902 </feature>
3903 <feature name="PCIEXvcR0FCCPLDun">
3904 <value>0</value>
3905 </feature>
3906 <feature name="PCIEXvcR0offset">
3907 <value>0</value>
3908 </feature>
3909 <feature name="PCIEXvcR0pend">
3910 <value>0</value>
3911 </feature>
3912 <feature name="PCIEXvcR1FCPHun">
3913 <value>0</value>
3914 </feature>
3915 <feature name="PCIEXvcR1FCPDun">
3916 <value>0</value>
3917 </feature>
3918 <feature name="PCIEXvcR1FCNPHun">
3919 <value>0</value>
3920 </feature>
3921 <feature name="PCIEXvcR1FCNPDun">
3922 <value>0</value>
3923 </feature>
3924 <feature name="PCIEXvcR1FCCPLHun">
3925 <value>0</value>
3926 </feature>
3927 <feature name="PCIEXvcR1FCCPLDun">
3928 <value>0</value>
3929 </feature>
3930 <feature name="PCIEXvcR1offset">
3931 <value>0</value>
3932 </feature>
3933 <feature name="PCIEXvcR2FCPHun">
3934 <value>0</value>
3935 </feature>
3936 <feature name="PCIEXvcR2FCPDun">
3937 <value>0</value>
3938 </feature>
3939 <feature name="PCIEXvcR2FCNPHun">
3940 <value>0</value>
3941 </feature>
3942 <feature name="PCIEXvcR2FCNPDun">
3943 <value>0</value>
3944 </feature>
3945 <feature name="PCIEXvcR2FCCPLHun">
3946 <value>0</value>
3947 </feature>
3948 <feature name="PCIEXvcR2FCCPLDun">
3949 <value>0</value>
3950 </feature>
3951 <feature name="PCIEXvcR2offset">
3952 <value>0</value>
3953 </feature>
3954 <feature name="PCIEXvcR3FCPHun">
3955 <value>0</value>
3956 </feature>
3957 <feature name="PCIEXvcR3FCPDun">
3958 <value>0</value>
3959 </feature>
3960 <feature name="PCIEXvcR3FCNPHun">
3961 <value>0</value>
3962 </feature>
3963 <feature name="PCIEXvcR3FCNPDun">
3964 <value>0</value>
3965 </feature>
3966 <feature name="PCIEXvcR3FCCPLHun">
3967 <value>0</value>
3968 </feature>
3969 <feature name="PCIEXvcR3FCCPLDun">
3970 <value>0</value>
3971 </feature>
3972 <feature name="PCIEXvcR3offset">
3973 <value>0</value>
3974 </feature>
3975 <feature name="PCIEXvcR4FCPHun">
3976 <value>0</value>
3977 </feature>
3978 <feature name="PCIEXvcR4FCPDun">
3979 <value>0</value>
3980 </feature>
3981 <feature name="PCIEXvcR4FCNPHun">
3982 <value>0</value>
3983 </feature>
3984 <feature name="PCIEXvcR4FCNPDun">
3985 <value>0</value>
3986 </feature>
3987 <feature name="PCIEXvcR4FCCPLHun">
3988 <value>0</value>
3989 </feature>
3990 <feature name="PCIEXvcR4FCCPLDun">
3991 <value>0</value>
3992 </feature>
3993 <feature name="PCIEXvcR4offset">
3994 <value>0</value>
3995 </feature>
3996 <feature name="PCIEXvcR5FCPHun">
3997 <value>0</value>
3998 </feature>
3999 <feature name="PCIEXvcR5FCPDun">
4000 <value>0</value>
4001 </feature>
4002 <feature name="PCIEXvcR5FCNPHun">
4003 <value>0</value>
4004 </feature>
4005 <feature name="PCIEXvcR5FCNPDun">
4006 <value>0</value>
4007 </feature>
4008 <feature name="PCIEXvcR5FCCPLHun">
4009 <value>0</value>
4010 </feature>
4011 <feature name="PCIEXvcR5FCCPLDun">
4012 <value>0</value>
4013 </feature>
4014 <feature name="PCIEXvcR5offset">
4015 <value>0</value>
4016 </feature>
4017 <feature name="PCIEXvcR6FCPHun">
4018 <value>0</value>
4019 </feature>
4020 <feature name="PCIEXvcR6FCPDun">
4021 <value>0</value>
4022 </feature>
4023 <feature name="PCIEXvcR6FCNPHun">
4024 <value>0</value>
4025 </feature>
4026 <feature name="PCIEXvcR6FCNPDun">
4027 <value>0</value>
4028 </feature>
4029 <feature name="PCIEXvcR6FCCPLHun">
4030 <value>0</value>
4031 </feature>
4032 <feature name="PCIEXvcR6FCCPLDun">
4033 <value>0</value>
4034 </feature>
4035 <feature name="PCIEXvcR6offset">
4036 <value>0</value>
4037 </feature>
4038 <feature name="PCIEXvcR7FCPHun">
4039 <value>0</value>
4040 </feature>
4041 <feature name="PCIEXvcR7FCPDun">
4042 <value>0</value>
4043 </feature>
4044 <feature name="PCIEXvcR7FCNPHun">
4045 <value>0</value>
4046 </feature>
4047 <feature name="PCIEXvcR7FCNPDun">
4048 <value>0</value>
4049 </feature>
4050 <feature name="PCIEXvcR7FCCPLHun">
4051 <value>0</value>
4052 </feature>
4053 <feature name="PCIEXvcR7FCCPLDun">
4054 <value>0</value>
4055 </feature>
4056 <feature name="PCIEXvcR7offset">
4057 <value>0</value>
4058 </feature>
4059 <feature name="PCIEXpbDarr">
4060 <value>0</value>
4061 </feature>
4062 <feature name="PCIEXvsec">
4063 <value>0</value>
4064 </feature>
4065 <feature name="PCIEXvsecDef">
4066 <value />
4067 </feature>
4068 <feature name="Ats">
4069 <value>0</value>
4070 </feature>
4071 <feature name="AtsITag">
4072 <value>0</value>
4073 </feature>
4074 <feature name="AtsITagGlobal">
4075 <value>0</value>
4076 </feature>
4077 <feature name="AtsITagPerDevice">
4078 <value>0</value>
4079 </feature>
4080 <feature name="AtsStu">
4081 <value>0</value>
4082 </feature>
4083 <feature name="AtsCap">
4084 <value>0</value>
4085 </feature>
4086 <feature name="AtsAddr">
4087 <value>0</value>
4088 </feature>
4089 <feature name="AtsNextPtr">
4090 <value>0</value>
4091 </feature>
4092 <feature name="AtsInvQDepth">
4093 <value>0</value>
4094 </feature>
4095 <feature name="PCIEACS">
4096 <value>0</value>
4097 </feature>
4098 <feature name="PCIEACSaddr">
4099 <value>0</value>
4100 </feature>
4101 <feature name="capACSPtr">
4102 <value>0</value>
4103 </feature>
4104 <feature name="PCIEACSver">
4105 <value>1</value>
4106 </feature>
4107 <feature name="PCIEACSsrcValid">
4108 <value>1</value>
4109 </feature>
4110 <feature name="PCIEACStranBlock">
4111 <value>1</value>
4112 </feature>
4113 <feature name="PCIEACSp2pReqRedirect">
4114 <value>1</value>
4115 </feature>
4116 <feature name="PCIEACSp2pCplRedirect">
4117 <value>1</value>
4118 </feature>
4119 <feature name="PCIEACSupForward">
4120 <value>1</value>
4121 </feature>
4122 <feature name="PCIEACSp2pEctrl">
4123 <value>1</value>
4124 </feature>
4125 <feature name="PCIEACSdirTranP2p">
4126 <value>1</value>
4127 </feature>
4128 <feature name="PCIEACSEctrlSize">
4129 <value>1</value>
4130 </feature>
4131 <feature name="PCIEariCap">
4132 <value>0</value>
4133 </feature>
4134 <feature name="PCIEariAddr">
4135 <value>0</value>
4136 </feature>
4137 <feature name="PCIEariPtr">
4138 <value>0</value>
4139 </feature>
4140 <feature name="PCIEariVer">
4141 <value>1</value>
4142 </feature>
4143 <feature name="PCIEariMFVCcap">
4144 <value>0</value>
4145 </feature>
4146 <feature name="PCIEariACScap">
4147 <value>0</value>
4148 </feature>
4149 <feature name="PCIEariNextFunc">
4150 <value>0</value>
4151 </feature>
4152 <feature name="PCIEiovSRcap">
4153 <value>0</value>
4154 </feature>
4155 <feature name="PCIEiovSRaddr">
4156 <value>0</value>
4157 </feature>
4158 <feature name="PCIEiovSRptr">
4159 <value>0</value>
4160 </feature>
4161 <feature name="PCIEiovSRver">
4162 <value>1</value>
4163 </feature>
4164 <feature name="PCIEiovSRmigCap">
4165 <value>0</value>
4166 </feature>
4167 <feature name="PCIEiovSRinitialVF">
4168 <value>0</value>
4169 </feature>
4170 <feature name="PCIEiovSRtotalVF">
4171 <value>0</value>
4172 </feature>
4173 <feature name="PCIEiovSRfuncDepLink">
4174 <value>0</value>
4175 </feature>
4176 <feature name="PCIEiovSRVFoffset">
4177 <value>0</value>
4178 </feature>
4179 <feature name="PCIEiovSRVFstride">
4180 <value>1</value>
4181 </feature>
4182 <feature name="PCIEiovSRVFdeviceID">
4183 <value>0</value>
4184 </feature>
4185 <feature name="PCIEiovSRpageSize">
4186 <value>0</value>
4187 </feature>
4188 <feature name="PCIEiovSRmig">
4189 <value>0</value>
4190 </feature>
4191 <feature name="PCIEiovSRmigOffset">
4192 <value>0</value>
4193 </feature>
4194 <feature name="PCIEiovSRmigBIR">
4195 <value>0</value>
4196 </feature>
4197 <feature name="PCIEiovSRbar0impl">
4198 <value>0</value>
4199 </feature>
4200 <feature name="PCIEiovSRbar0width">
4201 <value>32</value>
4202 </feature>
4203 <feature name="PCIEiovSRbar0size">
4204 <value>12</value>
4205 </feature>
4206 <feature name="PCIEiovSRbar0Pref">
4207 <value>0</value>
4208 </feature>
4209 <feature name="PCIEiovSRbar1impl">
4210 <value>0</value>
4211 </feature>
4212 <feature name="PCIEiovSRbar1width">
4213 <value>32</value>
4214 </feature>
4215 <feature name="PCIEiovSRbar1size">
4216 <value>12</value>
4217 </feature>
4218 <feature name="PCIEiovSRbar1Pref">
4219 <value>0</value>
4220 </feature>
4221 <feature name="PCIEiovSRbar2impl">
4222 <value>0</value>
4223 </feature>
4224 <feature name="PCIEiovSRbar2width">
4225 <value>32</value>
4226 </feature>
4227 <feature name="PCIEiovSRbar2size">
4228 <value>12</value>
4229 </feature>
4230 <feature name="PCIEiovSRbar2Pref">
4231 <value>0</value>
4232 </feature>
4233 <feature name="PCIEiovSRbar3impl">
4234 <value>0</value>
4235 </feature>
4236 <feature name="PCIEiovSRbar3width">
4237 <value>32</value>
4238 </feature>
4239 <feature name="PCIEiovSRbar3size">
4240 <value>12</value>
4241 </feature>
4242 <feature name="PCIEiovSRbar3Pref">
4243 <value>0</value>
4244 </feature>
4245 <feature name="PCIEiovSRbar4impl">
4246 <value>0</value>
4247 </feature>
4248 <feature name="PCIEiovSRbar4width">
4249 <value>32</value>
4250 </feature>
4251 <feature name="PCIEiovSRbar4size">
4252 <value>12</value>
4253 </feature>
4254 <feature name="PCIEiovSRbar4Pref">
4255 <value>0</value>
4256 </feature>
4257 <feature name="PCIEiovSRbar5impl">
4258 <value>0</value>
4259 </feature>
4260 <feature name="PCIEiovSRbar5width">
4261 <value>32</value>
4262 </feature>
4263 <feature name="PCIEiovSRbar5size">
4264 <value>12</value>
4265 </feature>
4266 <feature name="PCIEiovSRbar5Pref">
4267 <value>0</value>
4268 </feature>
4269 <pin name="Rate">
4270 <username>Rate</username>
4271 <bits>1</bits>
4272 </pin>
4273 <pin name="TxDeemph">
4274 <username>TxDeemph</username>
4275 <bits>1</bits>
4276 </pin>
4277 <pin name="TxMargin">
4278 <username>TxMargin</username>
4279 <bits>3</bits>
4280 </pin>
4281 <pin name="TxSwing">
4282 <username>TxSwing</username>
4283 <bits>1</bits>
4284 </pin>
4285 </functionality>
4286 <timing>
4287 <timing.set default="yes" name="default">
4288 <timing.parm name="ttoPollSpeed">
4289 <value>400.12 ps</value>
4290 </timing.parm>
4291 <timing.parm name="ttoCfgLnWaitUp">
4292 <value>2 ms</value>
4293 </timing.parm>
4294 <timing.parm name="ttoCfgLnWaitDn">
4295 <value>2 ms</value>
4296 </timing.parm>
4297 <timing.parm name="ttoPollConfig">
4298 <value>48 ms</value>
4299 </timing.parm>
4300 <timing.parm name="ttoPollActive">
4301 <value>2 us</value>
4302 </timing.parm>
4303 <timing.parm name="ttoDetectQuiet">
4304 <value>400 ns</value>
4305 </timing.parm>
4306 <timing.parm name="ttoDetectActive">
4307 <value>200 ns</value>
4308 </timing.parm>
4309 <timing.parm name="ttoCfgLkStartDn">
4310 <value>24 ms</value>
4311 </timing.parm>
4312 <timing.parm name="ttoCfgLkStartUp">
4313 <value>24 ms</value>
4314 </timing.parm>
4315 <timing.parm name="ttoCfgCompDn">
4316 <value>2 ms</value>
4317 </timing.parm>
4318 <timing.parm name="ttoCfgCompUp">
4319 <value>24 ms</value>
4320 </timing.parm>
4321 <timing.parm name="ttoCfgLkAcceptDn">
4322 <value>2 ms</value>
4323 </timing.parm>
4324 <timing.parm name="ttoCfgLkAcceptUp">
4325 <value>2 ms</value>
4326 </timing.parm>
4327 <timing.parm name="ttoCfgIdle">
4328 <value>2 ms</value>
4329 </timing.parm>
4330 <timing.parm name="ttoRcvrCfg">
4331 <value>48 ms</value>
4332 </timing.parm>
4333 <timing.parm name="ttoRcvrLock">
4334 <value>24 ms</value>
4335 </timing.parm>
4336 <timing.parm name="ttoRcvrIdle">
4337 <value>2 ms</value>
4338 </timing.parm>
4339 <timing.parm name="ttoDisabled">
4340 <value>2 ms</value>
4341 </timing.parm>
4342 <timing.parm name="ttoHotReset">
4343 <value>2 ms</value>
4344 </timing.parm>
4345 <timing.parm name="ttoLoopback">
4346 <value>2 ms</value>
4347 </timing.parm>
4348 <timing.parm name="ttoTLCpl">
4349 <value>5000 ns</value>
4350 </timing.parm>
4351 <timing.parm name="ttxUImin">
4352 <value>399.88 ps</value>
4353 </timing.parm>
4354 <timing.parm name="ttxUImax">
4355 <value>400.12 ps</value>
4356 </timing.parm>
4357 <timing.parm name="ttxIDLEmin">
4358 <value>50 clk</value>
4359 </timing.parm>
4360 <timing.parm name="ttxSetToIDLEmax">
4361 <value>20 clk</value>
4362 </timing.parm>
4363 <timing.parm name="ttxLaneSKEWmax">
4364 <value>1300 ps</value>
4365 </timing.parm>
4366 <timing.parm name="ttxCxLKmin">
4367 <value>0 ms</value>
4368 </timing.parm>
4369 <timing.parm name="ttxCxLKmax">
4370 <value>1 ms</value>
4371 </timing.parm>
4372 <timing.parm name="trxUImin">
4373 <value>399.88 ps</value>
4374 </timing.parm>
4375 <timing.parm name="trxUImax">
4376 <value>400.12 ps</value>
4377 </timing.parm>
4378 <timing.parm name="trxSetToDetectmax">
4379 <value>10 ms</value>
4380 </timing.parm>
4381 <timing.parm name="trxTotalSKEWmax">
4382 <value>20 ns</value>
4383 </timing.parm>
4384 <timing.parm name="ttoFcInitRollover" enabled="no" />
4385 <timing.parm name="ttxIdleToDiff" enabled="no" />
4386 <timing.parm name="ttoResetTOCfg" enabled="no">
4387 <value>100 ms</value>
4388 </timing.parm>
4389 <timing.parm name="ttoResetTODetect" enabled="no">
4390 <value>20 ms</value>
4391 </timing.parm>
4392 <timing.parm name="ttoLoopbackEntry" enabled="no">
4393 <value>100 ms</value>
4394 </timing.parm>
4395 <timing.parm name="ttoLoopbackEntry2Active" enabled="no">
4396 <value>2 ms</value>
4397 </timing.parm>
4398 <timing.parm name="ttoLoopbackEntryEIMaster" enabled="no">
4399 <value>2 ms</value>
4400 </timing.parm>
4401 <timing.parm name="ttoLoopbackEntryEISlave" enabled="no">
4402 <value>1 ms</value>
4403 </timing.parm>
4404 <timing.parm name="ttoTLCplRx" enabled="no">
4405 <value>0 us</value>
4406 </timing.parm>
4407 <timing.parm name="ttoFCmin" enabled="no">
4408 <value>200 us</value>
4409 </timing.parm>
4410 <timing.parm name="ttoFCmax" enabled="no">
4411 <value>300 us</value>
4412 </timing.parm>
4413 <timing.parm name="ttoPMEmin" enabled="no">
4414 <value>95 ms</value>
4415 </timing.parm>
4416 <timing.parm name="ttoPMEmax" enabled="no">
4417 <value>150 ms</value>
4418 </timing.parm>
4419 <timing.parm name="ttoL0smax" enabled="no">
4420 <value>7 us</value>
4421 </timing.parm>
4422 <timing.parm name="ttoL0smin" enabled="no">
4423 <value>7 us</value>
4424 </timing.parm>
4425 <timing.parm name="ttoL1min" enabled="no">
4426 <value>0 us</value>
4427 </timing.parm>
4428 <timing.parm name="ttoL1max" enabled="no">
4429 <value>0 us</value>
4430 </timing.parm>
4431 <timing.parm name="ttoL1aspmmin" enabled="no">
4432 <value>20 us</value>
4433 </timing.parm>
4434 <timing.parm name="ttoL1aspmmax" enabled="no">
4435 <value>20 us</value>
4436 </timing.parm>
4437 <timing.parm name="ttoTurnOffmax" enabled="no">
4438 <value>20 us</value>
4439 </timing.parm>
4440 <timing.parm name="ttoPMmax" enabled="no">
4441 <value>1 s</value>
4442 </timing.parm>
4443 <timing.parm name="ttoD3hot2D0max" enabled="no">
4444 <value>10 ms</value>
4445 </timing.parm>
4446 <timing.parm name="ttoPMHSmax" enabled="no">
4447 <value>10 ms</value>
4448 </timing.parm>
4449 <timing.parm name="ttoCRSmax" enabled="no">
4450 <value>400 ps</value>
4451 </timing.parm>
4452 <timing.parm name="ttoSysInit" enabled="no">
4453 <value>0 ms</value>
4454 </timing.parm>
4455 <timing.parm name="ttoPReqAccLimit" enabled="no">
4456 <value>10 us</value>
4457 </timing.parm>
4458 <timing.parm name="ttoHPCmdMax" enabled="no">
4459 <value>1 s</value>
4460 </timing.parm>
4461 <timing.parm name="ttoHPCmdMin" enabled="no">
4462 <value>50 ns</value>
4463 </timing.parm>
4464 <timing.parm name="ttoPCLKmarginMax" enabled="no">
4465 <value>100 ps</value>
4466 </timing.parm>
4467 <timing.parm name="ttoInferEIRcvrCfg2_5" enabled="no">
4468 <value>1280 clk</value>
4469 </timing.parm>
4470 <timing.parm name="ttoInferEIRcvrCfg5_0" enabled="no">
4471 <value>1280 clk</value>
4472 </timing.parm>
4473 <timing.parm name="ttoInferEISpeed2_5" enabled="no">
4474 <value>1280 clk</value>
4475 </timing.parm>
4476 <timing.parm name="ttoInferEISpeed5_0" enabled="no">
4477 <value>1280 clk</value>
4478 </timing.parm>
4479 <timing.parm name="ttoInferEIExitSpeed2_5" enabled="no">
4480 <value>2000 clk</value>
4481 </timing.parm>
4482 <timing.parm name="ttoInferEIExitSpeed5_0" enabled="no">
4483 <value>16000 clk</value>
4484 </timing.parm>
4485 <timing.parm name="ttoInL1N2_5Min" enabled="no">
4486 <value>40 ns</value>
4487 </timing.parm>
4488 <timing.parm name="ttoRecSpeedSuccTxEiMin" enabled="no">
4489 <value>2000 clk</value>
4490 </timing.parm>
4491 <timing.parm name="ttoRecSpeedTxEiMin" enabled="no">
4492 <value>6 us</value>
4493 </timing.parm>
4494 <timing.parm name="ttoRecSpeedTxEiMax" enabled="no">
4495 <value>1 ms</value>
4496 </timing.parm>
4497 <timing.parm name="ttoRecSpeed" enabled="no">
4498 <value>48 ms</value>
4499 </timing.parm>
4500 <timing.parm name="ttoPollCompTxEiMin" enabled="no">
4501 <value>1 ms</value>
4502 </timing.parm>
4503 <timing.parm name="ttoPollCompTxEiMax" enabled="no">
4504 <value>2 ms</value>
4505 </timing.parm>
4506 <timing.parm name="ttoUpconfig" enabled="no">
4507 <value>1 ms</value>
4508 </timing.parm>
4509 <timing.parm name="ttoFLRmax" enabled="no">
4510 <value>100 ms</value>
4511 </timing.parm>
4512 <timing.parm name="ttoFLRmin" enabled="no">
4513 <value>100 ms</value>
4514 </timing.parm>
4515 <timing.parm name="ttoFLRInit" enabled="no">
4516 <value>0 ms</value>
4517 </timing.parm>
4518 <timing.parm name="ttoIOVinit" enabled="no">
4519 <value>0 ms</value>
4520 </timing.parm>
4521 <timing.parm name="ttxIdleToValid" enabled="no">
4522 <value>20 clk</value>
4523 </timing.parm>
4524 <timing.parm name="ttxReceiverDetect" enabled="no">
4525 <value>0 clk</value>
4526 </timing.parm>
4527 <timing.parm name="ttxFCmin" enabled="no">
4528 <value>30 us</value>
4529 </timing.parm>
4530 <timing.parm name="ttxFCmax" enabled="no">
4531 <value>45 us</value>
4532 </timing.parm>
4533 <timing.parm name="ttxFCESmin" enabled="no">
4534 <value>120 us</value>
4535 </timing.parm>
4536 <timing.parm name="ttxFCESmax" enabled="no">
4537 <value>180 us</value>
4538 </timing.parm>
4539 <timing.parm name="ttxFCL1exitMax" enabled="no">
4540 <value>1 us</value>
4541 </timing.parm>
4542 <timing.parm name="ttxTurnOffMin" enabled="no">
4543 <value>1 ms</value>
4544 </timing.parm>
4545 <timing.parm name="ttxTurnOffMax" enabled="no">
4546 <value>10 ms</value>
4547 </timing.parm>
4548 <timing.parm name="ttxPwrOffMin" enabled="no">
4549 <value>100 ns</value>
4550 </timing.parm>
4551 <timing.parm name="ttx2L1aspmMin" enabled="no">
4552 <value>10 us</value>
4553 </timing.parm>
4554 <timing.parm name="ttx2L1aspmUpMin" enabled="no">
4555 <value>9.5 us</value>
4556 </timing.parm>
4557 <timing.parm name="ttxReadyMax" enabled="no">
4558 <value>0 ns</value>
4559 </timing.parm>
4560 <timing.parm name="ttxPcie2UImin" enabled="no">
4561 <value>199.94 ps</value>
4562 </timing.parm>
4563 <timing.parm name="ttxPcie2UImax" enabled="no">
4564 <value>200.06 ps</value>
4565 </timing.parm>
4566 <timing.parm name="ttxG2DetectQuietMin" enabled="no">
4567 <value>1 ms</value>
4568 </timing.parm>
4569 <timing.parm name="trxPcie2UImin" enabled="no">
4570 <value>199.94 ps</value>
4571 </timing.parm>
4572 <timing.parm name="trxPcie2UImax" enabled="no">
4573 <value>200.06 ps</value>
4574 </timing.parm>
4575 <timing.parm name="trxInferEImax" enabled="no">
4576 <value>128 us</value>
4577 </timing.parm>
4578 <timing.parm name="trxInferClkEIsuccmax" enabled="no">
4579 <value>1280 clk</value>
4580 </timing.parm>
4581 <timing.parm name="trxInferClkEImax" enabled="no">
4582 <value>16000 clk</value>
4583 </timing.parm>
4584 <timing.parm name="ttxPhyLatency" enabled="no">
4585 <value>1 clk</value>
4586 </timing.parm>
4587 <timing.parm name="trxPhyLatency" enabled="no">
4588 <value>1 clk</value>
4589 </timing.parm>
4590 <timing.parm name="ttxBeaconMax" enabled="no">
4591 <value>10 ns</value>
4592 </timing.parm>
4593 <timing.parm name="ttxBeaconMin" enabled="no">
4594 <value>1 ns</value>
4595 </timing.parm>
4596 <timing.parm name="trxBeaconMax" enabled="no">
4597 <value>10 ns</value>
4598 </timing.parm>
4599 <timing.parm name="trxBeaconMin" enabled="no">
4600 <value>0 ns</value>
4601 </timing.parm>
4602 <timing.parm name="trxElecIdleMax" enabled="no">
4603 <value>10 ns</value>
4604 </timing.parm>
4605 <timing.parm name="trxElecIdleMin" enabled="no">
4606 <value>1 ns</value>
4607 </timing.parm>
4608 <timing.parm name="ttxDetectRxMax" enabled="no">
4609 <value>10 ns</value>
4610 </timing.parm>
4611 <timing.parm name="ttxDetectRxMin" enabled="no">
4612 <value>1 ns</value>
4613 </timing.parm>
4614 <timing.parm name="trxPhyLockMax" enabled="no">
4615 <value>1 us</value>
4616 </timing.parm>
4617 <timing.parm name="trxPhyLockMin" enabled="no">
4618 <value>0 us</value>
4619 </timing.parm>
4620 <timing.parm name="ttxSymLockSkipSet" enabled="no">
4621 <value>0 clk</value>
4622 </timing.parm>
4623 <timing.parm name="tP0ToP0sMax" enabled="no">
4624 <value>0 clk</value>
4625 </timing.parm>
4626 <timing.parm name="tP0ToP0sMin" enabled="no">
4627 <value>0 clk</value>
4628 </timing.parm>
4629 <timing.parm name="tP0ToP1Max" enabled="no">
4630 <value>0 clk</value>
4631 </timing.parm>
4632 <timing.parm name="tP0ToP1Min" enabled="no">
4633 <value>0 clk</value>
4634 </timing.parm>
4635 <timing.parm name="tP0ToP2Max" enabled="no">
4636 <value>0 clk</value>
4637 </timing.parm>
4638 <timing.parm name="tP0ToP2Min" enabled="no">
4639 <value>0 clk</value>
4640 </timing.parm>
4641 <timing.parm name="tP0sToP0Max" enabled="no">
4642 <value>0 clk</value>
4643 </timing.parm>
4644 <timing.parm name="tP0sToP0Min" enabled="no">
4645 <value>0 clk</value>
4646 </timing.parm>
4647 <timing.parm name="tP1ToP0Max" enabled="no">
4648 <value>0 clk</value>
4649 </timing.parm>
4650 <timing.parm name="tP1ToP0Min" enabled="no">
4651 <value>0 clk</value>
4652 </timing.parm>
4653 <timing.parm name="tP2ToP1Max" enabled="no">
4654 <value>10 ns</value>
4655 </timing.parm>
4656 <timing.parm name="tP2ToP1Min" enabled="no">
4657 <value>1 ns</value>
4658 </timing.parm>
4659 <timing.parm name="tP2ShutdownMax" enabled="no">
4660 <value>100 ns</value>
4661 </timing.parm>
4662 <timing.parm name="tP2ShutdownMin" enabled="no">
4663 <value>1 ns</value>
4664 </timing.parm>
4665 <timing.parm name="tP1StartupMax" enabled="no">
4666 <value>100 ns</value>
4667 </timing.parm>
4668 <timing.parm name="tP1StartupMin" enabled="no">
4669 <value>1 ns</value>
4670 </timing.parm>
4671 <timing.parm name="tResetToReadyMax" enabled="no">
4672 <value>100 ns</value>
4673 </timing.parm>
4674 <timing.parm name="tResetToReadyMin" enabled="no">
4675 <value>1 ns</value>
4676 </timing.parm>
4677 <timing.parm name="ttxPCLKToDataValidMax" enabled="no">
4678 <value>1 ns</value>
4679 </timing.parm>
4680 <timing.parm name="ttxPCLKToDataValidMin" enabled="no">
4681 <value>0 ns</value>
4682 </timing.parm>
4683 <timing.parm name="trxPCLKSetupMax" enabled="no">
4684 <value>1 ns</value>
4685 </timing.parm>
4686 <timing.parm name="trxPCLKHoldMin" enabled="no">
4687 <value>0 ns</value>
4688 </timing.parm>
4689 <timing.parm name="ttxResetToOutputMax" enabled="no">
4690 <value>1 ns</value>
4691 </timing.parm>
4692 <timing.parm name="ttxResetToOutputMin" enabled="no">
4693 <value>0 ns</value>
4694 </timing.parm>
4695 <timing.parm name="ttxAsyncPhyStatusMax" enabled="no">
4696 <value>1 ns</value>
4697 </timing.parm>
4698 <timing.parm name="ttxAsyncPhyStatusMin" enabled="no">
4699 <value>0 ns</value>
4700 </timing.parm>
4701 <timing.parm name="ttxDataRateChangeMin" enabled="no">
4702 <value>4 ns</value>
4703 </timing.parm>
4704 <timing.parm name="ttxDataRateChange2Min" enabled="no">
4705 <value>4 ns</value>
4706 </timing.parm>
4707 </timing.set>
4708 </timing>
4709 </part>
4710</soma>
4711
Full OpenSPARC design & verification tarball including full HDL.