[OpenSPARC-T2-DV] / verif / env / ilu_peu / vera / N2str / ilupeuPioCfgIOWrStr.vr

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ilupeuPioCfgIOWrStr.vr
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
class PioCfgIOWrPEUStr extends PioBasePEUStr {


  // ******************************************************************
  // The Test Environment objects need to execute the strategy.
  // ******************************************************************
  protected PEUTestEnv              _env;
  protected integer                 _errQueue;


  // ******************************************************************
  // TLP Fields - These fields will be randomized using the parameters
  // in the following section, and obeying the constraints defined
  // within this class.
  // ******************************************************************  
  protected         bit [1:0]       _format_req;
  protected         bit [1:0]       _format_cpl;
  protected         bit [4:0]       _type_req;
  protected         bit [4:0]       _type_cpl;

  protected         bit [2:0]       _tc;
  
  protected         bit             _td_req;
  protected         bit             _td_cpl;
  protected         bit             _ep_req;
  protected         bit             _ep_cpl;

  protected         bit [1:0]       _attr;
  protected         bit [9:0]       _len_req;
  protected         bit [9:0]       _len_cpl;
  protected         bit [15:0]      _req_id;
  protected         bit [7:0]       _tag;
  protected rand    bit [31:0]      _addr_lsb;

  protected         bit [3:0]       _last_dwbe;
  protected         bit [3:0]       _first_dwbe;

  protected         bit [15:0]      _cpl_id;
  protected         bit [2:0]       _cpl_status;
  protected         bit             _bcm;
  protected         bit [11:0]      _byte_count;
  protected         bit [6:0]       _lower_addr;
  protected         bit [63:0]      _data;

  protected	bit [PEC_PCI__HDR]	reqHdr;
  protected	bit [PEC_PCI__HDR]	cplHdr;
  protected	bit [PEC_PCI__HDR]	urHdr;

  protected	bit [7:0]		dataAddr;
  
  static        bit                 firstCfgWr0;
  static        bit [15:0]          firstCfgWr0ID;
  
  // ******************************************************************
  // The following constraint is used to generate the correct values
  // for the TLP.
  // ******************************************************************  
  constraint generate_tlp {

    this._addr_lsb in {this._addr_lsb_min : this._addr_lsb_max};
    
    if (this._type_req == PEC_PCI__TYPE_CFG0){
      this._addr_lsb[15:12] == 4'b_0000;   //Reserved bits
      this._addr_lsb[11:8] in {1 : 15 };   //Ext Reg - 0 messes up Denali

    }

    if (this._type_req == PEC_PCI__TYPE_CFG1)
      this._addr_lsb[15:12] == 4'b_0000;
  }     


  // ******************************************************************
  // Constructor
  // ******************************************************************
  public task new(PEUTestEnv a_env, (integer a_errQueue = 'bx));


  // ******************************************************************
  // Break this out as common class fullchip and ios can use
  // ******************************************************************
  public task SetPacketParams();
  task SetCfgWrtSuppressErrs();

  // ******************************************************************
  // Execute the strategy.  Drive a TLP into the ILU, and expect it out
  // of the PEU.
  // ******************************************************************
   public task Execute();  
}


//-------------------------------------------------------------------
// Method Name: 
// Description: 
//-------------------------------------------------------------------
task PioCfgIOWrPEUStr::new(PEUTestEnv a_env, (integer a_errQueue = 'bx)) {

  
  super.new(a_env);
  this._env = a_env;  
  this._errQueue = a_errQueue;
}


//-------------------------------------------------------------------
// Method Name: 
// Description: 
//-------------------------------------------------------------------
task PioCfgIOWrPEUStr::SetPacketParams() {

  integer pass_constrain = 0;
  this._env.allocWrTag(this._tag, dataAddr);


  this._format_req = PEC_PCI__FMT_DATA_3DW;
  this._format_cpl = PEC_PCI__FMT_NO_DATA_3DW;
  this._type_cpl   = PEC_PCI__TYPE_CPL;
  this._tc         = 3'b_000;
  this._td_req     = 1'b_0;
  this._ep_req     = 1'b_0;
  this._attr       = 2'b_00;
  this._len_req    = 10'h_001;
  this._len_cpl    = 10'h_000;
//  this._req_id     = 16'h_0000;
//Fullchip may need to set this in their tests
  this._req_id     = urandom_range(this._req_id_max, this._req_id_min);
  this._last_dwbe  = 4'b_0000;   
  this._byte_count = 12'd_4;
  this._lower_addr = 7'b_000_0000;

  
  this._first_dwbe = urandom_range(this._first_dwbe_max, this._first_dwbe_min);
  this._cpl_id     = urandom_range(this._cpl_id_max, this._cpl_id_min);
  this._data[63:32] = urandom_range(this._data_max[63:32],   this._data_min[63:32]);
  this._data[31: 0] = urandom_range(this._data_max[31: 0],   this._data_min[31: 0]);


  randcase {
    this._type_req_prob_cfg0  : this._type_req = PEC_PCI__TYPE_CFG0;
    this._type_req_prob_cfg1  : this._type_req = PEC_PCI__TYPE_CFG1;
    this._type_req_prob_io    : this._type_req = PEC_PCI__TYPE_IO;
  }
  
  randcase {
    this._td_cpl_prob_false   : this._td_cpl = 1'b_0;
    this._td_cpl_prob_true    : this._td_cpl = 1'b_1;
  }

  randcase {
    this._ep_cpl_prob_false   : this._ep_cpl = 1'b_0;
    this._ep_cpl_prob_true    : this._ep_cpl = 1'b_1;
  }
  
  randcase { 
    this._cpl_status_prob_sc    : this._cpl_status = PEC_PCI__CPL_STATUS_SC;
    this._cpl_status_prob_ur    : this._cpl_status = PEC_PCI__CPL_STATUS_UR;
    this._cpl_status_prob_crs   : this._cpl_status = PEC_PCI__CPL_STATUS_CRS;
    this._cpl_status_prob_ca    : this._cpl_status = PEC_PCI__CPL_STATUS_CA;
    this._cpl_status_prob_rsvd1 : this._cpl_status = PEC_PCI__CPL_STATUS_RSVD1;
    this._cpl_status_prob_rsvd2 : this._cpl_status = PEC_PCI__CPL_STATUS_RSVD2;
    this._cpl_status_prob_rsvd3 : this._cpl_status = PEC_PCI__CPL_STATUS_RSVD3;
    this._cpl_status_prob_rsvd4 : this._cpl_status = PEC_PCI__CPL_STATUS_RSVD4;
  }

  randcase {
    this._bcm_prob_false      : this._bcm = 1'b_0;
    this._bcm_prob_true       : this._bcm = 1'b_1;
  }

#ifdef N2_FC
  while (!pass_constrain)
  {
    this._addr_lsb = urandom_range(this._addr_lsb_max, this._addr_lsb_min);
    pass_constrain = 1;
    if (this._type_req == PEC_PCI__TYPE_CFG0){
      if (this._addr_lsb[15:12] != 4'b_0000) pass_constrain = 0;   //Reserved bits
      if (this._addr_lsb[11:8] == 4'b0) pass_constrain = 0;  //Ext Reg - 0 messes up Denali
    }

    if (this._type_req == PEC_PCI__TYPE_CFG1) {
      if (this._addr_lsb[15:12] != 4'b_0000) pass_constrain = 0;
    }     
  }
/// random constrain end
#else  
  
  if( this.randomize() != OK ) {
    _env.Report.report(RTYP_TEST_ERROR,"PioCfgIOWrPEUStr::SetPacketParams - randomize failure \n" );
  }
#endif

  if (this._type_req == PEC_PCI__TYPE_CFG0){
     if( firstCfgWr0 !== 1'b1 ){
        firstCfgWr0ID = this._addr_lsb[31:16];
        firstCfgWr0 = 1'b1;
     }
     this._addr_lsb[31:16] = firstCfgWr0ID ;
  }


  reqHdr [PEC_PCI__HDR]            = {128{1'b_0}};  
  reqHdr [PEC_PCI__FMT]            = this._format_req;
  reqHdr [PEC_PCI__TYPE]           = this._type_req;
  reqHdr [PEC_PCI__TC]             = this._tc;
  reqHdr [PEC_PCI__TD]             = this._td_req;
  reqHdr [PEC_PCI__EP]             = this._ep_req;
  reqHdr [PEC_PCI__ATTR]           = this._attr;
  reqHdr [PEC_PCI__LEN]            = this._len_req;
  reqHdr [PEC_PCI__REQ_ID]         = this._req_id;
  reqHdr [PEC_PCI__TLP_TAG]        = this._tag;
  reqHdr [PEC_PCI__LAST_DWBE]      = this._last_dwbe;
  reqHdr [PEC_PCI__FIRST_DWBE]     = this._first_dwbe;
  reqHdr [PEC_PCI__ADDR32]         = { this._addr_lsb[31:2], 2'b_00 };
  
  cplHdr [PEC_PCI__HDR]            = {128{1'b_0}};
  cplHdr [PEC_PCI__FMT]            = this._format_cpl;
  cplHdr [PEC_PCI__TYPE]           = this._type_cpl;
  cplHdr [PEC_PCI__TC]             = this._tc;
  cplHdr [PEC_PCI__TD]             = this._td_cpl;
  cplHdr [PEC_PCI__EP]             = this._ep_cpl;
  cplHdr [PEC_PCI__ATTR]           = this._attr;
  cplHdr [PEC_PCI__LEN]            = this._len_cpl;
  cplHdr [PEC_PCI__CPL_ID]         = this._cpl_id;
  cplHdr [PEC_PCI__CPL_STATUS]     = this._cpl_status;
  cplHdr [PEC_PCI__BCM]            = this._bcm;
  cplHdr [PEC_PCI__BYTECOUNT]      = this._byte_count;
  cplHdr [PEC_PCI__CPL_REQ_ID]     = this._req_id;
  cplHdr [PEC_PCI__CPL_TAG]        = this._tag;
  cplHdr [PEC_PCI__LOWADDR]        = this._lower_addr;

  urHdr [PEC_PCI__HDR]             = {128{1'b_0}};
  urHdr [PEC_PCI__FMT]             = this._format_cpl;
  urHdr [PEC_PCI__TYPE]            = this._type_cpl;
  urHdr [PEC_PCI__TC]              = this._tc;
  urHdr [PEC_PCI__TD]              = this._td_cpl;
  urHdr [PEC_PCI__EP]              = this._ep_cpl;
  urHdr [PEC_PCI__ATTR]            = this._attr;
  urHdr [PEC_PCI__LEN]             = this._len_cpl;
  urHdr [PEC_PCI__CPL_ID]          = this._cpl_id;
  urHdr [PEC_PCI__CPL_STATUS]      = PEC_PCI__CPL_STATUS_UR;
  urHdr [PEC_PCI__BCM]             = this._bcm;
  urHdr [PEC_PCI__BYTECOUNT]       = this._byte_count;
  urHdr [PEC_PCI__CPL_REQ_ID]      = this._req_id;
  urHdr [PEC_PCI__CPL_TAG]         = this._tag;
  urHdr [PEC_PCI__LOWADDR]         = this._lower_addr;

  //Suppress all errors Denali reports due to random Cfg Write 0
  if( this._type_req === PEC_PCI__TYPE_CFG0 ){
     SetCfgWrtSuppressErrs();
  }
}

task PioCfgIOWrPEUStr::SetCfgWrtSuppressErrs() {
    this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_FATAL_CFG_DID_TXCPLQ );
    this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_FATAL_CFG_DID_RXCPLQ );
    this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_FATAL_CFG_VCARB1_1 );
    this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_FATAL_CFG_TC_DELTC );

}

task PioCfgIOWrPEUStr::Execute() {
  
  SetPacketParams();
  
  this._env.driveILU(reqHdr, dataAddr, this._data);

  this._env.expectPCIE(reqHdr, this._data);

  if ( (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD1) ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD2) ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD3) ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD4)) {
      this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlCplSt ); //Malformed Completion TLP - Reserved completion status (%u).
  }
  
  //
  repeat( urandom_range( _env.Scenario.ilupeuPioCfgIOWrCplDelayMax, _env.Scenario.ilupeuPioCfgIOWrCplDelayMin)) @(posedge CLOCK);

  this._env.drivePCIE(cplHdr, 0);

  
  if ((this._cpl_status === PEC_PCI__CPL_STATUS_CA)    ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_UR)    ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD1) ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD2) ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD3) ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD4)) {
    
    this._env.expectILU(urHdr, this._data);
    mailbox_put(this._errQueue, e_ERR_oe_wuc);
    mailbox_put(this._errQueue, cplHdr );
    if ( (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD1) ||
         (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD2) ||
         (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD3) ||
         (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD4)) {
      this._env.Pod.FNXPCIEEnableTrans.unSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlCplSt ); //Malformed Completion TLP - Reserved completion status (%u).
  }
  }

  else if (this._cpl_status === PEC_PCI__CPL_STATUS_CRS) {

    this._env.expectTimeoutCpl(reqHdr);
    mailbox_put(this._errQueue, e_ERR_oe_crs);
    mailbox_put(this._errQueue, cplHdr );
  }
  
  else if (this._ep_cpl === 1'b_1) {

    cplHdr [PEC_PCI__EP] = 0;
    this._env.drivePCIE(cplHdr, 0);
    this._env.expectILU(cplHdr, 0);
    cplHdr [PEC_PCI__EP] = 1;
    mailbox_put(this._errQueue, e_ERR_ue_pp);
    mailbox_put(this._errQueue, cplHdr);
  }
  
  else {
    
    this._env.expectILU(cplHdr, this._data);
  }


  this._env.freePioTag(this._tag);
}
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: ilupeuPioCfgIOWrStr.vr
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	class PioCfgIOWrPEUStr extends PioBasePEUStr {
	36
	37
	38	// ******************************************************************
	39	// The Test Environment objects need to execute the strategy.
	40	// ******************************************************************
	41	protected PEUTestEnv _env;
	42	protected integer _errQueue;
	43
	44
	45	// ******************************************************************
	46	// TLP Fields - These fields will be randomized using the parameters
	47	// in the following section, and obeying the constraints defined
	48	// within this class.
	49	// ******************************************************************
	50	protected bit [1:0] _format_req;
	51	protected bit [1:0] _format_cpl;
	52	protected bit [4:0] _type_req;
	53	protected bit [4:0] _type_cpl;
	54
	55	protected bit [2:0] _tc;
	56
	57	protected bit _td_req;
	58	protected bit _td_cpl;
	59	protected bit _ep_req;
	60	protected bit _ep_cpl;
	61
	62	protected bit [1:0] _attr;
	63	protected bit [9:0] _len_req;
	64	protected bit [9:0] _len_cpl;
65	protected bit [15:0] _req_id;
66	protected bit [7:0] _tag;
67	protected rand bit [31:0] _addr_lsb;
68
69	protected bit [3:0] _last_dwbe;
70	protected bit [3:0] _first_dwbe;
71
72	protected bit [15:0] _cpl_id;
73	protected bit [2:0] _cpl_status;
74	protected bit _bcm;
75	protected bit [11:0] _byte_count;
76	protected bit [6:0] _lower_addr;
77	protected bit [63:0] _data;
78
79	protected bit [PEC_PCI__HDR] reqHdr;
80	protected bit [PEC_PCI__HDR] cplHdr;
81	protected bit [PEC_PCI__HDR] urHdr;
82
83	protected bit [7:0] dataAddr;
84
85	static bit firstCfgWr0;
86	static bit [15:0] firstCfgWr0ID;
87
88	// ******************************************************************
89	// The following constraint is used to generate the correct values
90	// for the TLP.
91	// ******************************************************************
92	constraint generate_tlp {
93
94	this._addr_lsb in {this._addr_lsb_min : this._addr_lsb_max};
95
96	if (this._type_req == PEC_PCI__TYPE_CFG0){
97	this._addr_lsb[15:12] == 4'b_0000; //Reserved bits
98	this._addr_lsb[11:8] in {1 : 15 }; //Ext Reg - 0 messes up Denali
99
100	}
101
102	if (this._type_req == PEC_PCI__TYPE_CFG1)
103	this._addr_lsb[15:12] == 4'b_0000;
104	}
105
106
107	// ******************************************************************
108	// Constructor
109	// ******************************************************************
110	public task new(PEUTestEnv a_env, (integer a_errQueue = 'bx));
111
112
113	// ******************************************************************
114	// Break this out as common class fullchip and ios can use
115	// ******************************************************************
116	public task SetPacketParams();
117	task SetCfgWrtSuppressErrs();
118
119	// ******************************************************************
120	// Execute the strategy. Drive a TLP into the ILU, and expect it out
121	// of the PEU.
122	// ******************************************************************
123	public task Execute();
124	}
125
126
127
128	//-------------------------------------------------------------------
129	// Method Name:
130	// Description:
131	//-------------------------------------------------------------------
132	task PioCfgIOWrPEUStr::new(PEUTestEnv a_env, (integer a_errQueue = 'bx)) {
133
134
135	super.new(a_env);
136	this._env = a_env;
137	this._errQueue = a_errQueue;
138	}
139
140
141
142	//-------------------------------------------------------------------
143	// Method Name:
144	// Description:
145	//-------------------------------------------------------------------
146	task PioCfgIOWrPEUStr::SetPacketParams() {
147
148	integer pass_constrain = 0;
149	this._env.allocWrTag(this._tag, dataAddr);
150
151
152	this._format_req = PEC_PCI__FMT_DATA_3DW;
153	this._format_cpl = PEC_PCI__FMT_NO_DATA_3DW;
154	this._type_cpl = PEC_PCI__TYPE_CPL;
155	this._tc = 3'b_000;
156	this._td_req = 1'b_0;
157	this._ep_req = 1'b_0;
158	this._attr = 2'b_00;
159	this._len_req = 10'h_001;
160	this._len_cpl = 10'h_000;
161	// this._req_id = 16'h_0000;
162	//Fullchip may need to set this in their tests
163	this._req_id = urandom_range(this._req_id_max, this._req_id_min);
164	this._last_dwbe = 4'b_0000;
165	this._byte_count = 12'd_4;
166	this._lower_addr = 7'b_000_0000;
167
168
169	this._first_dwbe = urandom_range(this._first_dwbe_max, this._first_dwbe_min);
170	this._cpl_id = urandom_range(this._cpl_id_max, this._cpl_id_min);
171	this._data[63:32] = urandom_range(this._data_max[63:32], this._data_min[63:32]);
172	this._data[31: 0] = urandom_range(this._data_max[31: 0], this._data_min[31: 0]);
173
174
175	randcase {
176	this._type_req_prob_cfg0 : this._type_req = PEC_PCI__TYPE_CFG0;
177	this._type_req_prob_cfg1 : this._type_req = PEC_PCI__TYPE_CFG1;
178	this._type_req_prob_io : this._type_req = PEC_PCI__TYPE_IO;
179	}
180
181	randcase {
182	this._td_cpl_prob_false : this._td_cpl = 1'b_0;
183	this._td_cpl_prob_true : this._td_cpl = 1'b_1;
184	}
185
186	randcase {
187	this._ep_cpl_prob_false : this._ep_cpl = 1'b_0;
188	this._ep_cpl_prob_true : this._ep_cpl = 1'b_1;
189	}
190
191	randcase {
192	this._cpl_status_prob_sc : this._cpl_status = PEC_PCI__CPL_STATUS_SC;
193	this._cpl_status_prob_ur : this._cpl_status = PEC_PCI__CPL_STATUS_UR;
194	this._cpl_status_prob_crs : this._cpl_status = PEC_PCI__CPL_STATUS_CRS;
195	this._cpl_status_prob_ca : this._cpl_status = PEC_PCI__CPL_STATUS_CA;
196	this._cpl_status_prob_rsvd1 : this._cpl_status = PEC_PCI__CPL_STATUS_RSVD1;
197	this._cpl_status_prob_rsvd2 : this._cpl_status = PEC_PCI__CPL_STATUS_RSVD2;
198	this._cpl_status_prob_rsvd3 : this._cpl_status = PEC_PCI__CPL_STATUS_RSVD3;
199	this._cpl_status_prob_rsvd4 : this._cpl_status = PEC_PCI__CPL_STATUS_RSVD4;
200	}
201
202	randcase {
203	this._bcm_prob_false : this._bcm = 1'b_0;
204	this._bcm_prob_true : this._bcm = 1'b_1;
205	}
206
207	#ifdef N2_FC
208	while (!pass_constrain)
209	{
210	this._addr_lsb = urandom_range(this._addr_lsb_max, this._addr_lsb_min);
211	pass_constrain = 1;
212	if (this._type_req == PEC_PCI__TYPE_CFG0){
213	if (this._addr_lsb[15:12] != 4'b_0000) pass_constrain = 0; //Reserved bits
214	if (this._addr_lsb[11:8] == 4'b0) pass_constrain = 0; //Ext Reg - 0 messes up Denali
215	}
216
217	if (this._type_req == PEC_PCI__TYPE_CFG1) {
218	if (this._addr_lsb[15:12] != 4'b_0000) pass_constrain = 0;
219	}
220	}
221	/// random constrain end
222	#else
223
224	if( this.randomize() != OK ) {
225	_env.Report.report(RTYP_TEST_ERROR,"PioCfgIOWrPEUStr::SetPacketParams - randomize failure \n" );
226	}
227	#endif
228
229	if (this._type_req == PEC_PCI__TYPE_CFG0){
230	if( firstCfgWr0 !== 1'b1 ){
231	firstCfgWr0ID = this._addr_lsb[31:16];
232	firstCfgWr0 = 1'b1;
233	}
234	this._addr_lsb[31:16] = firstCfgWr0ID ;
235	}
236
237
238	reqHdr [PEC_PCI__HDR] = {128{1'b_0}};
239	reqHdr [PEC_PCI__FMT] = this._format_req;
240	reqHdr [PEC_PCI__TYPE] = this._type_req;
241	reqHdr [PEC_PCI__TC] = this._tc;
242	reqHdr [PEC_PCI__TD] = this._td_req;
243	reqHdr [PEC_PCI__EP] = this._ep_req;
244	reqHdr [PEC_PCI__ATTR] = this._attr;
245	reqHdr [PEC_PCI__LEN] = this._len_req;
246	reqHdr [PEC_PCI__REQ_ID] = this._req_id;
247	reqHdr [PEC_PCI__TLP_TAG] = this._tag;
248	reqHdr [PEC_PCI__LAST_DWBE] = this._last_dwbe;
249	reqHdr [PEC_PCI__FIRST_DWBE] = this._first_dwbe;
250	reqHdr [PEC_PCI__ADDR32] = { this._addr_lsb[31:2], 2'b_00 };
251
252	cplHdr [PEC_PCI__HDR] = {128{1'b_0}};
253	cplHdr [PEC_PCI__FMT] = this._format_cpl;
254	cplHdr [PEC_PCI__TYPE] = this._type_cpl;
255	cplHdr [PEC_PCI__TC] = this._tc;
256	cplHdr [PEC_PCI__TD] = this._td_cpl;
257	cplHdr [PEC_PCI__EP] = this._ep_cpl;
258	cplHdr [PEC_PCI__ATTR] = this._attr;
259	cplHdr [PEC_PCI__LEN] = this._len_cpl;
260	cplHdr [PEC_PCI__CPL_ID] = this._cpl_id;
261	cplHdr [PEC_PCI__CPL_STATUS] = this._cpl_status;
262	cplHdr [PEC_PCI__BCM] = this._bcm;
263	cplHdr [PEC_PCI__BYTECOUNT] = this._byte_count;
264	cplHdr [PEC_PCI__CPL_REQ_ID] = this._req_id;
265	cplHdr [PEC_PCI__CPL_TAG] = this._tag;
266	cplHdr [PEC_PCI__LOWADDR] = this._lower_addr;
267
268	urHdr [PEC_PCI__HDR] = {128{1'b_0}};
269	urHdr [PEC_PCI__FMT] = this._format_cpl;
270	urHdr [PEC_PCI__TYPE] = this._type_cpl;
271	urHdr [PEC_PCI__TC] = this._tc;
272	urHdr [PEC_PCI__TD] = this._td_cpl;
273	urHdr [PEC_PCI__EP] = this._ep_cpl;
274	urHdr [PEC_PCI__ATTR] = this._attr;
275	urHdr [PEC_PCI__LEN] = this._len_cpl;
276	urHdr [PEC_PCI__CPL_ID] = this._cpl_id;
277	urHdr [PEC_PCI__CPL_STATUS] = PEC_PCI__CPL_STATUS_UR;
278	urHdr [PEC_PCI__BCM] = this._bcm;
279	urHdr [PEC_PCI__BYTECOUNT] = this._byte_count;
280	urHdr [PEC_PCI__CPL_REQ_ID] = this._req_id;
281	urHdr [PEC_PCI__CPL_TAG] = this._tag;
282	urHdr [PEC_PCI__LOWADDR] = this._lower_addr;
283
284	//Suppress all errors Denali reports due to random Cfg Write 0
285	if( this._type_req === PEC_PCI__TYPE_CFG0 ){
286	SetCfgWrtSuppressErrs();
287	}
288	}
289
290	task PioCfgIOWrPEUStr::SetCfgWrtSuppressErrs() {
291	this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_FATAL_CFG_DID_TXCPLQ );
292	this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_FATAL_CFG_DID_RXCPLQ );
293	this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_FATAL_CFG_VCARB1_1 );
294	this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_FATAL_CFG_TC_DELTC );
295
296	}
297
298	task PioCfgIOWrPEUStr::Execute() {
299
300	SetPacketParams();
301
302	this._env.driveILU(reqHdr, dataAddr, this._data);
303
304	this._env.expectPCIE(reqHdr, this._data);
305
306	if ( (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD1) \|\|
307	(this._cpl_status === PEC_PCI__CPL_STATUS_RSVD2) \|\|
308	(this._cpl_status === PEC_PCI__CPL_STATUS_RSVD3) \|\|
309	(this._cpl_status === PEC_PCI__CPL_STATUS_RSVD4)) {
310	this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlCplSt ); //Malformed Completion TLP - Reserved completion status (%u).
311	}
312
313	//
314	repeat( urandom_range( _env.Scenario.ilupeuPioCfgIOWrCplDelayMax, _env.Scenario.ilupeuPioCfgIOWrCplDelayMin)) @(posedge CLOCK);
315
316	this._env.drivePCIE(cplHdr, 0);
317
318
319	if ((this._cpl_status === PEC_PCI__CPL_STATUS_CA) \|\|
320	(this._cpl_status === PEC_PCI__CPL_STATUS_UR) \|\|
321	(this._cpl_status === PEC_PCI__CPL_STATUS_RSVD1) \|\|
322	(this._cpl_status === PEC_PCI__CPL_STATUS_RSVD2) \|\|
323	(this._cpl_status === PEC_PCI__CPL_STATUS_RSVD3) \|\|
324	(this._cpl_status === PEC_PCI__CPL_STATUS_RSVD4)) {
325
326	this._env.expectILU(urHdr, this._data);
327	mailbox_put(this._errQueue, e_ERR_oe_wuc);
328	mailbox_put(this._errQueue, cplHdr );
329	if ( (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD1) \|\|
330	(this._cpl_status === PEC_PCI__CPL_STATUS_RSVD2) \|\|
331	(this._cpl_status === PEC_PCI__CPL_STATUS_RSVD3) \|\|
332	(this._cpl_status === PEC_PCI__CPL_STATUS_RSVD4)) {
333	this._env.Pod.FNXPCIEEnableTrans.unSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlCplSt ); //Malformed Completion TLP - Reserved completion status (%u).
334	}
335	}
336
337	else if (this._cpl_status === PEC_PCI__CPL_STATUS_CRS) {
338
339	this._env.expectTimeoutCpl(reqHdr);
340	mailbox_put(this._errQueue, e_ERR_oe_crs);
341	mailbox_put(this._errQueue, cplHdr );
342	}
343
344	else if (this._ep_cpl === 1'b_1) {
345
346	cplHdr [PEC_PCI__EP] = 0;
347	this._env.drivePCIE(cplHdr, 0);
348	this._env.expectILU(cplHdr, 0);
349	cplHdr [PEC_PCI__EP] = 1;
350	mailbox_put(this._errQueue, e_ERR_ue_pp);
351	mailbox_put(this._errQueue, cplHdr);
352	}
353
354	else {
355
356	this._env.expectILU(cplHdr, this._data);
357	}
358
359
360	this._env.freePioTag(this._tag);
361	}