verif/env/ilu_peu/vera/N2str/ilupeuPioCfgIOWrStr.vr

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: ilupeuPioCfgIOWrStr.vr
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
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//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
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// ========== Copyright Header End ============================================
class PioCfgIOWrPEUStr extends PioBasePEUStr {


  // ******************************************************************
  // The Test Environment objects need to execute the strategy.
  // ******************************************************************
  protected PEUTestEnv              _env;
  protected integer                 _errQueue;


  // ******************************************************************
  // TLP Fields - These fields will be randomized using the parameters
  // in the following section, and obeying the constraints defined
  // within this class.
  // ******************************************************************
  protected         bit [1:0]       _format_req;
  protected         bit [1:0]       _format_cpl;
  protected         bit [4:0]       _type_req;
  protected         bit [4:0]       _type_cpl;

  protected         bit [2:0]       _tc;

  protected         bit             _td_req;
  protected         bit             _td_cpl;
  protected         bit             _ep_req;
  protected         bit             _ep_cpl;

  protected         bit [1:0]       _attr;
  protected         bit [9:0]       _len_req;
  protected         bit [9:0]       _len_cpl;
  protected         bit [15:0]      _req_id;
  protected         bit [7:0]       _tag;
  protected rand    bit [31:0]      _addr_lsb;

  protected         bit [3:0]       _last_dwbe;
  protected         bit [3:0]       _first_dwbe;

  protected         bit [15:0]      _cpl_id;
  protected         bit [2:0]       _cpl_status;
  protected         bit             _bcm;
  protected         bit [11:0]      _byte_count;
  protected         bit [6:0]       _lower_addr;
  protected         bit [63:0]      _data;

  protected     bit [PEC_PCI__HDR]      reqHdr;
  protected     bit [PEC_PCI__HDR]      cplHdr;
  protected     bit [PEC_PCI__HDR]      urHdr;

  protected     bit [7:0]               dataAddr;

  static        bit                 firstCfgWr0;
  static        bit [15:0]          firstCfgWr0ID;

  // ******************************************************************
  // The following constraint is used to generate the correct values
  // for the TLP.
  // ******************************************************************
  constraint generate_tlp {

    this._addr_lsb in {this._addr_lsb_min : this._addr_lsb_max};

    if (this._type_req == PEC_PCI__TYPE_CFG0){
      this._addr_lsb[15:12] == 4'b_0000;   //Reserved bits
      this._addr_lsb[11:8] in {1 : 15 };   //Ext Reg - 0 messes up Denali

    }

    if (this._type_req == PEC_PCI__TYPE_CFG1)
      this._addr_lsb[15:12] == 4'b_0000;
  }


  // ******************************************************************
  // Constructor
  // ******************************************************************
  public task new(PEUTestEnv a_env, (integer a_errQueue = 'bx));


  // ******************************************************************
  // Break this out as common class fullchip and ios can use
  // ******************************************************************
  public task SetPacketParams();
  task SetCfgWrtSuppressErrs();

  // ******************************************************************
  // Execute the strategy.  Drive a TLP into the ILU, and expect it out
  // of the PEU.
  // ******************************************************************
   public task Execute();
}


//-------------------------------------------------------------------
// Method Name:
// Description:
//-------------------------------------------------------------------
task PioCfgIOWrPEUStr::new(PEUTestEnv a_env, (integer a_errQueue = 'bx)) {


  super.new(a_env);
  this._env = a_env;
  this._errQueue = a_errQueue;
}


//-------------------------------------------------------------------
// Method Name:
// Description:
//-------------------------------------------------------------------
task PioCfgIOWrPEUStr::SetPacketParams() {

  integer pass_constrain = 0;
  this._env.allocWrTag(this._tag, dataAddr);


  this._format_req = PEC_PCI__FMT_DATA_3DW;
  this._format_cpl = PEC_PCI__FMT_NO_DATA_3DW;
  this._type_cpl   = PEC_PCI__TYPE_CPL;
  this._tc         = 3'b_000;
  this._td_req     = 1'b_0;
  this._ep_req     = 1'b_0;
  this._attr       = 2'b_00;
  this._len_req    = 10'h_001;
  this._len_cpl    = 10'h_000;
//  this._req_id     = 16'h_0000;
//Fullchip may need to set this in their tests
  this._req_id     = urandom_range(this._req_id_max, this._req_id_min);
  this._last_dwbe  = 4'b_0000;
  this._byte_count = 12'd_4;
  this._lower_addr = 7'b_000_0000;


  this._first_dwbe = urandom_range(this._first_dwbe_max, this._first_dwbe_min);
  this._cpl_id     = urandom_range(this._cpl_id_max, this._cpl_id_min);
  this._data[63:32] = urandom_range(this._data_max[63:32],   this._data_min[63:32]);
  this._data[31: 0] = urandom_range(this._data_max[31: 0],   this._data_min[31: 0]);


  randcase {
    this._type_req_prob_cfg0  : this._type_req = PEC_PCI__TYPE_CFG0;
    this._type_req_prob_cfg1  : this._type_req = PEC_PCI__TYPE_CFG1;
    this._type_req_prob_io    : this._type_req = PEC_PCI__TYPE_IO;
  }

  randcase {
    this._td_cpl_prob_false   : this._td_cpl = 1'b_0;
    this._td_cpl_prob_true    : this._td_cpl = 1'b_1;
  }

  randcase {
    this._ep_cpl_prob_false   : this._ep_cpl = 1'b_0;
    this._ep_cpl_prob_true    : this._ep_cpl = 1'b_1;
  }

  randcase {
    this._cpl_status_prob_sc    : this._cpl_status = PEC_PCI__CPL_STATUS_SC;
    this._cpl_status_prob_ur    : this._cpl_status = PEC_PCI__CPL_STATUS_UR;
    this._cpl_status_prob_crs   : this._cpl_status = PEC_PCI__CPL_STATUS_CRS;
    this._cpl_status_prob_ca    : this._cpl_status = PEC_PCI__CPL_STATUS_CA;
    this._cpl_status_prob_rsvd1 : this._cpl_status = PEC_PCI__CPL_STATUS_RSVD1;
    this._cpl_status_prob_rsvd2 : this._cpl_status = PEC_PCI__CPL_STATUS_RSVD2;
    this._cpl_status_prob_rsvd3 : this._cpl_status = PEC_PCI__CPL_STATUS_RSVD3;
    this._cpl_status_prob_rsvd4 : this._cpl_status = PEC_PCI__CPL_STATUS_RSVD4;
  }

  randcase {
    this._bcm_prob_false      : this._bcm = 1'b_0;
    this._bcm_prob_true       : this._bcm = 1'b_1;
  }

#ifdef N2_FC
  while (!pass_constrain)
  {
    this._addr_lsb = urandom_range(this._addr_lsb_max, this._addr_lsb_min);
    pass_constrain = 1;
    if (this._type_req == PEC_PCI__TYPE_CFG0){
      if (this._addr_lsb[15:12] != 4'b_0000) pass_constrain = 0;   //Reserved bits
      if (this._addr_lsb[11:8] == 4'b0) pass_constrain = 0;  //Ext Reg - 0 messes up Denali
    }

    if (this._type_req == PEC_PCI__TYPE_CFG1) {
      if (this._addr_lsb[15:12] != 4'b_0000) pass_constrain = 0;
    }
  }
/// random constrain end
#else

  if( this.randomize() != OK ) {
    _env.Report.report(RTYP_TEST_ERROR,"PioCfgIOWrPEUStr::SetPacketParams - randomize failure \n" );
  }
#endif

  if (this._type_req == PEC_PCI__TYPE_CFG0){
     if( firstCfgWr0 !== 1'b1 ){
        firstCfgWr0ID = this._addr_lsb[31:16];
        firstCfgWr0 = 1'b1;
     }
     this._addr_lsb[31:16] = firstCfgWr0ID ;
  }


  reqHdr [PEC_PCI__HDR]            = {128{1'b_0}};
  reqHdr [PEC_PCI__FMT]            = this._format_req;
  reqHdr [PEC_PCI__TYPE]           = this._type_req;
  reqHdr [PEC_PCI__TC]             = this._tc;
  reqHdr [PEC_PCI__TD]             = this._td_req;
  reqHdr [PEC_PCI__EP]             = this._ep_req;
  reqHdr [PEC_PCI__ATTR]           = this._attr;
  reqHdr [PEC_PCI__LEN]            = this._len_req;
  reqHdr [PEC_PCI__REQ_ID]         = this._req_id;
  reqHdr [PEC_PCI__TLP_TAG]        = this._tag;
  reqHdr [PEC_PCI__LAST_DWBE]      = this._last_dwbe;
  reqHdr [PEC_PCI__FIRST_DWBE]     = this._first_dwbe;
  reqHdr [PEC_PCI__ADDR32]         = { this._addr_lsb[31:2], 2'b_00 };

  cplHdr [PEC_PCI__HDR]            = {128{1'b_0}};
  cplHdr [PEC_PCI__FMT]            = this._format_cpl;
  cplHdr [PEC_PCI__TYPE]           = this._type_cpl;
  cplHdr [PEC_PCI__TC]             = this._tc;
  cplHdr [PEC_PCI__TD]             = this._td_cpl;
  cplHdr [PEC_PCI__EP]             = this._ep_cpl;
  cplHdr [PEC_PCI__ATTR]           = this._attr;
  cplHdr [PEC_PCI__LEN]            = this._len_cpl;
  cplHdr [PEC_PCI__CPL_ID]         = this._cpl_id;
  cplHdr [PEC_PCI__CPL_STATUS]     = this._cpl_status;
  cplHdr [PEC_PCI__BCM]            = this._bcm;
  cplHdr [PEC_PCI__BYTECOUNT]      = this._byte_count;
  cplHdr [PEC_PCI__CPL_REQ_ID]     = this._req_id;
  cplHdr [PEC_PCI__CPL_TAG]        = this._tag;
  cplHdr [PEC_PCI__LOWADDR]        = this._lower_addr;

  urHdr [PEC_PCI__HDR]             = {128{1'b_0}};
  urHdr [PEC_PCI__FMT]             = this._format_cpl;
  urHdr [PEC_PCI__TYPE]            = this._type_cpl;
  urHdr [PEC_PCI__TC]              = this._tc;
  urHdr [PEC_PCI__TD]              = this._td_cpl;
  urHdr [PEC_PCI__EP]              = this._ep_cpl;
  urHdr [PEC_PCI__ATTR]            = this._attr;
  urHdr [PEC_PCI__LEN]             = this._len_cpl;
  urHdr [PEC_PCI__CPL_ID]          = this._cpl_id;
  urHdr [PEC_PCI__CPL_STATUS]      = PEC_PCI__CPL_STATUS_UR;
  urHdr [PEC_PCI__BCM]             = this._bcm;
  urHdr [PEC_PCI__BYTECOUNT]       = this._byte_count;
  urHdr [PEC_PCI__CPL_REQ_ID]      = this._req_id;
  urHdr [PEC_PCI__CPL_TAG]         = this._tag;
  urHdr [PEC_PCI__LOWADDR]         = this._lower_addr;

  //Suppress all errors Denali reports due to random Cfg Write 0
  if( this._type_req === PEC_PCI__TYPE_CFG0 ){
     SetCfgWrtSuppressErrs();
  }
}

task PioCfgIOWrPEUStr::SetCfgWrtSuppressErrs() {
    this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_FATAL_CFG_DID_TXCPLQ );
    this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_FATAL_CFG_DID_RXCPLQ );
    this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_FATAL_CFG_VCARB1_1 );
    this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_FATAL_CFG_TC_DELTC );

}

task PioCfgIOWrPEUStr::Execute() {

  SetPacketParams();

  this._env.driveILU(reqHdr, dataAddr, this._data);

  this._env.expectPCIE(reqHdr, this._data);

  if ( (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD1) ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD2) ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD3) ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD4)) {
      this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlCplSt ); //Malformed Completion TLP - Reserved completion status (%u).
  }

  //
  repeat( urandom_range( _env.Scenario.ilupeuPioCfgIOWrCplDelayMax, _env.Scenario.ilupeuPioCfgIOWrCplDelayMin)) @(posedge CLOCK);

  this._env.drivePCIE(cplHdr, 0);


  if ((this._cpl_status === PEC_PCI__CPL_STATUS_CA)    ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_UR)    ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD1) ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD2) ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD3) ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD4)) {

    this._env.expectILU(urHdr, this._data);
    mailbox_put(this._errQueue, e_ERR_oe_wuc);
    mailbox_put(this._errQueue, cplHdr );
    if ( (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD1) ||
         (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD2) ||
         (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD3) ||
         (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD4)) {
      this._env.Pod.FNXPCIEEnableTrans.unSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlCplSt ); //Malformed Completion TLP - Reserved completion status (%u).
  }
  }

  else if (this._cpl_status === PEC_PCI__CPL_STATUS_CRS) {

    this._env.expectTimeoutCpl(reqHdr);
    mailbox_put(this._errQueue, e_ERR_oe_crs);
    mailbox_put(this._errQueue, cplHdr );
  }

  else if (this._ep_cpl === 1'b_1) {

    cplHdr [PEC_PCI__EP] = 0;
    this._env.drivePCIE(cplHdr, 0);
    this._env.expectILU(cplHdr, 0);
    cplHdr [PEC_PCI__EP] = 1;
    mailbox_put(this._errQueue, e_ERR_ue_pp);
    mailbox_put(this._errQueue, cplHdr);
  }

  else {

    this._env.expectILU(cplHdr, this._data);
  }


  this._env.freePioTag(this._tag);
}