projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: ilupeu_defines.vri | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | #ifndef INC_ILUPEU_DEFINES_VRI | |
| 36 | #define INC_ILUPEU_DEFINES_VRI | |
| 37 | ||
| 38 | ||
| 39 | #define ILUPEU_DL_INACTIVE 3'b001 | |
| 40 | #define ILUPEU_DL_INIT 3'b010 | |
| 41 | #define ILUPEU_DL_ACTIVE 3'b100 | |
| 42 | ||
| 43 | #define ILUPEU_LINK_DOWN 1'b0 | |
| 44 | #define ILUPEU_LINK_UP 1'b1 | |
| 45 | ||
| 46 | #define ILUPEU_FC_IDLE 2'b00 | |
| 47 | #define ILUPEU_FC_INIT1 2'b01 | |
| 48 | #define ILUPEU_FC_INIT2 2'b11 | |
| 49 | #define ILUPEU_FC_INIT_DONE 2'b10 | |
| 50 | ||
| 51 | #define ILUPEU_LANE_REVERSED 1'b1 | |
| 52 | #define ILUPEU_LANE_NOT_REVERSED 1'b0 | |
| 53 | ||
| 54 | ||
| 55 | #define ILUPEU_LINK_WIDTH_X1 4'b0000 | |
| 56 | #define ILUPEU_LINK_WIDTH_X2 4'b0001 | |
| 57 | #define ILUPEU_LINK_WIDTH_X4 4'b0011 | |
| 58 | #define ILUPEU_LINK_WIDTH_X8 4'b0111 | |
| 59 | ||
| 60 | //PEU definitions from xmlh_ltssm.v | |
| 61 | #define ILUPEU_LTSSM_DETECT_QUIET 5'h00 | |
| 62 | #define ILUPEU_LTSSM_DETECT_ACT 5'h01 | |
| 63 | #define ILUPEU_LTSSM_POLL_ACTIVE 5'h02 | |
| 64 | #define ILUPEU_LTSSM_POLL_COMPLIANCE 5'h03 | |
| 65 | #define ILUPEU_LTSSM_POLL_CONFIG 5'h04 | |
| 66 | #define ILUPEU_LTSSM_PRE_DETECT_QUIET 5'h05 | |
| 67 | #define ILUPEU_LTSSM_DETECT_WAIT 5'h06 | |
| 68 | #define ILUPEU_LTSSM_CFG_LINKWD_START 5'h07 | |
| 69 | #define ILUPEU_LTSSM_CFG_LINKWD_ACEPT 5'h08 | |
| 70 | #define ILUPEU_LTSSM_CFG_LANENUM_WAIT 5'h09 | |
| 71 | #define ILUPEU_LTSSM_CFG_LANENUM_ACEPT 5'h0A | |
| 72 | #define ILUPEU_LTSSM_CFG_COMPLETE 5'h0B | |
| 73 | #define ILUPEU_LTSSM_CFG_IDLE 5'h0C | |
| 74 | #define ILUPEU_LTSSM_RCVRY_RCVRLOCK 5'h0D | |
| 75 | #define ILUPEU_LTSSM_RCVRY_RCVRCFG 5'h0E | |
| 76 | #define ILUPEU_LTSSM_RCVRY_IDLE 5'h0F | |
| 77 | #define ILUPEU_LTSSM_L0 5'h10 | |
| 78 | #define ILUPEU_LTSSM_L0S 5'h11 | |
| 79 | #define ILUPEU_LTSSM_L123_SEND_EIDLE 5'h12 | |
| 80 | #define ILUPEU_LTSSM_L1_IDLE 5'h13 | |
| 81 | #define ILUPEU_LTSSM_L2_IDLE 5'h14 | |
| 82 | #define ILUPEU_LTSSM_L2_WAKE 5'h15 | |
| 83 | #define ILUPEU_LTSSM_DISABLED_ENTRY 5'h16 | |
| 84 | #define ILUPEU_LTSSM_DISABLED_IDLE 5'h17 | |
| 85 | #define ILUPEU_LTSSM_DISABLED 5'h18 | |
| 86 | #define ILUPEU_LTSSM_LPBK_ENTRY 5'h19 | |
| 87 | #define ILUPEU_LTSSM_LPBK_ACTIVE 5'h1A | |
| 88 | #define ILUPEU_LTSSM_LPBK_EXIT 5'h1B | |
| 89 | #define ILUPEU_LTSSM_LPBK_EXIT_TIMEOUT 5'h1C | |
| 90 | #define ILUPEU_LTSSM_HOT_RESET_ENTRY 5'h1D | |
| 91 | #define ILUPEU_LTSSM_HOT_RESET 5'h1F | |
| 92 | ||
| 93 | //#define ILUPEU_LTSSM_DETECT_QUIET 5'h00 | |
| 94 | //#define ILUPEU_LTSSM_DETECT_ACTIVE 5'h01 | |
| 95 | //#define ILUPEU_LTSSM_DETECT_CHARGE 5'h02 | |
| 96 | //#define ILUPEU_LTSSM_POLLING_QUIET 5'h03 | |
| 97 | //#define ILUPEU_LTSSM_POLLING_ACTIVE 5'h04 | |
| 98 | //#define ILUPEU_LTSSM_POLLING_COMPL 5'h05 | |
| 99 | //#define ILUPEU_LTSSM_POLLING_CONFIG 5'h06 | |
| 100 | //#define ILUPEU_LTSSM_POLLING_SPEED 5'h07 | |
| 101 | //#define ILUPEU_LTSSM_CONFIG_RCVRCFG 5'h08 | |
| 102 | //#define ILUPEU_LTSSM_CONFIG_IDLE 5'h09 | |
| 103 | //#define ILUPEU_LTSSM_RECOVERY_RCVRLOCK 5'h0a | |
| 104 | //#define ILUPEU_LTSSM_RECOVERY_RCVRCFG 5'h0b | |
| 105 | //#define ILUPEU_LTSSM_RECOVERY_IDLE 5'h0c | |
| 106 | //#define ILUPEU_LTSSM_L0 5'h0d | |
| 107 | //#define ILUPEU_LTSSM_L0S_RXE 5'h0e | |
| 108 | //#define ILUPEU_LTSSM_L0S_RXI 5'h0f | |
| 109 | ||
| 110 | //Standard CSR width | |
| 111 | #define ILUPEU_CSR_WIDTH 64 | |
| 112 | #define ILUPEU_FAST_LINK_TRAIN_TO 15000 | |
| 113 | #define ILUPEU_DEFAULT_LINK_TRAIN_TO 10000000 | |
| 114 | ||
| 115 | //Default Retry Credits | |
| 116 | #define ILUPEU_DEFAULT_RETRY_CREDITS 16'h1580 | |
| 117 | ||
| 118 | //Defines for Ingress/Egress | |
| 119 | #define ILUPEU_INGRESS_TRANS 1 | |
| 120 | #define ILUPEU_EGRESS_TRANS 0 | |
| 121 | ||
| 122 | //Defines for Strategy Encodings | |
| 123 | #define ILUPEU_TLP_STRAT_ENC 0 | |
| 124 | #define ILUPEU_DLLP_FC_STRAT_ENC 1 | |
| 125 | #define ILUPEU_DLLP_PM_STRAT_ENC 2 | |
| 126 | ||
| 127 | ||
| 128 | //review - Need a new define file for testbench once its working | |
| 129 | ||
| 130 | // | |
| 131 | // File name : LPUXtrComponentsDefine.vri | |
| 132 | // | |
| 133 | // Description: All LPU Transactor #defines live in this file. | |
| 134 | // | |
| 135 | // | |
| 136 | // Revision History : | |
| 137 | // 04/10/02 filliate : Original File Created | |
| 138 | // 08/28/02 Modified for LPU | |
| 139 | // | |
| 140 | // ************************************************************************* | |
| 141 | ||
| 142 | ||
| 143 | ||
| 144 | #define ILUPEU_TRUE 1 | |
| 145 | #define ILUPEU_FALSE 0 | |
| 146 | ||
| 147 | // TLP Field Acquisition Defines | |
| 148 | #define ILUPEU_TLP_TYPE_QUAD_LOC 0 | |
| 149 | #define ILUPEU_TLP_TYPE_BITS 30:24 | |
| 150 | ||
| 151 | #define ILUPEU_TLP_TC_QUAD_LOC 0 | |
| 152 | #define ILUPEU_TLP_TC_BITS 22:20 | |
| 153 | ||
| 154 | #define ILUPEU_TLP_DATASIZE_QUAD_LOC 0 | |
| 155 | #define ILUPEU_TLP_DATASIZE_BITS 9:0 | |
| 156 | ||
| 157 | ||
| 158 | ||
| 159 | // TLP Type Encodings | |
| 160 | #define ILUPEU_TLP_FMT_TYPE_MRD32 7'b_00_00000 | |
| 161 | #define ILUPEU_TLP_FMT_TYPE_MRD64 7'b_01_00000 | |
| 162 | #define ILUPEU_TLP_FMT_TYPE_MRDLK32 7'b_00_00001 | |
| 163 | #define ILUPEU_TLP_FMT_TYPE_MRDLK64 7'b_01_00001 | |
| 164 | #define ILUPEU_TLP_FMT_TYPE_MWR32 7'b_10_00000 | |
| 165 | #define ILUPEU_TLP_FMT_TYPE_MWR64 7'b_11_00000 | |
| 166 | #define ILUPEU_TLP_FMT_TYPE_IORD 7'b_00_00010 | |
| 167 | #define ILUPEU_TLP_FMT_TYPE_IOWR 7'b_10_00010 | |
| 168 | #define ILUPEU_TLP_FMT_TYPE_CFGRD0 7'b_00_00100 | |
| 169 | #define ILUPEU_TLP_FMT_TYPE_CFGWR0 7'b_10_00100 | |
| 170 | #define ILUPEU_TLP_FMT_TYPE_CFGRD1 7'b_00_00101 | |
| 171 | #define ILUPEU_TLP_FMT_TYPE_CFGWR1 7'b_10_00101 | |
| 172 | #define ILUPEU_TLP_FMT_TYPE_MSG0 7'b_01_10000 | |
| 173 | #define ILUPEU_TLP_FMT_TYPE_MSG1 7'b_01_10001 | |
| 174 | #define ILUPEU_TLP_FMT_TYPE_MSG2 7'b_01_10010 | |
| 175 | #define ILUPEU_TLP_FMT_TYPE_MSG3 7'b_01_10011 | |
| 176 | #define ILUPEU_TLP_FMT_TYPE_MSG4 7'b_01_10100 | |
| 177 | #define ILUPEU_TLP_FMT_TYPE_MSG5 7'b_01_10101 | |
| 178 | #define ILUPEU_TLP_FMT_TYPE_MSG6 7'b_01_10110 | |
| 179 | #define ILUPEU_TLP_FMT_TYPE_MSG7 7'b_01_10111 | |
| 180 | #define ILUPEU_TLP_FMT_TYPE_MSGD0 7'b_11_10000 | |
| 181 | #define ILUPEU_TLP_FMT_TYPE_MSGD1 7'b_11_10001 | |
| 182 | #define ILUPEU_TLP_FMT_TYPE_MSGD2 7'b_11_10010 | |
| 183 | #define ILUPEU_TLP_FMT_TYPE_MSGD3 7'b_11_10011 | |
| 184 | #define ILUPEU_TLP_FMT_TYPE_MSGD4 7'b_11_10100 | |
| 185 | #define ILUPEU_TLP_FMT_TYPE_MSGD5 7'b_11_10101 | |
| 186 | #define ILUPEU_TLP_FMT_TYPE_MSGD6 7'b_11_10110 | |
| 187 | #define ILUPEU_TLP_FMT_TYPE_MSGD7 7'b_11_10111 | |
| 188 | #define ILUPEU_TLP_FMT_TYPE_CPL 7'b_00_01010 | |
| 189 | #define ILUPEU_TLP_FMT_TYPE_CPLD 7'b_10_01010 | |
| 190 | #define ILUPEU_TLP_FMT_TYPE_CPLLK 7'b_00_01011 | |
| 191 | #define ILUPEU_TLP_FMT_TYPE_CPLDLK 7'b_10_01011 | |
| 192 | ||
| 193 | ||
| 194 | ||
| 195 | // TLP Commands | |
| 196 | #define ILUPEU_TLP_CMD_IDLE 3'b_000 | |
| 197 | #define ILUPEU_TLP_CMD_ABORT_EOP 3'b_001 | |
| 198 | #define ILUPEU_TLP_CMD_DATA 3'b_010 | |
| 199 | #define ILUPEU_TLP_CMD_DATA_EOP 3'b_011 | |
| 200 | #define ILUPEU_TLP_CMD_RESERVED_A 3'b_100 | |
| 201 | #define ILUPEU_TLP_CMD_RESERVED_B 3'b_101 | |
| 202 | #define ILUPEU_TLP_CMD_SOP_DATA 3'b_110 | |
| 203 | #define ILUPEU_TLP_CMD_SOP_DATA_EOP 3'b_111 | |
| 204 | ||
| 205 | ||
| 206 | ||
| 207 | // TLP Status | |
| 208 | #define ILUPEU_TLP_STATUS_NO_ERROR 4'b_0000 | |
| 209 | #define ILUPEU_TLP_STATUS_RECEIVE_ERROR 4'b_0001 | |
| 210 | #define ILUPEU_TLP_STATUS_CRC_ERROR 4'b_0010 | |
| 211 | #define ILUPEU_TLP_STATUS_EDB_INDICATION 4'b_0011 | |
| 212 | #define ILUPEU_TLP_STATUS_MISSING_EOP_ERROR 4'b_0100 | |
| 213 | #define ILUPEU_TLP_STATUS_PACKET_LENGTH_ERROR 4'b_0101 | |
| 214 | #define ILUPEU_TLP_STATUS_DATA_PARITY_ERROR 4'b_0110 | |
| 215 | ||
| 216 | ||
| 217 | ||
| 218 | // FC Type | |
| 219 | #define ILUPEU_FC_TYPE_IDLE 3'b_000 | |
| 220 | #define ILUPEU_FC_TYPE_INIT_COMPLETION 3'b_001 | |
| 221 | #define ILUPEU_FC_TYPE_INIT_NON_POSTED 3'b_010 | |
| 222 | #define ILUPEU_FC_TYPE_INIT_POSTED 3'b_011 | |
| 223 | #define ILUPEU_FC_TYPE_RESERVED 3'b_100 | |
| 224 | #define ILUPEU_FC_TYPE_UPDATE_COMPLETION 3'b_101 | |
| 225 | #define ILUPEU_FC_TYPE_UPDATE_NON_POSTED 3'b_110 | |
| 226 | #define ILUPEU_FC_TYPE_UPDATE_POSTED 3'b_111 | |
| 227 | #define ILUPEU_FC_HEADER_CREDIT_WIDTH 8 | |
| 228 | #define ILUPEU_FC_DATA_CREDIT_WIDTH 12 | |
| 229 | ||
| 230 | ||
| 231 | //DL Link State | |
| 232 | //review - Defined above | |
| 233 | //#define ILUPEU_LS_DL_INACTIVE 3'b001 | |
| 234 | //#define ILUPEU_LS_DL_INIT 3'b010 | |
| 235 | //#define ILUPEU_LS_DL_ACTIVE 3'b100 | |
| 236 | ||
| 237 | //Defines for 4DW 128 bit header | |
| 238 | #define ILUPEU_TLP_HDR_WIDTH 128 | |
| 239 | #define ILUPEU_TLP_HDR_DW0_BITS 127:96 | |
| 240 | #define ILUPEU_TLP_HDR_DW1_BITS 95:64 | |
| 241 | #define ILUPEU_TLP_HDR_DW2_BITS 63:32 | |
| 242 | #define ILUPEU_TLP_HDR_DW3_BITS 31:0 | |
| 243 | #define ILUPEU_TLP_HDR_BITS 127:0 | |
| 244 | #define ILUPEU_TLP_HDR_FMT_BITS 126:125 | |
| 245 | #define ILUPEU_TLP_HDR_FMT_DATA_BITS 126:126 | |
| 246 | #define ILUPEU_TLP_HDR_FMT_4DW_BITS 125:125 | |
| 247 | #define ILUPEU_TLP_HDR_TYPE_BITS 124:120 | |
| 248 | #define ILUPEU_TLP_HDR_FMT_TYPE_BITS 126:120 | |
| 249 | #define ILUPEU_TLP_HDR_TC_BITS 118:116 | |
| 250 | #define ILUPEU_TLP_HDR_TD_BITS 111:111 | |
| 251 | #define ILUPEU_TLP_HDR_EP_BITS 110:110 | |
| 252 | #define ILUPEU_TLP_HDR_ATTR_BITS 109:108 | |
| 253 | #define ILUPEU_TLP_HDR_RO_BITS 109:109 | |
| 254 | #define ILUPEU_TLP_HDR_SNOOP_BITS 108:108 | |
| 255 | #define ILUPEU_TLP_HDR_LEN_BITS 105:96 | |
| 256 | #define ILUPEU_TLP_HDR_REQ_ID_BITS 95:80 | |
| 257 | #define ILUPEU_TLP_HDR_REQ_BUS_NUM_BITS 95:88 | |
| 258 | #define ILUPEU_TLP_HDR_REQ_DEV_NUM_BITS 87:83 | |
| 259 | #define ILUPEU_TLP_HDR_REQ_FUNC_NUM_BITS 82:80 | |
| 260 | #define ILUPEU_TLP_HDR_TAG_BITS 79:72 | |
| 261 | #define ILUPEU_TLP_HDR_LAST_DWBE_BITS 71:68 | |
| 262 | #define ILUPEU_TLP_HDR_FIRST_DWBE_BITS 67:64 | |
| 263 | #define ILUPEU_TLP_HDR_MSG_CODE_BITS 71:64 | |
| 264 | #define ILUPEU_TLP_HDR_ADDR64_UPPER_BITS 63:32 | |
| 265 | #define ILUPEU_TLP_HDR_ADDR64_LOWER_BITS 31:2 | |
| 266 | #define ILUPEU_TLP_HDR_ADDR32_BITS 63:34 | |
| 267 | #define ILUPEU_TLP_HDR_CPL_ID_BITS 95:80 | |
| 268 | #define ILUPEU_TLP_HDR_CPL_CPL_BUS_NUM_BITS 95:88 | |
| 269 | #define ILUPEU_TLP_HDR_CPL_CPL_DEV_NUM_BITS 87:83 | |
| 270 | #define ILUPEU_TLP_HDR_CPL_CPL_FUNC_NUM_BITS 82:80 | |
| 271 | #define ILUPEU_TLP_HDR_CPL_STATUS_BITS 79:77 | |
| 272 | #define ILUPEU_TLP_HDR_CPL_BCM_BITS 76:76 | |
| 273 | #define ILUPEU_TLP_HDR_CPL_BYTECOUNT_BITS 75:64 | |
| 274 | #define ILUPEU_TLP_HDR_CPL_REQ_ID_BITS 63:48 | |
| 275 | #define ILUPEU_TLP_HDR_CPL_REQ_BUS_NUM_BITS 63:56 | |
| 276 | #define ILUPEU_TLP_HDR_CPL_REQ_DEV_NUM_BITS 55:51 | |
| 277 | #define ILUPEU_TLP_HDR_CPL_REQ_FUNC_NUM_BITS 50:48 | |
| 278 | #define ILUPEU_TLP_HDR_CPL_TAG_BITS 47:40 | |
| 279 | #define ILUPEU_TLP_HDR_CPL_LOWADDR_BITS 38:32 | |
| 280 | #define ILUPEU_TLP_HDR_CFG_BUS_NUM_BITS 63:56 | |
| 281 | #define ILUPEU_TLP_HDR_CFG_DEV_NUM_BITS 55:51 | |
| 282 | #define ILUPEU_TLP_HDR_CFG_FUNC_NUM_BITS 50:48 | |
| 283 | #define ILUPEU_TLP_HDR_CFG_EXT_REG_NUM_BITS 43:40 | |
| 284 | #define ILUPEU_TLP_HDR_CFG_REG_NUM_BITS 39:34 | |
| 285 | #define ILUPEU_TLP_HDR_MSG_DW3_BITS 63:32 | |
| 286 | #define ILUPEU_TLP_HDR_MSG_DW4_BITS 31:0 | |
| 287 | #define ILUPEU_TLP_HDR_MSG_VNDR_CPL_BUS_NUM_BITS 63:56 | |
| 288 | #define ILUPEU_TLP_HDR_MSG_VNDR_CPL_DEV_NUM_BITS 55:51 | |
| 289 | #define ILUPEU_TLP_HDR_MSG_VNDR_CPL_FUNC_NUM_BITS 50:48 | |
| 290 | #define ILUPEU_TLP_HDR_MSG_VNDR_VNDR_ID 47:32 | |
| 291 | ||
| 292 | ||
| 293 | ||
| 294 | ||
| 295 | ||
| 296 | #define ILUPEU_DW_WIDTH 32 | |
| 297 | #define ILUPEU_DW_BITS 31:0 | |
| 298 | #define ILUPEU_DW_BYTE_0_BITS 31:24 | |
| 299 | #define ILUPEU_DW_BYTE_1_BITS 23:16 | |
| 300 | #define ILUPEU_DW_BYTE_2_BITS 15:8 | |
| 301 | #define ILUPEU_DW_BYTE_3_BITS 7:0 | |
| 302 | ||
| 303 | ||
| 304 | #define ILUPEU_TLP_HDR_FMT_DATA_3DW 2'b_10 | |
| 305 | #define ILUPEU_TLP_HDR_FMT_DATA_4DW 2'b_11 | |
| 306 | #define ILUPEU_TLP_HDR_FMT_NO_DATA_3DW 2'b_00 | |
| 307 | #define ILUPEU_TLP_HDR_FMT_NO_DATA_4DW 2'b_01 | |
| 308 | ||
| 309 | ||
| 310 | ||
| 311 | #define ILUPEU_TLP_TYPE_MEM 5'b00000 | |
| 312 | #define ILUPEU_TLP_TYPE_MEM_LK 5'b00001 | |
| 313 | #define ILUPEU_TLP_TYPE_CPL 5'b01010 | |
| 314 | #define ILUPEU_TLP_TYPE_CPL_LK 5'b01011 | |
| 315 | #define ILUPEU_TLP_TYPE_CFG0 5'b00100 | |
| 316 | #define ILUPEU_TLP_TYPE_CFG1 5'b00101 | |
| 317 | #define ILUPEU_TLP_TYPE_IO 5'b00010 | |
| 318 | #define ILUPEU_TLP_TYPE_MSG 5'b10000 | |
| 319 | #define ILUPEU_TLP_TYPE_MSG_RC_MASK 5'b00111 | |
| 320 | #define ILUPEU_TLP_TYPE_VALID_00 32'h00000c37 | |
| 321 | #define ILUPEU_TLP_TYPE_VALID_01 32'h00ff0003 | |
| 322 | #define ILUPEU_TLP_TYPE_VALID_10 32'h00000c35 | |
| 323 | #define ILUPEU_TLP_TYPE_VALID_11 32'h00ff0001 | |
| 324 | ||
| 325 | ||
| 326 | #define ILUPEU_TLP_CPL_STATUS_SC 3'b_000 | |
| 327 | #define ILUPEU_TLP_CPL_STATUS_UR 3'b_001 | |
| 328 | #define ILUPEU_TLP_CPL_STATUS_CRS 3'b_010 | |
| 329 | #define ILUPEU_TLP_CPL_STATUS_CA 3'b_100 | |
| 330 | #define ILUPEU_TLP_CPL_STATUS_TIMEOUT 3'b_111 | |
| 331 | #define ILUPEU_TLP_CPL_STATUS_RSVD1 3'b_011 | |
| 332 | #define ILUPEU_TLP_CPL_STATUS_RSVD2 3'b_101 | |
| 333 | #define ILUPEU_TLP_CPL_STATUS_RSVD3 3'b_110 | |
| 334 | #define ILUPEU_TLP_CPL_STATUS_RSVD4 3'b_111 | |
| 335 | ||
| 336 | //L2T defines | |
| 337 | #define ILUPEU_L2T_ITP_CMD_WIDTH 3 | |
| 338 | #define ILUPEU_L2T_ITP_CMD_BITS 2:0 | |
| 339 | #define ILUPEU_L2T_ITP_CMD_EOP_VLD_BITS 0:0 | |
| 340 | #define ILUPEU_L2T_ITP_CMD_DATA_VLD_BITS 1:1 | |
| 341 | #define ILUPEU_L2T_ITP_CMD_SOP_VLD_BITS 2:2 | |
| 342 | #define ILUPEU_L2T_ITP_POS_WIDTH 4 | |
| 343 | #define ILUPEU_L2T_ITP_POS_SOP_WIDTH 2 | |
| 344 | #define ILUPEU_L2T_ITP_POS_EOP_WIDTH 2 | |
| 345 | #define ILUPEU_L2T_ITP_POS_BITS 3:0 | |
| 346 | #define ILUPEU_L2T_ITP_POS_SOP_BITS 3:2 | |
| 347 | #define ILUPEU_L2T_ITP_POS_EOP_BITS 1:0 | |
| 348 | #define ILUPEU_L2T_ITP_POS_SOP_POS0 2'b00 | |
| 349 | #define ILUPEU_L2T_ITP_POS_SOP_POS1 2'b01 | |
| 350 | #define ILUPEU_L2T_ITP_POS_SOP_POS2 2'b10 | |
| 351 | #define ILUPEU_L2T_ITP_POS_SOP_POS3 2'b11 | |
| 352 | #define ILUPEU_L2T_ITP_POS_EOP_POS0 2'b00 | |
| 353 | #define ILUPEU_L2T_ITP_POS_EOP_POS1 2'b01 | |
| 354 | #define ILUPEU_L2T_ITP_POS_EOP_POS2 2'b10 | |
| 355 | #define ILUPEU_L2T_ITP_POS_EOP_POS3 2'b11 | |
| 356 | ||
| 357 | //T2L defines | |
| 358 | #define ILUPEU_T2L_LNK_CAP_WIDTH 32 | |
| 359 | #define ILUPEU_T2L_LNK_CAP_MAX_LNK_SPD_WIDTH 4 | |
| 360 | #define ILUPEU_T2L_LNK_CAP_MAX_LNK_SPD_BITS 3:0 | |
| 361 | #define ILUPEU_T2L_LNK_CAP_MAX_LNK_WDTH_WIDTH 6 | |
| 362 | #define ILUPEU_T2L_LNK_CAP_MAX_LNK_WDTH_BITS 9:4 | |
| 363 | ||
| 364 | #define ILUPEU_T2L_LNK_CAP_ASPM_WIDTH 2 | |
| 365 | #define ILUPEU_T2L_LNK_CAP_ASPM_BITS 11:10 | |
| 366 | #define ILUPEU_T2L_LNK_CAP_LOS_EXIT_LAT_WIDTH 3 | |
| 367 | #define ILUPEU_T2L_LNK_CAP_LOS_EXIT_LAT_BITS 14:12 | |
| 368 | #define ILUPEU_T2L_LNK_CAP_L1_EXIT_LAT_WIDTH 3 | |
| 369 | #define ILUPEU_T2L_LNK_CAP_L1_EXIT_LAT_BITS 17:15 | |
| 370 | #define ILUPEU_T2L_LNK_CAP_PORT_NMBR_WIDTH 8 | |
| 371 | #define ILUPEU_T2L_LNK_CAP_PORT_NMBR_BITS 31:24 | |
| 372 | ||
| 373 | #define ILUPEU_T2L_LNK_CTRL_WIDTH 16 | |
| 374 | #define ILUPEU_T2L_LNK_CTRL_ASPM_WIDTH 2 | |
| 375 | #define ILUPEU_T2L_LNK_CTRL_ASPM_BITS 1:0 | |
| 376 | #define ILUPEU_T2L_LNK_CTRL_RCB_WIDTH 1 | |
| 377 | #define ILUPEU_T2L_LNK_CTRL_RCB_BITS 3:3 | |
| 378 | #define ILUPEU_T2L_LNK_CTRL_LNK_DISABL_WIDTH 1 | |
| 379 | #define ILUPEU_T2L_LNK_CTRL_LNK_DISABL_BITS 4:4 | |
| 380 | #define ILUPEU_T2L_LNK_CTRL_RETRAIN_LNK_WIDTH 1 | |
| 381 | #define ILUPEU_T2L_LNK_CTRL_RETRAIN_LNK_BITS 5:5 | |
| 382 | #define ILUPEU_T2L_LNK_CTRL_CMN_CLK_CFG_WIDTH 1 | |
| 383 | #define ILUPEU_T2L_LNK_CTRL_CMN_CLK_CFG_BITS 6:6 | |
| 384 | #define ILUPEU_T2L_LNK_CTRL_EXTND_SYNC_WIDTH 1 | |
| 385 | #define ILUPEU_T2L_LNK_CTRL_EXTND_SYNC_BITS 7:7 | |
| 386 | ||
| 387 | #define ILUPEU_T2L_LNK_CFG_WIDTH 8 | |
| 388 | #define ILUPEU_T2L_LNK_CFG_PORT_CFG_WIDTH 1 | |
| 389 | #define ILUPEU_T2L_LNK_CFG_PORT_CFG_BITS 0:0 | |
| 390 | #define ILUPEU_T2L_LNK_CFG_SLOT_CLK_CFG_WIDTH 1 | |
| 391 | #define ILUPEU_T2L_LNK_CFG_SLOT_CLK_CFG_BITS 1:1 | |
| 392 | ||
| 393 | ||
| 394 | // PM DLLP Type | |
| 395 | #define ILUPEU_PM_DLLP_TYPE_WIDTH 3 | |
| 396 | #define ILUPEU_PM_DLLP_TYPE_IDLE 3'b_000 | |
| 397 | #define ILUPEU_PM_DLLP_TYPE_ENTER_L1 3'b_001 | |
| 398 | #define ILUPEU_PM_DLLP_TYPE_ENTER_L23 3'b_010 | |
| 399 | #define ILUPEU_PM_DLLP_TYPE_ACTIVE_STATE_REQ_L1 3'b_011 | |
| 400 | #define ILUPEU_PM_DLLP_TYPE_REQ_ACK 3'b_100 | |
| 401 | ||
| 402 | ||
| 403 | #endif | |
| 404 | ||
| 405 |