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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / niu / txc_sat / vera / include / txc_drr_chk_if.vri
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86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: txc_drr_chk_if.vri
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#ifdef NEPTUNE
36#define OUTPUT_EDGE PHOLD
37#define INPUT_EDGE PSAMPLE #-1
38#define OUTPUT_SKEW #1
39#endif
40
41#ifdef N2_IOS
42#include "top_defines.vrh"
43#endif
44
45#include "neptune_defines.vri"
46#define TXC_PATH NIU_DUV_PATH.rtx.niu_txc
47#define TXC1_PATH NIU_DUV_PATH.rtx.niu_txc.niu_txc_packetEngine0.niu_txc_drr_engine.niu_txc_drr_arbiter
48
49
50interface txc_drr_if
51{
52 input clk CLOCK verilog_node TXC_PATH.clk";
53
54 input pio_txc_sel INPUT_EDGE verilog_node TXC_PATH.pio_txc_sel";
55
56 input [19:0] pio_clients_addr INPUT_EDGE verilog_node TXC_PATH.pio_clients_addr";
57
58 input [63:0] pio_clients_wdata INPUT_EDGE verilog_node TXC_PATH.pio_clients_wdata";
59
60 input pio_clients_rd INPUT_EDGE verilog_node TXC_PATH.pio_clients_rd";
61
62 input dmc_txc_dma0_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma0_active";
63 input dmc_txc_dma0_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma0_eoflist";
64 input dmc_txc_dma0_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma0_error";
65 input dmc_txc_dma0_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma0_cacheready";
66
67 input dmc_txc_dma1_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma1_active";
68 input dmc_txc_dma1_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma1_eoflist";
69 input dmc_txc_dma1_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma1_error";
70 input dmc_txc_dma1_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma1_cacheready";
71
72 input dmc_txc_dma2_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma2_active";
73 input dmc_txc_dma2_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma2_eoflist";
74 input dmc_txc_dma2_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma2_error";
75 input dmc_txc_dma2_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma2_cacheready";
76
77 input dmc_txc_dma3_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma3_active";
78 input dmc_txc_dma3_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma3_eoflist";
79 input dmc_txc_dma3_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma3_error";
80 input dmc_txc_dma3_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma3_cacheready";
81
82
83 input dmc_txc_dma4_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma4_active";
84 input dmc_txc_dma4_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma4_eoflist";
85 input dmc_txc_dma4_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma4_error";
86 input dmc_txc_dma4_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma4_cacheready";
87
88
89 input dmc_txc_dma5_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma5_active";
90 input dmc_txc_dma5_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma5_eoflist";
91 input dmc_txc_dma5_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma5_error";
92 input dmc_txc_dma5_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma5_cacheready";
93
94
95 input dmc_txc_dma6_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma6_active";
96 input dmc_txc_dma6_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma6_eoflist";
97 input dmc_txc_dma6_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma6_error";
98 input dmc_txc_dma6_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma6_cacheready";
99
100
101 input dmc_txc_dma7_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma7_active";
102 input dmc_txc_dma7_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma7_eoflist";
103 input dmc_txc_dma7_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma7_error";
104 input dmc_txc_dma7_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma7_cacheready";
105
106
107 input dmc_txc_dma8_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma8_active";
108 input dmc_txc_dma8_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma8_eoflist";
109 input dmc_txc_dma8_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma8_error";
110 input dmc_txc_dma8_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma8_cacheready";
111
112
113 input dmc_txc_dma9_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma9_active";
114 input dmc_txc_dma9_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma9_eoflist";
115 input dmc_txc_dma9_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma9_error";
116 input dmc_txc_dma9_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma9_cacheready";
117
118
119 input dmc_txc_dma10_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma10_active";
120 input dmc_txc_dma10_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma10_eoflist";
121 input dmc_txc_dma10_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma10_error";
122 input dmc_txc_dma10_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma10_cacheready";
123
124
125 input dmc_txc_dma11_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma11_active";
126 input dmc_txc_dma11_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma11_eoflist";
127 input dmc_txc_dma11_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma11_error";
128 input dmc_txc_dma11_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma11_cacheready";
129
130 input dmc_txc_dma12_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma12_active";
131 input dmc_txc_dma12_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma12_eoflist";
132 input dmc_txc_dma12_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma12_error";
133 input dmc_txc_dma12_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma12_cacheready";
134
135
136 input dmc_txc_dma13_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma13_active";
137 input dmc_txc_dma13_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma13_eoflist";
138 input dmc_txc_dma13_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma13_error";
139 input dmc_txc_dma13_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma13_cacheready";
140
141
142 input dmc_txc_dma14_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma14_active";
143 input dmc_txc_dma14_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma14_eoflist";
144 input dmc_txc_dma14_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma14_error";
145 input dmc_txc_dma14_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma14_cacheready";
146
147
148 input dmc_txc_dma15_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma15_active";
149 input dmc_txc_dma15_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma15_eoflist";
150 input dmc_txc_dma15_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma15_error";
151 input dmc_txc_dma15_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma15_cacheready";
152
153
154 input dmc_txc_dma16_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma16_active";
155 input dmc_txc_dma16_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma16_eoflist";
156 input dmc_txc_dma16_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma16_error";
157 input dmc_txc_dma16_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma16_cacheready";
158
159
160 input dmc_txc_dma17_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma17_active";
161 input dmc_txc_dma17_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma17_eoflist";
162 input dmc_txc_dma17_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma17_error";
163 input dmc_txc_dma17_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma17_cacheready";
164
165
166 input dmc_txc_dma18_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma18_active";
167 input dmc_txc_dma18_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma18_eoflist";
168 input dmc_txc_dma18_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma18_error";
169 input dmc_txc_dma18_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma18_cacheready";
170
171
172 input dmc_txc_dma19_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma19_active";
173 input dmc_txc_dma19_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma19_eoflist";
174 input dmc_txc_dma19_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma19_error";
175 input dmc_txc_dma19_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma19_cacheready";
176
177
178 input dmc_txc_dma20_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma20_active";
179 input dmc_txc_dma20_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma20_eoflist";
180 input dmc_txc_dma20_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma20_error";
181 input dmc_txc_dma20_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma20_cacheready";
182
183 input dmc_txc_dma21_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma21_active";
184 input dmc_txc_dma21_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma21_eoflist";
185 input dmc_txc_dma21_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma21_error";
186 input dmc_txc_dma21_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma21_cacheready";
187
188
189 input dmc_txc_dma22_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma22_active";
190 input dmc_txc_dma22_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma22_eoflist";
191 input dmc_txc_dma22_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma22_error";
192 input dmc_txc_dma22_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma22_cacheready";
193
194
195 input dmc_txc_dma23_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma23_active";
196 input dmc_txc_dma23_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma23_eoflist";
197 input dmc_txc_dma23_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma23_error";
198 input dmc_txc_dma23_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma23_cacheready";
199
200
201 input dmc_txc_dma24_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma24_active";
202 input dmc_txc_dma24_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma24_eoflist";
203 input dmc_txc_dma24_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma24_error";
204 input dmc_txc_dma24_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma24_cacheready";
205
206
207 input dmc_txc_dma25_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma25_active";
208 input dmc_txc_dma25_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma25_eoflist";
209 input dmc_txc_dma25_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma25_error";
210 input dmc_txc_dma25_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma25_cacheready";
211
212
213 input dmc_txc_dma26_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma26_active";
214 input dmc_txc_dma26_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma26_eoflist";
215 input dmc_txc_dma26_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma26_error";
216 input dmc_txc_dma26_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma26_cacheready";
217
218
219 input dmc_txc_dma27_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma27_active";
220 input dmc_txc_dma27_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma27_eoflist";
221 input dmc_txc_dma27_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma27_error";
222 input dmc_txc_dma27_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma27_cacheready";
223
224
225 input dmc_txc_dma28_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma28_active";
226 input dmc_txc_dma28_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma28_eoflist";
227 input dmc_txc_dma28_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma28_error";
228 input dmc_txc_dma28_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma28_cacheready";
229
230
231 input dmc_txc_dma29_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma29_active";
232 input dmc_txc_dma29_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma29_eoflist";
233 input dmc_txc_dma29_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma29_error";
234 input dmc_txc_dma29_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma29_cacheready";
235
236 input dmc_txc_dma30_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma30_active";
237 input dmc_txc_dma30_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma30_eoflist";
238 input dmc_txc_dma30_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma30_error";
239 input dmc_txc_dma30_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma30_cacheready";
240
241
242 input dmc_txc_dma31_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma31_active";
243 input dmc_txc_dma31_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma31_eoflist";
244 input dmc_txc_dma31_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma31_error";
245 input dmc_txc_dma31_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma31_cacheready";
246
247 input txc_mac_ack0 INPUT_EDGE verilog_node TXC_PATH.txc_mac_ack0";
248 input txc_mac_tag0 INPUT_EDGE verilog_node TXC_PATH.txc_mac_tag0";
249
250 #ifndef RXC_SAT
251 input latch_activedma INPUT_EDGE verilog_node TXC1_PATH.latchActiveDMA";
252 #endif
253 input AddCreditToContext INPUT_EDGE verilog_node TXC1_PATH.AddCreditToContext";
254
255 input txc_pio_ack INPUT_EDGE verilog_node TXC_PATH.txc_pio_ack";
256
257 }
258
259
260port txc_pio_port {
261
262 clk;
263 pio_sel;
264 pio_addr;
265 pio_wdata;
266 pio_rd;
267 pio_ack;
268}
269
270port txc_alldmas_port {
271
272 clk;
273 dma0_active;
274 dma0_eoflist;
275 dma0_error;
276 dma0_cacheready;
277
278 dma1_active;
279 dma1_eoflist;
280 dma1_error;
281 dma1_cacheready;
282
283 dma2_active;
284 dma2_eoflist;
285 dma2_error;
286 dma2_cacheready;
287
288 dma3_active;
289 dma3_eoflist;
290 dma3_error;
291 dma3_cacheready;
292
293 dma4_active;
294 dma4_eoflist;
295 dma4_error;
296 dma4_cacheready;
297
298 dma5_active;
299 dma5_eoflist;
300 dma5_error;
301 dma5_cacheready;
302
303 dma6_active;
304 dma6_eoflist;
305 dma6_error;
306 dma6_cacheready;
307
308 dma7_active;
309 dma7_eoflist;
310 dma7_error;
311 dma7_cacheready;
312
313 dma8_active;
314 dma8_eoflist;
315 dma8_error;
316 dma8_cacheready;
317
318 dma9_active;
319 dma9_eoflist;
320 dma9_error;
321 dma9_cacheready;
322
323 dma10_active;
324 dma10_eoflist;
325 dma10_error;
326 dma10_cacheready;
327
328 dma11_active;
329 dma11_eoflist;
330 dma11_error;
331 dma11_cacheready;
332
333 dma12_active;
334 dma12_eoflist;
335 dma12_error;
336 dma12_cacheready;
337
338 dma13_active;
339 dma13_eoflist;
340 dma13_error;
341 dma13_cacheready;
342
343 dma14_active;
344 dma14_eoflist;
345 dma14_error;
346 dma14_cacheready;
347
348 dma15_active;
349 dma15_eoflist;
350 dma15_error;
351 dma15_cacheready;
352
353 dma16_active;
354 dma16_eoflist;
355 dma16_error;
356 dma16_cacheready;
357
358 dma17_active;
359 dma17_eoflist;
360 dma17_error;
361 dma17_cacheready;
362
363 dma18_active;
364 dma18_eoflist;
365 dma18_error;
366 dma18_cacheready;
367
368 dma19_active;
369 dma19_eoflist;
370 dma19_error;
371 dma19_cacheready;
372
373 dma20_active;
374 dma20_eoflist;
375 dma20_error;
376 dma20_cacheready;
377
378 dma21_active;
379 dma21_eoflist;
380 dma21_error;
381 dma21_cacheready;
382
383 dma22_active;
384 dma22_eoflist;
385 dma22_error;
386 dma22_cacheready;
387
388 dma23_active;
389 dma23_eoflist;
390 dma23_error;
391 dma23_cacheready;
392
393 dma24_active;
394 dma24_eoflist;
395 dma24_error;
396 dma24_cacheready;
397
398 dma25_active;
399 dma25_eoflist;
400 dma25_error;
401 dma25_cacheready;
402
403 dma26_active;
404 dma26_eoflist;
405 dma26_error;
406 dma26_cacheready;
407
408 dma27_active;
409 dma27_eoflist;
410 dma27_error;
411 dma27_cacheready;
412
413 dma28_active;
414 dma28_eoflist;
415 dma28_error;
416 dma28_cacheready;
417
418 dma29_active;
419 dma29_eoflist;
420 dma29_error;
421 dma29_cacheready;
422
423 dma30_active;
424 dma30_eoflist;
425 dma30_error;
426 dma30_cacheready;
427
428 dma31_active;
429 dma31_eoflist;
430 dma31_error;
431 dma31_cacheready;
432
433 latch_dma;
434 add_credit;
435}
436
437port txc_mac0_port {
438
439 clk;
440 port0_ack;
441 port0_tag;
442}
443
444bind txc_mac0_port txc_mac0_bind
445{
446 clk txc_drr_if.clk;
447 port0_ack txc_drr_if.txc_mac_ack0;
448 port0_tag txc_drr_if.txc_mac_tag0;
449}
450
451
452bind txc_pio_port txc_pio_port_bind
453{
454 clk txc_drr_if.clk;
455 pio_sel txc_drr_if.pio_txc_sel;
456 pio_addr txc_drr_if.pio_clients_addr;
457 pio_wdata txc_drr_if.pio_clients_wdata;
458 pio_rd txc_drr_if.pio_clients_rd;
459 pio_ack txc_drr_if.txc_pio_ack;
460}
461
462bind txc_alldmas_port txc_alldmas_bind
463{
464 clk txc_drr_if.clk;
465 dma0_active txc_drr_if.dmc_txc_dma0_active;
466 dma0_eoflist txc_drr_if.dmc_txc_dma0_eoflist;
467 dma0_error txc_drr_if.dmc_txc_dma0_error;
468 dma0_cacheready txc_drr_if.dmc_txc_dma0_cacheready;
469
470 dma1_active txc_drr_if.dmc_txc_dma1_active;
471 dma1_eoflist txc_drr_if.dmc_txc_dma1_eoflist;
472 dma1_error txc_drr_if.dmc_txc_dma1_error;
473 dma1_cacheready txc_drr_if.dmc_txc_dma1_cacheready;
474
475 dma2_active txc_drr_if.dmc_txc_dma2_active;
476 dma2_eoflist txc_drr_if.dmc_txc_dma2_eoflist;
477 dma2_error txc_drr_if.dmc_txc_dma2_error;
478 dma2_cacheready txc_drr_if.dmc_txc_dma2_cacheready;
479
480 dma3_active txc_drr_if.dmc_txc_dma3_active;
481 dma3_eoflist txc_drr_if.dmc_txc_dma3_eoflist;
482 dma3_error txc_drr_if.dmc_txc_dma3_error;
483 dma3_cacheready txc_drr_if.dmc_txc_dma3_cacheready;
484
485 dma4_active txc_drr_if.dmc_txc_dma4_active;
486 dma4_eoflist txc_drr_if.dmc_txc_dma4_eoflist;
487 dma4_error txc_drr_if.dmc_txc_dma4_error;
488 dma4_cacheready txc_drr_if.dmc_txc_dma4_cacheready;
489
490 dma5_active txc_drr_if.dmc_txc_dma5_active;
491 dma5_eoflist txc_drr_if.dmc_txc_dma5_eoflist;
492 dma5_error txc_drr_if.dmc_txc_dma5_error;
493 dma5_cacheready txc_drr_if.dmc_txc_dma5_cacheready;
494
495 dma6_active txc_drr_if.dmc_txc_dma6_active;
496 dma6_eoflist txc_drr_if.dmc_txc_dma6_eoflist;
497 dma6_error txc_drr_if.dmc_txc_dma6_error;
498 dma6_cacheready txc_drr_if.dmc_txc_dma6_cacheready;
499
500 dma7_active txc_drr_if.dmc_txc_dma7_active;
501 dma7_eoflist txc_drr_if.dmc_txc_dma7_eoflist;
502 dma7_error txc_drr_if.dmc_txc_dma7_error;
503 dma7_cacheready txc_drr_if.dmc_txc_dma7_cacheready;
504
505 dma8_active txc_drr_if.dmc_txc_dma8_active;
506 dma8_eoflist txc_drr_if.dmc_txc_dma8_eoflist;
507 dma8_error txc_drr_if.dmc_txc_dma8_error;
508 dma8_cacheready txc_drr_if.dmc_txc_dma8_cacheready;
509
510 dma9_active txc_drr_if.dmc_txc_dma9_active;
511 dma9_eoflist txc_drr_if.dmc_txc_dma9_eoflist;
512 dma9_error txc_drr_if.dmc_txc_dma9_error;
513 dma9_cacheready txc_drr_if.dmc_txc_dma9_cacheready;
514
515 dma10_active txc_drr_if.dmc_txc_dma10_active;
516 dma10_eoflist txc_drr_if.dmc_txc_dma10_eoflist;
517 dma10_error txc_drr_if.dmc_txc_dma10_error;
518 dma10_cacheready txc_drr_if.dmc_txc_dma10_cacheready;
519
520 dma11_active txc_drr_if.dmc_txc_dma11_active;
521 dma11_eoflist txc_drr_if.dmc_txc_dma11_eoflist;
522 dma11_error txc_drr_if.dmc_txc_dma11_error;
523 dma11_cacheready txc_drr_if.dmc_txc_dma11_cacheready;
524
525 dma12_active txc_drr_if.dmc_txc_dma12_active;
526 dma12_eoflist txc_drr_if.dmc_txc_dma12_eoflist;
527 dma12_error txc_drr_if.dmc_txc_dma12_error;
528 dma12_cacheready txc_drr_if.dmc_txc_dma12_cacheready;
529
530 dma13_active txc_drr_if.dmc_txc_dma13_active;
531 dma13_eoflist txc_drr_if.dmc_txc_dma13_eoflist;
532 dma13_error txc_drr_if.dmc_txc_dma13_error;
533 dma13_cacheready txc_drr_if.dmc_txc_dma13_cacheready;
534
535 dma14_active txc_drr_if.dmc_txc_dma14_active;
536 dma14_eoflist txc_drr_if.dmc_txc_dma14_eoflist;
537 dma14_error txc_drr_if.dmc_txc_dma14_error;
538 dma14_cacheready txc_drr_if.dmc_txc_dma14_cacheready;
539
540 dma15_active txc_drr_if.dmc_txc_dma15_active;
541 dma15_eoflist txc_drr_if.dmc_txc_dma15_eoflist;
542 dma15_error txc_drr_if.dmc_txc_dma15_error;
543 dma15_cacheready txc_drr_if.dmc_txc_dma15_cacheready;
544
545 dma16_active txc_drr_if.dmc_txc_dma16_active;
546 dma16_eoflist txc_drr_if.dmc_txc_dma16_eoflist;
547 dma16_error txc_drr_if.dmc_txc_dma16_error;
548 dma16_cacheready txc_drr_if.dmc_txc_dma16_cacheready;
549
550 dma17_active txc_drr_if.dmc_txc_dma17_active;
551 dma17_eoflist txc_drr_if.dmc_txc_dma17_eoflist;
552 dma17_error txc_drr_if.dmc_txc_dma17_error;
553 dma17_cacheready txc_drr_if.dmc_txc_dma17_cacheready;
554
555 dma18_active txc_drr_if.dmc_txc_dma18_active;
556 dma18_eoflist txc_drr_if.dmc_txc_dma18_eoflist;
557 dma18_error txc_drr_if.dmc_txc_dma18_error;
558 dma18_cacheready txc_drr_if.dmc_txc_dma18_cacheready;
559
560 dma19_active txc_drr_if.dmc_txc_dma19_active;
561 dma19_eoflist txc_drr_if.dmc_txc_dma19_eoflist;
562 dma19_error txc_drr_if.dmc_txc_dma19_error;
563 dma19_cacheready txc_drr_if.dmc_txc_dma19_cacheready;
564
565 dma20_active txc_drr_if.dmc_txc_dma20_active;
566 dma20_eoflist txc_drr_if.dmc_txc_dma20_eoflist;
567 dma20_error txc_drr_if.dmc_txc_dma20_error;
568 dma20_cacheready txc_drr_if.dmc_txc_dma20_cacheready;
569
570 dma21_active txc_drr_if.dmc_txc_dma21_active;
571 dma21_eoflist txc_drr_if.dmc_txc_dma21_eoflist;
572 dma21_error txc_drr_if.dmc_txc_dma21_error;
573 dma21_cacheready txc_drr_if.dmc_txc_dma21_cacheready;
574
575 dma22_active txc_drr_if.dmc_txc_dma22_active;
576 dma22_eoflist txc_drr_if.dmc_txc_dma22_eoflist;
577 dma22_error txc_drr_if.dmc_txc_dma22_error;
578 dma22_cacheready txc_drr_if.dmc_txc_dma22_cacheready;
579
580 dma23_active txc_drr_if.dmc_txc_dma23_active;
581 dma23_eoflist txc_drr_if.dmc_txc_dma23_eoflist;
582 dma23_error txc_drr_if.dmc_txc_dma23_error;
583 dma23_cacheready txc_drr_if.dmc_txc_dma23_cacheready;
584
585 dma24_active txc_drr_if.dmc_txc_dma24_active;
586 dma24_eoflist txc_drr_if.dmc_txc_dma24_eoflist;
587 dma24_error txc_drr_if.dmc_txc_dma24_error;
588 dma24_cacheready txc_drr_if.dmc_txc_dma24_cacheready;
589
590 dma25_active txc_drr_if.dmc_txc_dma25_active;
591 dma25_eoflist txc_drr_if.dmc_txc_dma25_eoflist;
592 dma25_error txc_drr_if.dmc_txc_dma25_error;
593 dma25_cacheready txc_drr_if.dmc_txc_dma25_cacheready;
594
595 dma26_active txc_drr_if.dmc_txc_dma26_active;
596 dma26_eoflist txc_drr_if.dmc_txc_dma26_eoflist;
597 dma26_error txc_drr_if.dmc_txc_dma26_error;
598 dma26_cacheready txc_drr_if.dmc_txc_dma26_cacheready;
599
600 dma27_active txc_drr_if.dmc_txc_dma27_active;
601 dma27_eoflist txc_drr_if.dmc_txc_dma27_eoflist;
602 dma27_error txc_drr_if.dmc_txc_dma27_error;
603 dma27_cacheready txc_drr_if.dmc_txc_dma27_cacheready;
604
605 dma28_active txc_drr_if.dmc_txc_dma28_active;
606 dma28_eoflist txc_drr_if.dmc_txc_dma28_eoflist;
607 dma28_error txc_drr_if.dmc_txc_dma28_error;
608 dma28_cacheready txc_drr_if.dmc_txc_dma28_cacheready;
609
610 dma29_active txc_drr_if.dmc_txc_dma29_active;
611 dma29_eoflist txc_drr_if.dmc_txc_dma29_eoflist;
612 dma29_error txc_drr_if.dmc_txc_dma29_error;
613 dma29_cacheready txc_drr_if.dmc_txc_dma29_cacheready;
614
615 dma30_active txc_drr_if.dmc_txc_dma30_active;
616 dma30_eoflist txc_drr_if.dmc_txc_dma30_eoflist;
617 dma30_error txc_drr_if.dmc_txc_dma30_error;
618 dma30_cacheready txc_drr_if.dmc_txc_dma30_cacheready;
619
620 dma31_active txc_drr_if.dmc_txc_dma31_active;
621 dma31_eoflist txc_drr_if.dmc_txc_dma31_eoflist;
622 dma31_error txc_drr_if.dmc_txc_dma31_error;
623 dma31_cacheready txc_drr_if.dmc_txc_dma31_cacheready;
624
625
626 latch_dma txc_drr_if.latch_activedma;
627 add_credit txc_drr_if.AddCreditToContext;
628}
Full OpenSPARC design & verification tarball including full HDL.