verif/env/niu/txc_sat/vera/include/txc_drr_chk_if.vri

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: txc_drr_chk_if.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// have any questions.
//
// ========== Copyright Header End ============================================
#ifdef NEPTUNE
#define OUTPUT_EDGE PHOLD
#define INPUT_EDGE PSAMPLE #-1
#define OUTPUT_SKEW #1
#endif

#ifdef N2_IOS
#include "top_defines.vrh"
#endif

#include "neptune_defines.vri"
#define TXC_PATH NIU_DUV_PATH.rtx.niu_txc
#define TXC1_PATH NIU_DUV_PATH.rtx.niu_txc.niu_txc_packetEngine0.niu_txc_drr_engine.niu_txc_drr_arbiter


interface txc_drr_if
{
    input  clk CLOCK verilog_node TXC_PATH.clk";

    input  pio_txc_sel INPUT_EDGE verilog_node TXC_PATH.pio_txc_sel";

    input  [19:0] pio_clients_addr INPUT_EDGE verilog_node TXC_PATH.pio_clients_addr";

    input  [63:0] pio_clients_wdata INPUT_EDGE verilog_node TXC_PATH.pio_clients_wdata";

    input  pio_clients_rd INPUT_EDGE verilog_node TXC_PATH.pio_clients_rd";

    input  dmc_txc_dma0_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma0_active";
    input  dmc_txc_dma0_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma0_eoflist";
    input  dmc_txc_dma0_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma0_error";
    input  dmc_txc_dma0_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma0_cacheready";

    input  dmc_txc_dma1_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma1_active";
    input  dmc_txc_dma1_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma1_eoflist";
    input  dmc_txc_dma1_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma1_error";
    input  dmc_txc_dma1_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma1_cacheready";

    input  dmc_txc_dma2_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma2_active";
    input  dmc_txc_dma2_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma2_eoflist";
    input  dmc_txc_dma2_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma2_error";
    input  dmc_txc_dma2_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma2_cacheready";

    input  dmc_txc_dma3_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma3_active";
    input  dmc_txc_dma3_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma3_eoflist";
    input  dmc_txc_dma3_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma3_error";
    input  dmc_txc_dma3_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma3_cacheready";


    input  dmc_txc_dma4_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma4_active";
    input  dmc_txc_dma4_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma4_eoflist";
    input  dmc_txc_dma4_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma4_error";
    input  dmc_txc_dma4_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma4_cacheready";


    input  dmc_txc_dma5_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma5_active";
    input  dmc_txc_dma5_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma5_eoflist";
    input  dmc_txc_dma5_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma5_error";
    input  dmc_txc_dma5_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma5_cacheready";


    input  dmc_txc_dma6_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma6_active";
    input  dmc_txc_dma6_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma6_eoflist";
    input  dmc_txc_dma6_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma6_error";
    input  dmc_txc_dma6_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma6_cacheready";


    input  dmc_txc_dma7_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma7_active";
    input  dmc_txc_dma7_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma7_eoflist";
    input  dmc_txc_dma7_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma7_error";
    input  dmc_txc_dma7_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma7_cacheready";


    input  dmc_txc_dma8_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma8_active";
    input  dmc_txc_dma8_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma8_eoflist";
    input  dmc_txc_dma8_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma8_error";
    input  dmc_txc_dma8_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma8_cacheready";


    input  dmc_txc_dma9_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma9_active";
    input  dmc_txc_dma9_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma9_eoflist";
    input  dmc_txc_dma9_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma9_error";
    input  dmc_txc_dma9_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma9_cacheready";


    input  dmc_txc_dma10_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma10_active";
    input  dmc_txc_dma10_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma10_eoflist";
    input  dmc_txc_dma10_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma10_error";
    input  dmc_txc_dma10_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma10_cacheready";


    input  dmc_txc_dma11_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma11_active";
    input  dmc_txc_dma11_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma11_eoflist";
    input  dmc_txc_dma11_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma11_error";
    input  dmc_txc_dma11_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma11_cacheready";

    input  dmc_txc_dma12_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma12_active";
    input  dmc_txc_dma12_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma12_eoflist";
 input  dmc_txc_dma12_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma12_error";
 input  dmc_txc_dma12_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma12_cacheready";


 input  dmc_txc_dma13_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma13_active";
 input  dmc_txc_dma13_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma13_eoflist";
 input  dmc_txc_dma13_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma13_error";
 input  dmc_txc_dma13_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma13_cacheready";


 input  dmc_txc_dma14_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma14_active";
 input  dmc_txc_dma14_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma14_eoflist";
 input  dmc_txc_dma14_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma14_error";
 input  dmc_txc_dma14_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma14_cacheready";


 input  dmc_txc_dma15_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma15_active";
 input  dmc_txc_dma15_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma15_eoflist";
 input  dmc_txc_dma15_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma15_error";
 input  dmc_txc_dma15_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma15_cacheready";


 input  dmc_txc_dma16_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma16_active";
 input  dmc_txc_dma16_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma16_eoflist";
 input  dmc_txc_dma16_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma16_error";
 input  dmc_txc_dma16_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma16_cacheready";


 input  dmc_txc_dma17_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma17_active";
 input  dmc_txc_dma17_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma17_eoflist";
 input  dmc_txc_dma17_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma17_error";
 input  dmc_txc_dma17_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma17_cacheready";


 input  dmc_txc_dma18_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma18_active";
 input  dmc_txc_dma18_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma18_eoflist";
 input  dmc_txc_dma18_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma18_error";
 input  dmc_txc_dma18_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma18_cacheready";


 input  dmc_txc_dma19_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma19_active";
 input  dmc_txc_dma19_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma19_eoflist";
 input  dmc_txc_dma19_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma19_error";
 input  dmc_txc_dma19_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma19_cacheready";


 input  dmc_txc_dma20_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma20_active";
 input  dmc_txc_dma20_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma20_eoflist";
 input  dmc_txc_dma20_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma20_error";
 input  dmc_txc_dma20_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma20_cacheready";

  input  dmc_txc_dma21_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma21_active";
 input  dmc_txc_dma21_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma21_eoflist";
 input  dmc_txc_dma21_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma21_error";
 input  dmc_txc_dma21_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma21_cacheready";


 input  dmc_txc_dma22_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma22_active";
 input  dmc_txc_dma22_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma22_eoflist";
 input  dmc_txc_dma22_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma22_error";
 input  dmc_txc_dma22_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma22_cacheready";


 input  dmc_txc_dma23_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma23_active";
 input  dmc_txc_dma23_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma23_eoflist";
 input  dmc_txc_dma23_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma23_error";
 input  dmc_txc_dma23_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma23_cacheready";


 input  dmc_txc_dma24_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma24_active";
 input  dmc_txc_dma24_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma24_eoflist";
 input  dmc_txc_dma24_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma24_error";
 input  dmc_txc_dma24_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma24_cacheready";


 input  dmc_txc_dma25_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma25_active";
 input  dmc_txc_dma25_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma25_eoflist";
 input  dmc_txc_dma25_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma25_error";
 input  dmc_txc_dma25_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma25_cacheready";


 input  dmc_txc_dma26_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma26_active";
 input  dmc_txc_dma26_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma26_eoflist";
 input  dmc_txc_dma26_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma26_error";
 input  dmc_txc_dma26_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma26_cacheready";


 input  dmc_txc_dma27_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma27_active";
 input  dmc_txc_dma27_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma27_eoflist";
 input  dmc_txc_dma27_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma27_error";
 input  dmc_txc_dma27_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma27_cacheready";


 input  dmc_txc_dma28_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma28_active";
 input  dmc_txc_dma28_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma28_eoflist";
 input  dmc_txc_dma28_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma28_error";
 input  dmc_txc_dma28_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma28_cacheready";


 input  dmc_txc_dma29_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma29_active";
 input  dmc_txc_dma29_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma29_eoflist";
 input  dmc_txc_dma29_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma29_error";
 input  dmc_txc_dma29_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma29_cacheready";

 input  dmc_txc_dma30_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma30_active";
 input  dmc_txc_dma30_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma30_eoflist";
 input  dmc_txc_dma30_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma30_error";
 input  dmc_txc_dma30_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma30_cacheready";


 input  dmc_txc_dma31_active INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma31_active";
 input  dmc_txc_dma31_eoflist INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma31_eoflist";
 input  dmc_txc_dma31_error INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma31_error";
 input  dmc_txc_dma31_cacheready INPUT_EDGE verilog_node TXC_PATH.dmc_txc_dma31_cacheready";

    input  txc_mac_ack0 INPUT_EDGE verilog_node TXC_PATH.txc_mac_ack0";
    input  txc_mac_tag0 INPUT_EDGE verilog_node TXC_PATH.txc_mac_tag0";

  #ifndef RXC_SAT
    input  latch_activedma INPUT_EDGE verilog_node TXC1_PATH.latchActiveDMA";
  #endif
    input  AddCreditToContext INPUT_EDGE verilog_node TXC1_PATH.AddCreditToContext";

    input txc_pio_ack INPUT_EDGE verilog_node TXC_PATH.txc_pio_ack";

  }


port txc_pio_port {

        clk;
        pio_sel;
        pio_addr;
        pio_wdata;
        pio_rd;
        pio_ack;
}

port txc_alldmas_port {

        clk;
        dma0_active;
        dma0_eoflist;
        dma0_error;
        dma0_cacheready;

        dma1_active;
        dma1_eoflist;
        dma1_error;
        dma1_cacheready;

        dma2_active;
        dma2_eoflist;
        dma2_error;
        dma2_cacheready;

        dma3_active;
        dma3_eoflist;
        dma3_error;
        dma3_cacheready;

        dma4_active;
        dma4_eoflist;
        dma4_error;
        dma4_cacheready;

        dma5_active;
        dma5_eoflist;
        dma5_error;
        dma5_cacheready;

        dma6_active;
        dma6_eoflist;
        dma6_error;
        dma6_cacheready;

        dma7_active;
        dma7_eoflist;
        dma7_error;
        dma7_cacheready;

        dma8_active;
        dma8_eoflist;
        dma8_error;
        dma8_cacheready;

        dma9_active;
        dma9_eoflist;
        dma9_error;
        dma9_cacheready;

        dma10_active;
        dma10_eoflist;
        dma10_error;
        dma10_cacheready;

        dma11_active;
        dma11_eoflist;
        dma11_error;
        dma11_cacheready;

        dma12_active;
        dma12_eoflist;
        dma12_error;
        dma12_cacheready;

        dma13_active;
        dma13_eoflist;
        dma13_error;
        dma13_cacheready;

                dma14_active;
        dma14_eoflist;
        dma14_error;
        dma14_cacheready;

        dma15_active;
        dma15_eoflist;
        dma15_error;
        dma15_cacheready;

        dma16_active;
        dma16_eoflist;
        dma16_error;
        dma16_cacheready;

        dma17_active;
        dma17_eoflist;
        dma17_error;
        dma17_cacheready;

        dma18_active;
        dma18_eoflist;
        dma18_error;
        dma18_cacheready;

        dma19_active;
        dma19_eoflist;
        dma19_error;
        dma19_cacheready;

        dma20_active;
        dma20_eoflist;
        dma20_error;
        dma20_cacheready;

        dma21_active;
        dma21_eoflist;
        dma21_error;
        dma21_cacheready;

        dma22_active;
        dma22_eoflist;
        dma22_error;
        dma22_cacheready;

        dma23_active;
        dma23_eoflist;
        dma23_error;
        dma23_cacheready;

        dma24_active;
        dma24_eoflist;
        dma24_error;
        dma24_cacheready;

               dma25_active;
        dma25_eoflist;
        dma25_error;
        dma25_cacheready;

        dma26_active;
        dma26_eoflist;
        dma26_error;
        dma26_cacheready;

        dma27_active;
        dma27_eoflist;
        dma27_error;
        dma27_cacheready;

        dma28_active;
        dma28_eoflist;
        dma28_error;
        dma28_cacheready;

        dma29_active;
        dma29_eoflist;
        dma29_error;
        dma29_cacheready;

        dma30_active;
        dma30_eoflist;
        dma30_error;
        dma30_cacheready;

        dma31_active;
        dma31_eoflist;
        dma31_error;
        dma31_cacheready;

        latch_dma;
        add_credit;
}

port txc_mac0_port {

       clk;
       port0_ack;
       port0_tag;
}

bind txc_mac0_port txc_mac0_bind
{
       clk       txc_drr_if.clk;
       port0_ack txc_drr_if.txc_mac_ack0;
       port0_tag txc_drr_if.txc_mac_tag0;
}


bind txc_pio_port txc_pio_port_bind
{
       clk           txc_drr_if.clk;
       pio_sel       txc_drr_if.pio_txc_sel;
       pio_addr      txc_drr_if.pio_clients_addr;
       pio_wdata     txc_drr_if.pio_clients_wdata;
       pio_rd        txc_drr_if.pio_clients_rd;
       pio_ack       txc_drr_if.txc_pio_ack;
}

bind txc_alldmas_port txc_alldmas_bind
{
       clk              txc_drr_if.clk;
       dma0_active      txc_drr_if.dmc_txc_dma0_active;
       dma0_eoflist     txc_drr_if.dmc_txc_dma0_eoflist;
       dma0_error       txc_drr_if.dmc_txc_dma0_error;
       dma0_cacheready  txc_drr_if.dmc_txc_dma0_cacheready;

       dma1_active      txc_drr_if.dmc_txc_dma1_active;
       dma1_eoflist     txc_drr_if.dmc_txc_dma1_eoflist;
       dma1_error       txc_drr_if.dmc_txc_dma1_error;
       dma1_cacheready  txc_drr_if.dmc_txc_dma1_cacheready;

       dma2_active      txc_drr_if.dmc_txc_dma2_active;
       dma2_eoflist     txc_drr_if.dmc_txc_dma2_eoflist;
       dma2_error       txc_drr_if.dmc_txc_dma2_error;
       dma2_cacheready  txc_drr_if.dmc_txc_dma2_cacheready;

              dma3_active      txc_drr_if.dmc_txc_dma3_active;
       dma3_eoflist     txc_drr_if.dmc_txc_dma3_eoflist;
       dma3_error       txc_drr_if.dmc_txc_dma3_error;
       dma3_cacheready  txc_drr_if.dmc_txc_dma3_cacheready;

       dma4_active      txc_drr_if.dmc_txc_dma4_active;
       dma4_eoflist     txc_drr_if.dmc_txc_dma4_eoflist;
       dma4_error       txc_drr_if.dmc_txc_dma4_error;
       dma4_cacheready  txc_drr_if.dmc_txc_dma4_cacheready;

       dma5_active      txc_drr_if.dmc_txc_dma5_active;
       dma5_eoflist     txc_drr_if.dmc_txc_dma5_eoflist;
       dma5_error       txc_drr_if.dmc_txc_dma5_error;
       dma5_cacheready  txc_drr_if.dmc_txc_dma5_cacheready;

       dma6_active      txc_drr_if.dmc_txc_dma6_active;
       dma6_eoflist     txc_drr_if.dmc_txc_dma6_eoflist;
       dma6_error       txc_drr_if.dmc_txc_dma6_error;
       dma6_cacheready  txc_drr_if.dmc_txc_dma6_cacheready;

       dma7_active      txc_drr_if.dmc_txc_dma7_active;
       dma7_eoflist     txc_drr_if.dmc_txc_dma7_eoflist;
       dma7_error       txc_drr_if.dmc_txc_dma7_error;
       dma7_cacheready  txc_drr_if.dmc_txc_dma7_cacheready;

       dma8_active      txc_drr_if.dmc_txc_dma8_active;
       dma8_eoflist     txc_drr_if.dmc_txc_dma8_eoflist;
       dma8_error       txc_drr_if.dmc_txc_dma8_error;
       dma8_cacheready  txc_drr_if.dmc_txc_dma8_cacheready;

       dma9_active      txc_drr_if.dmc_txc_dma9_active;
       dma9_eoflist     txc_drr_if.dmc_txc_dma9_eoflist;
       dma9_error       txc_drr_if.dmc_txc_dma9_error;
       dma9_cacheready  txc_drr_if.dmc_txc_dma9_cacheready;

       dma10_active      txc_drr_if.dmc_txc_dma10_active;
       dma10_eoflist     txc_drr_if.dmc_txc_dma10_eoflist;
       dma10_error       txc_drr_if.dmc_txc_dma10_error;
       dma10_cacheready  txc_drr_if.dmc_txc_dma10_cacheready;

       dma11_active      txc_drr_if.dmc_txc_dma11_active;
       dma11_eoflist     txc_drr_if.dmc_txc_dma11_eoflist;
       dma11_error       txc_drr_if.dmc_txc_dma11_error;
       dma11_cacheready  txc_drr_if.dmc_txc_dma11_cacheready;

       dma12_active      txc_drr_if.dmc_txc_dma12_active;
       dma12_eoflist     txc_drr_if.dmc_txc_dma12_eoflist;
       dma12_error       txc_drr_if.dmc_txc_dma12_error;
       dma12_cacheready  txc_drr_if.dmc_txc_dma12_cacheready;

       dma13_active      txc_drr_if.dmc_txc_dma13_active;
       dma13_eoflist     txc_drr_if.dmc_txc_dma13_eoflist;
       dma13_error       txc_drr_if.dmc_txc_dma13_error;
       dma13_cacheready  txc_drr_if.dmc_txc_dma13_cacheready;

              dma14_active      txc_drr_if.dmc_txc_dma14_active;
       dma14_eoflist     txc_drr_if.dmc_txc_dma14_eoflist;
       dma14_error       txc_drr_if.dmc_txc_dma14_error;
       dma14_cacheready  txc_drr_if.dmc_txc_dma14_cacheready;

       dma15_active      txc_drr_if.dmc_txc_dma15_active;
       dma15_eoflist     txc_drr_if.dmc_txc_dma15_eoflist;
       dma15_error       txc_drr_if.dmc_txc_dma15_error;
       dma15_cacheready  txc_drr_if.dmc_txc_dma15_cacheready;

       dma16_active      txc_drr_if.dmc_txc_dma16_active;
       dma16_eoflist     txc_drr_if.dmc_txc_dma16_eoflist;
       dma16_error       txc_drr_if.dmc_txc_dma16_error;
       dma16_cacheready  txc_drr_if.dmc_txc_dma16_cacheready;

       dma17_active      txc_drr_if.dmc_txc_dma17_active;
       dma17_eoflist     txc_drr_if.dmc_txc_dma17_eoflist;
       dma17_error       txc_drr_if.dmc_txc_dma17_error;
       dma17_cacheready  txc_drr_if.dmc_txc_dma17_cacheready;

       dma18_active      txc_drr_if.dmc_txc_dma18_active;
       dma18_eoflist     txc_drr_if.dmc_txc_dma18_eoflist;
       dma18_error       txc_drr_if.dmc_txc_dma18_error;
       dma18_cacheready  txc_drr_if.dmc_txc_dma18_cacheready;

       dma19_active      txc_drr_if.dmc_txc_dma19_active;
       dma19_eoflist     txc_drr_if.dmc_txc_dma19_eoflist;
       dma19_error       txc_drr_if.dmc_txc_dma19_error;
       dma19_cacheready  txc_drr_if.dmc_txc_dma19_cacheready;

       dma20_active      txc_drr_if.dmc_txc_dma20_active;
       dma20_eoflist     txc_drr_if.dmc_txc_dma20_eoflist;
       dma20_error       txc_drr_if.dmc_txc_dma20_error;
       dma20_cacheready  txc_drr_if.dmc_txc_dma20_cacheready;

       dma21_active      txc_drr_if.dmc_txc_dma21_active;
       dma21_eoflist     txc_drr_if.dmc_txc_dma21_eoflist;
       dma21_error       txc_drr_if.dmc_txc_dma21_error;
       dma21_cacheready  txc_drr_if.dmc_txc_dma21_cacheready;

       dma22_active      txc_drr_if.dmc_txc_dma22_active;
       dma22_eoflist     txc_drr_if.dmc_txc_dma22_eoflist;
       dma22_error       txc_drr_if.dmc_txc_dma22_error;
       dma22_cacheready  txc_drr_if.dmc_txc_dma22_cacheready;

       dma23_active      txc_drr_if.dmc_txc_dma23_active;
       dma23_eoflist     txc_drr_if.dmc_txc_dma23_eoflist;
       dma23_error       txc_drr_if.dmc_txc_dma23_error;
       dma23_cacheready  txc_drr_if.dmc_txc_dma23_cacheready;

       dma24_active      txc_drr_if.dmc_txc_dma24_active;
       dma24_eoflist     txc_drr_if.dmc_txc_dma24_eoflist;
       dma24_error       txc_drr_if.dmc_txc_dma24_error;
       dma24_cacheready  txc_drr_if.dmc_txc_dma24_cacheready;

       dma25_active      txc_drr_if.dmc_txc_dma25_active;
       dma25_eoflist     txc_drr_if.dmc_txc_dma25_eoflist;
       dma25_error       txc_drr_if.dmc_txc_dma25_error;
       dma25_cacheready  txc_drr_if.dmc_txc_dma25_cacheready;

       dma26_active      txc_drr_if.dmc_txc_dma26_active;
       dma26_eoflist     txc_drr_if.dmc_txc_dma26_eoflist;
       dma26_error       txc_drr_if.dmc_txc_dma26_error;
       dma26_cacheready  txc_drr_if.dmc_txc_dma26_cacheready;

       dma27_active      txc_drr_if.dmc_txc_dma27_active;
       dma27_eoflist     txc_drr_if.dmc_txc_dma27_eoflist;
       dma27_error       txc_drr_if.dmc_txc_dma27_error;
       dma27_cacheready  txc_drr_if.dmc_txc_dma27_cacheready;

       dma28_active      txc_drr_if.dmc_txc_dma28_active;
       dma28_eoflist     txc_drr_if.dmc_txc_dma28_eoflist;
       dma28_error       txc_drr_if.dmc_txc_dma28_error;
       dma28_cacheready  txc_drr_if.dmc_txc_dma28_cacheready;

       dma29_active      txc_drr_if.dmc_txc_dma29_active;
       dma29_eoflist     txc_drr_if.dmc_txc_dma29_eoflist;
       dma29_error       txc_drr_if.dmc_txc_dma29_error;
       dma29_cacheready  txc_drr_if.dmc_txc_dma29_cacheready;

       dma30_active      txc_drr_if.dmc_txc_dma30_active;
       dma30_eoflist     txc_drr_if.dmc_txc_dma30_eoflist;
       dma30_error       txc_drr_if.dmc_txc_dma30_error;
       dma30_cacheready  txc_drr_if.dmc_txc_dma30_cacheready;

       dma31_active      txc_drr_if.dmc_txc_dma31_active;
       dma31_eoflist     txc_drr_if.dmc_txc_dma31_eoflist;
       dma31_error       txc_drr_if.dmc_txc_dma31_error;
       dma31_cacheready  txc_drr_if.dmc_txc_dma31_cacheready;


       latch_dma        txc_drr_if.latch_activedma;
       add_credit       txc_drr_if.AddCreditToContext;
}