[OpenSPARC-T2-DV] / verif / env / niu / vera / niu_pio / include / dmc_memory_map.vri

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmc_memory_map.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#include "neptune_memory_map.vri"


#define  RX_DMA_CK_DIV		FZC_DMC_ADDRESS_RANGE+20'h00000
#define  RDC_DEF_PT0_RDC	FZC_DMC_ADDRESS_RANGE+20'h00008
#define  RDC_DEF_PT1_RDC	FZC_DMC_ADDRESS_RANGE+20'h00010
#define	 RDC_DEF_PT2_RDC	FZC_DMC_ADDRESS_RANGE+20'h00018
#define  RDC_DEF_PT3_RDC	FZC_DMC_ADDRESS_RANGE+20'h00020
#define  RDC_TABLE_BASE		FZC_DMC_ADDRESS_RANGE+20'h10000
#define	 RX_LOG_PAGE_VLD	FZC_DMC_ADDRESS_RANGE+20'h20000
#define	 RX_LOG_STEP   		'h40
#define  RX_LOG_PAGE1		FZC_DMC_ADDRESS_RANGE+20'h20008
#define  RX_LOG_PAGE2		FZC_DMC_ADDRESS_RANGE+20'h20010
#define	 RX_LOG_PAGE_MASK1	FZC_DMC_ADDRESS_RANGE+20'h20008
#define	 RX_LOG_PAGE_MASK2	FZC_DMC_ADDRESS_RANGE+20'h20010
#define	 RX_LOG_PAGE_VALUE1	FZC_DMC_ADDRESS_RANGE+20'h20018
#define	 RX_LOG_PAGE_VALUE2	FZC_DMC_ADDRESS_RANGE+20'h20020
#define	 RX_LOG_PAGE_RELO1	FZC_DMC_ADDRESS_RANGE+20'h20028
#define	 RX_LOG_PAGE_RELO2	FZC_DMC_ADDRESS_RANGE+20'h20030
#define	 RX_LOG_PAGE_HDL	FZC_DMC_ADDRESS_RANGE+20'h20038

#define  RDC_RED_PARA		FZC_DMC_ADDRESS_RANGE+20'h30000
#define  RDC_RED_STEP		'h10
//#define  RXDMA_CFIG_BASE	DMC_ADDRESS_RANGE+20'h00000
#define  RXDMA_CFIG1		DMC_ADDRESS_RANGE+20'h00000
#define  RXDMA_CFIG2		DMC_ADDRESS_RANGE+20'h00008
#define  RBR_CFIG_A		DMC_ADDRESS_RANGE+20'h00010
#define  RBR_CFIG_B		DMC_ADDRESS_RANGE+20'h00018
#define	 RBR_KICK		DMC_ADDRESS_RANGE+20'h00020
#define	 RBR_STAT		DMC_ADDRESS_RANGE+20'h00028
#define	 RBR_HD			DMC_ADDRESS_RANGE+20'h00030
#define  RCR_CFIG_A		DMC_ADDRESS_RANGE+20'h00040
#define  RCR_CFIG_B		DMC_ADDRESS_RANGE+20'h00048
#define  RCR_STAT_A		DMC_ADDRESS_RANGE+20'h00050
#define  RCR_STAT_C		DMC_ADDRESS_RANGE+20'h00058
#define  RCR_STAT_D		DMC_ADDRESS_RANGE+20'h00060
#define	 TBR_CFIG_A		DMC_ADDRESS_RANGE+20'h10000
#define	 RBR_HDH		DMC_ADDRESS_RANGE+20'h00030
#define	 RBR_HDL		DMC_ADDRESS_RANGE+20'h00038


/* #define TX_RING_HD		DMC_ADDRESS_RANGE+20'h40008
#define TX_RING_KICK		DMC_ADDRESS_RANGE+20'h40010
#define TXDMA_CFG		DMC_ADDRESS_RANGE+20'h40018
*/ 

#define TX_RNG_CFIG             DMC_ADDRESS_RANGE+20'h40000
#define TX_RING_HDH             DMC_ADDRESS_RANGE+20'h40008
#define TX_RING_HDL             DMC_ADDRESS_RANGE+20'h40010
#define TX_RING_KICK            DMC_ADDRESS_RANGE+20'h40018
#define TX_ENT_MASK             DMC_ADDRESS_RANGE+20'h40020
#define TX_CS                   DMC_ADDRESS_RANGE+20'h40028
#define TXDMA_MBH               DMC_ADDRESS_RANGE+20'h40030
#define TXDMA_MBL               DMC_ADDRESS_RANGE+20'h40038
#define TX_DMA_PRE_ST           DMC_ADDRESS_RANGE+20'h40040
#define TX_RNG_ERR_LOGH         DMC_ADDRESS_RANGE+20'h40048
#define TX_RNG_ERR_LOGL         DMC_ADDRESS_RANGE+20'h40050
#define TDMC_INTR_DBG           DMC_ADDRESS_RANGE+20'h40060
#define TX_CS_DBG               DMC_ADDRESS_RANGE+20'h40068

#define TX_LOG_PAGE_VLD         FZC_DMC_ADDRESS_RANGE+20'h40000
#define TX_LOG_MASK1            FZC_DMC_ADDRESS_RANGE+20'h40008
#define TX_LOG_VALUE1           FZC_DMC_ADDRESS_RANGE+20'h40010
#define TX_LOG_MASK2            FZC_DMC_ADDRESS_RANGE+20'h40018
#define TX_LOG_VALUE2           FZC_DMC_ADDRESS_RANGE+20'h40020
#define TX_LOG_PAGE_RELO1       FZC_DMC_ADDRESS_RANGE+20'h40028
#define TX_LOG_PAGE_RELO2       FZC_DMC_ADDRESS_RANGE+20'h40030
#define TX_LOG_PAGE_HDL         FZC_DMC_ADDRESS_RANGE+20'h40038
#define TDMC_INJ_PAR_ERR        FZC_DMC_ADDRESS_RANGE+20'h45040
#define TDMC_DBG_SEL            FZC_DMC_ADDRESS_RANGE+20'h45080
#define TDMC_TRAIN_VEC          FZC_DMC_ADDRESS_RANGE+20'h45088

#define TX_DMA_MAP0             FZC_DMC_ADDRESS_RANGE+20'h50000
#define TX_DMA_MAP1             FZC_DMC_ADDRESS_RANGE+20'h50008
#define TX_DMA_MAP2             FZC_DMC_ADDRESS_RANGE+20'h50010
#define TX_DMA_MAP3             FZC_DMC_ADDRESS_RANGE+20'h50018

#define TXDMA_DUMMY		DMC_ADDRESS_RANGE+20'h40040


// ################################################################################
// ALL RDMC Registers #defined. Not using hard numbers anywhere in the tests/env.
// ################################################################################

#define DEF_PTO_RDC		FZC_DMC_ADDRESS_RANGE+20'h00008
#define DEF_PT1_RDC		FZC_DMC_ADDRESS_RANGE+20'h00010
#define DEF_PT2_RDC		FZC_DMC_ADDRESS_RANGE+20'h00018
#define DEF_PT3_RDC		FZC_DMC_ADDRESS_RANGE+20'h00020
#define RDC_TBL_START		FZC_DMC_ADDRESS_RANGE+20'h10000
#define RDC_TBL_END		FZC_DMC_ADDRESS_RANGE+20'h107f8
#define RDC_TBL_STEP		8
#define RX_ADDR_MD		FZC_DMC_ADDRESS_RANGE+20'h00070
#define PT_DRR_WT0		FZC_DMC_ADDRESS_RANGE+20'h00028
#define PT_DRR_WT1		FZC_DMC_ADDRESS_RANGE+20'h00030
#define PT_DRR_WT2		FZC_DMC_ADDRESS_RANGE+20'h00038
#define PT_DRR_WT3		FZC_DMC_ADDRESS_RANGE+20'h00040
#define PT_USE0   		FZC_DMC_ADDRESS_RANGE+20'h00048
#define PT_USE1   		FZC_DMC_ADDRESS_RANGE+20'h00050
#define PT_USE2   		FZC_DMC_ADDRESS_RANGE+20'h00058
#define PT_USE3   		FZC_DMC_ADDRESS_RANGE+20'h00060
#define RX_LOG_PAGE_VLD_START 	FZC_DMC_ADDRESS_RANGE+20'h20000
#define RX_LOG_PAGE_VLD_END 	FZC_DMC_ADDRESS_RANGE+20'h203c0
#define RX_LOG_PAGE_VLD_STEP    8'h40
#define RX_LOG_MASK1_START 	FZC_DMC_ADDRESS_RANGE+20'h20008
#define RX_LOG_MASK1_END 	FZC_DMC_ADDRESS_RANGE+20'h203c8
#define RX_LOG_MASK1_STEP       8'h40
#define RX_LOG_VAL1_START 	FZC_DMC_ADDRESS_RANGE+20'h20010
#define RX_LOG_VAL1_END 	FZC_DMC_ADDRESS_RANGE+20'h203d0
#define RX_LOG_VAL1_STEP        8'h40
#define RX_LOG_MASK2_START 	FZC_DMC_ADDRESS_RANGE+20'h20018
#define RX_LOG_MASK2_END 	FZC_DMC_ADDRESS_RANGE+20'h203d8
#define RX_LOG_MASK2_STEP       8'h40
#define RX_LOG_VAL2_START 	FZC_DMC_ADDRESS_RANGE+20'h20020
#define RX_LOG_VAL2_END 	FZC_DMC_ADDRESS_RANGE+20'h203e0
#define RX_LOG_VAL2_STEP        8'h40
#define RX_LOG_RELO1_START 	FZC_DMC_ADDRESS_RANGE+20'h20028
#define RX_LOG_RELO1_END 	FZC_DMC_ADDRESS_RANGE+20'h203e8
#define RX_LOG_RELO1_STEP       8'h40
#define RX_LOG_RELO2_START 	FZC_DMC_ADDRESS_RANGE+20'h20030
#define RX_LOG_RELO2_END 	FZC_DMC_ADDRESS_RANGE+20'h203f0
#define RX_LOG_RELO2_STEP       8'h40
#define RX_LOG_PAGE_HDL_START 	FZC_DMC_ADDRESS_RANGE+20'h20038
#define RX_LOG_PAGE_HDL_END 	FZC_DMC_ADDRESS_RANGE+20'h203f8
#define RX_LOG_PAGE_HDL_STEP    8'h40
#define RED_RAN_INIT	 	FZC_DMC_ADDRESS_RANGE+20'h00068
#define RDC_RED_PARA_START     	FZC_DMC_ADDRESS_RANGE+20'h30000
#define RDC_RED_PARA_END     	FZC_DMC_ADDRESS_RANGE+20'h303c0
#define RDC_RED_PARA_STEP       8'h40
#define RED_DIS_CNT_START     	FZC_DMC_ADDRESS_RANGE+20'h30008
#define RED_DIS_CNT_END     	FZC_DMC_ADDRESS_RANGE+20'h303c8
#define RED_DIS_CNT_STEP        8'h40
#define RXDMA_CFIG1_START     	DMC_ADDRESS_RANGE+20'h00000
#define RXDMA_CFIG1_END       	DMC_ADDRESS_RANGE+20'h01e00
#define RXDMA_CFIG2_START     	DMC_ADDRESS_RANGE+20'h00008
#define RXDMA_CFIG2_END       	DMC_ADDRESS_RANGE+20'h01e08
#define RBR_CFIG_A_START      	DMC_ADDRESS_RANGE+20'h00010
#define RBR_CFIG_A_END       	DMC_ADDRESS_RANGE+20'h01e10
#define RBR_CFIG_B_START      	DMC_ADDRESS_RANGE+20'h00018
#define RBR_CFIG_B_END       	DMC_ADDRESS_RANGE+20'h01e18
#define RBR_KICK_START      	DMC_ADDRESS_RANGE+20'h00020
#define RBR_KICK_END       	DMC_ADDRESS_RANGE+20'h01e20
#define RBR_STAT_START      	DMC_ADDRESS_RANGE+20'h00028
#define RBR_STAT_END       	DMC_ADDRESS_RANGE+20'h01e28
#define RBR_HDH_START      	DMC_ADDRESS_RANGE+20'h00030
#define RBR_HDH_END       	DMC_ADDRESS_RANGE+20'h01e30
#define RBR_HDL_START      	DMC_ADDRESS_RANGE+20'h00038
#define RBR_HDL_END       	DMC_ADDRESS_RANGE+20'h01e38
#define RCR_CFIG_A_START      	DMC_ADDRESS_RANGE+20'h00040
#define RCR_CFIG_A_END       	DMC_ADDRESS_RANGE+20'h01e40
#define RCR_CFIG_B_START      	DMC_ADDRESS_RANGE+20'h00048
#define RCR_CFIG_B_END       	DMC_ADDRESS_RANGE+20'h01e48
#define RCR_STAT_A_START      	DMC_ADDRESS_RANGE+20'h00050
#define RCR_STAT_A_END       	DMC_ADDRESS_RANGE+20'h01e50
#define RCR_STAT_B_START      	DMC_ADDRESS_RANGE+20'h00058
#define RCR_STAT_B_END       	DMC_ADDRESS_RANGE+20'h01e58
#define RCR_STAT_C_START      	DMC_ADDRESS_RANGE+20'h00060
#define RCR_STAT_C_END       	DMC_ADDRESS_RANGE+20'h01e60
#define RX_DMA_ENT_MSK_START    DMC_ADDRESS_RANGE+20'h00068
#define RX_DMA_ENT_MSK_END      DMC_ADDRESS_RANGE+20'h01e68
#define RX_DMA_CTL_STAT_START   DMC_ADDRESS_RANGE+20'h00070
#define RX_DMA_CTL_STAT_END     DMC_ADDRESS_RANGE+20'h01e70
#define RCR_FLUSH_START         DMC_ADDRESS_RANGE+20'h00078
#define RCR_FLUSH_END           DMC_ADDRESS_RANGE+20'h01e78
#define RX_DMA_LOGA_START       DMC_ADDRESS_RANGE+20'h00080
#define RX_DMA_LOGA_END         DMC_ADDRESS_RANGE+20'h01e80
#define RX_DMA_LOGB_START       DMC_ADDRESS_RANGE+20'h00088
#define RX_DMA_LOGB_END         DMC_ADDRESS_RANGE+20'h01e88
#define RX_MISC_START		DMC_ADDRESS_RANGE+20'h00090
#define RX_MISC_END  		DMC_ADDRESS_RANGE+20'h01e90
#define RDC_PRE_EMPTY_START     DMC_ADDRESS_RANGE+20'h000b0
#define RDC_PRE_EMPTY_END       DMC_ADDRESS_RANGE+20'h01eb0
#define RX_DMA_INTR_DEBUG_START DMC_ADDRESS_RANGE+20'h00098
#define RX_DMA_INTR_DEBUG_END   DMC_ADDRESS_RANGE+20'h01e98
#define RXDMA_STEP		12'h200

#define RDMC_PRE_PAR_ERR	FZC_DMC_ADDRESS_RANGE+20'h00078
#define RDMC_SHA_PAR_ERR	FZC_DMC_ADDRESS_RANGE+20'h00080
#define RDMC_MEM_ADDR		FZC_DMC_ADDRESS_RANGE+20'h00088
#define RDMC_MEM_DAT0		FZC_DMC_ADDRESS_RANGE+20'h00090
#define RDMC_MEM_DAT1		FZC_DMC_ADDRESS_RANGE+20'h00098
#define RDMC_MEM_DAT2		FZC_DMC_ADDRESS_RANGE+20'h000a0
#define RDMC_MEM_DAT3		FZC_DMC_ADDRESS_RANGE+20'h000a8
#define RDMC_MEM_DAT4		FZC_DMC_ADDRESS_RANGE+20'h000b0

#define RX_CTL_DAT_FIFO_MASK    FZC_DMC_ADDRESS_RANGE+20'h000c0
#define RX_CTL_DAT_FIFO_STAT    FZC_DMC_ADDRESS_RANGE+20'h000b8
#define RX_CTL_DAT_FIFO_STAT_DBG FZC_DMC_ADDRESS_RANGE+20'h000d0
#define RDMC_TRAINING_VECTOR	FZC_DMC_ADDRESS_RANGE+20'h000c8


// RDMC Register Bit definitions

// RX_DMA_ENT_MSK Register
#define RX_DMA_ENT_MSK_RBR_TMOUT 	21
#define RX_DMA_ENT_MSK_RSP_CNT_ERR 	20
#define RX_DMA_ENT_MSK_BYTE_EN_BUS 	19
#define RX_DMA_ENT_MSK_RSP_DAT_ERR 	18
#define RX_DMA_ENT_MSK_RCR_ACK_ERR 	17
#define RX_DMA_ENT_MSK_DC_FIFO_ERR 	16
#define RX_DMA_ENT_MSK_RCRTHRES 	14
#define RX_DMA_ENT_MSK_RCRTO 		13
#define RX_DMA_ENT_MSK_RCR_SHA_PAR 	12
#define RX_DMA_ENT_MSK_RBR_PRE_PAR 	11
#define RX_DMA_ENT_MSK_PORT_DROP_PKT 	10
#define RX_DMA_ENT_MSK_WRED_DROP 	9
#define RX_DMA_ENT_MSK_RBR_PRE_EMTY 	8
#define RX_DMA_ENT_MSK_RCR_SHADOW_FULL	7
#define RX_DMA_ENT_MSK_CONFIG_ERR 	6
#define RX_DMA_ENT_MSK_RCRINCON 	5
#define RX_DMA_ENT_MSK_RCRFULL 		4
#define RX_DMA_ENT_MSK_RBR_EMPTY 	3
#define RX_DMA_ENT_MSK_RBRFULL 		2
#define RX_DMA_ENT_MSK_RBRLOGPAGE 	1
#define RX_DMA_ENT_MSK_CFIGLOGPAGE 	0

// RX_DMA_CTL_STAT Register
#define RX_DMA_CTL_STAT_RBR_TMOUT 	53
#define RX_DMA_CTL_STAT_RSP_CNT_ERR 	52
#define RX_DMA_CTL_STAT_BYTE_EN_BUS 	51
#define RX_DMA_CTL_STAT_RSP_DAT_ERR 	50
#define RX_DMA_CTL_STAT_RCR_ACK_ERR 	49
#define RX_DMA_CTL_STAT_DC_FIFO_ERR 	48
#define RX_DMA_CTL_STAT_MEX 		47
#define RX_DMA_CTL_STAT_RCRTHRES 	46
#define RX_DMA_CTL_STAT_RCRTO 		45
#define RX_DMA_CTL_STAT_RCR_SHA_PAR 	44
#define RX_DMA_CTL_STAT_RBR_PRE_PAR 	43
#define RX_DMA_CTL_STAT_PORT_DROP_PKT 	42
#define RX_DMA_CTL_STAT_WRED_DROP 	41
#define RX_DMA_CTL_STAT_RBR_PRE_EMTY 	40
#define RX_DMA_CTL_STAT_RCR_SHADOW_FULL 39
#define RX_DMA_CTL_STAT_CONFIG_ERR 	38
#define RX_DMA_CTL_STAT_RCRINCON 	37
#define RX_DMA_CTL_STAT_RCRFULL 	36
#define RX_DMA_CTL_STAT_RBR_EMPTY 	35
#define RX_DMA_CTL_STAT_RBRFULL 	34
#define RX_DMA_CTL_STAT_RBRLOGPAGE 	33
#define RX_DMA_CTL_STAT_CFIGLOGPAGE 	32

#define RX_DMA_CTL_STAT_PTRREAD 	31:16
#define RX_DMA_CTL_STAT_PKTREAD 	15:0

// RX_DMA_INTR_DEBUG Register
#define RX_DMA_INTR_DEBUG_RBR_TMOUT 		53
#define RX_DMA_INTR_DEBUG_RSP_CNT_ERR 		52
#define RX_DMA_INTR_DEBUG_BYTE_EN_BUS 		51
#define RX_DMA_INTR_DEBUG_RSP_DAT_ERR 		50
#define RX_DMA_INTR_DEBUG_RCR_ACK_ERR 		49
#define RX_DMA_INTR_DEBUG_DC_FIFO_ERR 		48
#define RX_DMA_INTR_DEBUG_MEX 			47
#define RX_DMA_INTR_DEBUG_RCRTHRES 		46
#define RX_DMA_INTR_DEBUG_RCRTO 		45
#define RX_DMA_INTR_DEBUG_RCR_SHA_PAR 		44
#define RX_DMA_INTR_DEBUG_RBR_PRE_PAR 		43
#define RX_DMA_INTR_DEBUG_PORT_DROP_PKT 	42
#define RX_DMA_INTR_DEBUG_WRED_DROP 		41
#define RX_DMA_INTR_DEBUG_RBR_PRE_EMTY 		40
#define RX_DMA_INTR_DEBUG_RCR_SHADOW_FULL 	39
#define RX_DMA_INTR_DEBUG_CONFIG_ERR 		38
#define RX_DMA_INTR_DEBUG_RCRINCON 		37
#define RX_DMA_INTR_DEBUG_RCRFULL 		36
#define RX_DMA_INTR_DEBUG_RBR_EMPTY 		35
#define RX_DMA_INTR_DEBUG_RBRFULL 		34
#define RX_DMA_INTR_DEBUG_RBRLOGPAGE 		33
#define RX_DMA_INTR_DEBUG_CFIGLOGPAGE 		32

#define RX_DMA_INTR_DEBUG_PTRREAD 		31:16
#define RX_DMA_INTR_DEBUG_PKTREAD 		15:0

#define RX_ADDR_MD_RAM_ACC 			1

#define RDMC_MEM_ADDR_PRE_SHAD			8
#define RDMC_MEM_ADDR_PRE_ADDR			7:0
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: dmc_memory_map.vri
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	#include "neptune_memory_map.vri"
	36
	37
	38	#define RX_DMA_CK_DIV FZC_DMC_ADDRESS_RANGE+20'h00000
	39	#define RDC_DEF_PT0_RDC FZC_DMC_ADDRESS_RANGE+20'h00008
	40	#define RDC_DEF_PT1_RDC FZC_DMC_ADDRESS_RANGE+20'h00010
	41	#define RDC_DEF_PT2_RDC FZC_DMC_ADDRESS_RANGE+20'h00018
	42	#define RDC_DEF_PT3_RDC FZC_DMC_ADDRESS_RANGE+20'h00020
	43	#define RDC_TABLE_BASE FZC_DMC_ADDRESS_RANGE+20'h10000
	44	#define RX_LOG_PAGE_VLD FZC_DMC_ADDRESS_RANGE+20'h20000
	45	#define RX_LOG_STEP 'h40
	46	#define RX_LOG_PAGE1 FZC_DMC_ADDRESS_RANGE+20'h20008
	47	#define RX_LOG_PAGE2 FZC_DMC_ADDRESS_RANGE+20'h20010
	48	#define RX_LOG_PAGE_MASK1 FZC_DMC_ADDRESS_RANGE+20'h20008
	49	#define RX_LOG_PAGE_MASK2 FZC_DMC_ADDRESS_RANGE+20'h20010
	50	#define RX_LOG_PAGE_VALUE1 FZC_DMC_ADDRESS_RANGE+20'h20018
	51	#define RX_LOG_PAGE_VALUE2 FZC_DMC_ADDRESS_RANGE+20'h20020
	52	#define RX_LOG_PAGE_RELO1 FZC_DMC_ADDRESS_RANGE+20'h20028
	53	#define RX_LOG_PAGE_RELO2 FZC_DMC_ADDRESS_RANGE+20'h20030
	54	#define RX_LOG_PAGE_HDL FZC_DMC_ADDRESS_RANGE+20'h20038
	55
	56	#define RDC_RED_PARA FZC_DMC_ADDRESS_RANGE+20'h30000
	57	#define RDC_RED_STEP 'h10
	58	//#define RXDMA_CFIG_BASE DMC_ADDRESS_RANGE+20'h00000
	59	#define RXDMA_CFIG1 DMC_ADDRESS_RANGE+20'h00000
	60	#define RXDMA_CFIG2 DMC_ADDRESS_RANGE+20'h00008
	61	#define RBR_CFIG_A DMC_ADDRESS_RANGE+20'h00010
	62	#define RBR_CFIG_B DMC_ADDRESS_RANGE+20'h00018
	63	#define RBR_KICK DMC_ADDRESS_RANGE+20'h00020
	64	#define RBR_STAT DMC_ADDRESS_RANGE+20'h00028
65	#define RBR_HD DMC_ADDRESS_RANGE+20'h00030
66	#define RCR_CFIG_A DMC_ADDRESS_RANGE+20'h00040
67	#define RCR_CFIG_B DMC_ADDRESS_RANGE+20'h00048
68	#define RCR_STAT_A DMC_ADDRESS_RANGE+20'h00050
69	#define RCR_STAT_C DMC_ADDRESS_RANGE+20'h00058
70	#define RCR_STAT_D DMC_ADDRESS_RANGE+20'h00060
71	#define TBR_CFIG_A DMC_ADDRESS_RANGE+20'h10000
72	#define RBR_HDH DMC_ADDRESS_RANGE+20'h00030
73	#define RBR_HDL DMC_ADDRESS_RANGE+20'h00038
74
75
76	/* #define TX_RING_HD DMC_ADDRESS_RANGE+20'h40008
77	#define TX_RING_KICK DMC_ADDRESS_RANGE+20'h40010
78	#define TXDMA_CFG DMC_ADDRESS_RANGE+20'h40018
79	*/
80
81	#define TX_RNG_CFIG DMC_ADDRESS_RANGE+20'h40000
82	#define TX_RING_HDH DMC_ADDRESS_RANGE+20'h40008
83	#define TX_RING_HDL DMC_ADDRESS_RANGE+20'h40010
84	#define TX_RING_KICK DMC_ADDRESS_RANGE+20'h40018
85	#define TX_ENT_MASK DMC_ADDRESS_RANGE+20'h40020
86	#define TX_CS DMC_ADDRESS_RANGE+20'h40028
87	#define TXDMA_MBH DMC_ADDRESS_RANGE+20'h40030
88	#define TXDMA_MBL DMC_ADDRESS_RANGE+20'h40038
89	#define TX_DMA_PRE_ST DMC_ADDRESS_RANGE+20'h40040
90	#define TX_RNG_ERR_LOGH DMC_ADDRESS_RANGE+20'h40048
91	#define TX_RNG_ERR_LOGL DMC_ADDRESS_RANGE+20'h40050
92	#define TDMC_INTR_DBG DMC_ADDRESS_RANGE+20'h40060
93	#define TX_CS_DBG DMC_ADDRESS_RANGE+20'h40068
94
95	#define TX_LOG_PAGE_VLD FZC_DMC_ADDRESS_RANGE+20'h40000
96	#define TX_LOG_MASK1 FZC_DMC_ADDRESS_RANGE+20'h40008
97	#define TX_LOG_VALUE1 FZC_DMC_ADDRESS_RANGE+20'h40010
98	#define TX_LOG_MASK2 FZC_DMC_ADDRESS_RANGE+20'h40018
99	#define TX_LOG_VALUE2 FZC_DMC_ADDRESS_RANGE+20'h40020
100	#define TX_LOG_PAGE_RELO1 FZC_DMC_ADDRESS_RANGE+20'h40028
101	#define TX_LOG_PAGE_RELO2 FZC_DMC_ADDRESS_RANGE+20'h40030
102	#define TX_LOG_PAGE_HDL FZC_DMC_ADDRESS_RANGE+20'h40038
103	#define TDMC_INJ_PAR_ERR FZC_DMC_ADDRESS_RANGE+20'h45040
104	#define TDMC_DBG_SEL FZC_DMC_ADDRESS_RANGE+20'h45080
105	#define TDMC_TRAIN_VEC FZC_DMC_ADDRESS_RANGE+20'h45088
106
107	#define TX_DMA_MAP0 FZC_DMC_ADDRESS_RANGE+20'h50000
108	#define TX_DMA_MAP1 FZC_DMC_ADDRESS_RANGE+20'h50008
109	#define TX_DMA_MAP2 FZC_DMC_ADDRESS_RANGE+20'h50010
110	#define TX_DMA_MAP3 FZC_DMC_ADDRESS_RANGE+20'h50018
111
112	#define TXDMA_DUMMY DMC_ADDRESS_RANGE+20'h40040
113
114
115	// ################################################################################
116	// ALL RDMC Registers #defined. Not using hard numbers anywhere in the tests/env.
117	// ################################################################################
118
119	#define DEF_PTO_RDC FZC_DMC_ADDRESS_RANGE+20'h00008
120	#define DEF_PT1_RDC FZC_DMC_ADDRESS_RANGE+20'h00010
121	#define DEF_PT2_RDC FZC_DMC_ADDRESS_RANGE+20'h00018
122	#define DEF_PT3_RDC FZC_DMC_ADDRESS_RANGE+20'h00020
123	#define RDC_TBL_START FZC_DMC_ADDRESS_RANGE+20'h10000
124	#define RDC_TBL_END FZC_DMC_ADDRESS_RANGE+20'h107f8
125	#define RDC_TBL_STEP 8
126	#define RX_ADDR_MD FZC_DMC_ADDRESS_RANGE+20'h00070
127	#define PT_DRR_WT0 FZC_DMC_ADDRESS_RANGE+20'h00028
128	#define PT_DRR_WT1 FZC_DMC_ADDRESS_RANGE+20'h00030
129	#define PT_DRR_WT2 FZC_DMC_ADDRESS_RANGE+20'h00038
130	#define PT_DRR_WT3 FZC_DMC_ADDRESS_RANGE+20'h00040
131	#define PT_USE0 FZC_DMC_ADDRESS_RANGE+20'h00048
132	#define PT_USE1 FZC_DMC_ADDRESS_RANGE+20'h00050
133	#define PT_USE2 FZC_DMC_ADDRESS_RANGE+20'h00058
134	#define PT_USE3 FZC_DMC_ADDRESS_RANGE+20'h00060
135	#define RX_LOG_PAGE_VLD_START FZC_DMC_ADDRESS_RANGE+20'h20000
136	#define RX_LOG_PAGE_VLD_END FZC_DMC_ADDRESS_RANGE+20'h203c0
137	#define RX_LOG_PAGE_VLD_STEP 8'h40
138	#define RX_LOG_MASK1_START FZC_DMC_ADDRESS_RANGE+20'h20008
139	#define RX_LOG_MASK1_END FZC_DMC_ADDRESS_RANGE+20'h203c8
140	#define RX_LOG_MASK1_STEP 8'h40
141	#define RX_LOG_VAL1_START FZC_DMC_ADDRESS_RANGE+20'h20010
142	#define RX_LOG_VAL1_END FZC_DMC_ADDRESS_RANGE+20'h203d0
143	#define RX_LOG_VAL1_STEP 8'h40
144	#define RX_LOG_MASK2_START FZC_DMC_ADDRESS_RANGE+20'h20018
145	#define RX_LOG_MASK2_END FZC_DMC_ADDRESS_RANGE+20'h203d8
146	#define RX_LOG_MASK2_STEP 8'h40
147	#define RX_LOG_VAL2_START FZC_DMC_ADDRESS_RANGE+20'h20020
148	#define RX_LOG_VAL2_END FZC_DMC_ADDRESS_RANGE+20'h203e0
149	#define RX_LOG_VAL2_STEP 8'h40
150	#define RX_LOG_RELO1_START FZC_DMC_ADDRESS_RANGE+20'h20028
151	#define RX_LOG_RELO1_END FZC_DMC_ADDRESS_RANGE+20'h203e8
152	#define RX_LOG_RELO1_STEP 8'h40
153	#define RX_LOG_RELO2_START FZC_DMC_ADDRESS_RANGE+20'h20030
154	#define RX_LOG_RELO2_END FZC_DMC_ADDRESS_RANGE+20'h203f0
155	#define RX_LOG_RELO2_STEP 8'h40
156	#define RX_LOG_PAGE_HDL_START FZC_DMC_ADDRESS_RANGE+20'h20038
157	#define RX_LOG_PAGE_HDL_END FZC_DMC_ADDRESS_RANGE+20'h203f8
158	#define RX_LOG_PAGE_HDL_STEP 8'h40
159	#define RED_RAN_INIT FZC_DMC_ADDRESS_RANGE+20'h00068
160	#define RDC_RED_PARA_START FZC_DMC_ADDRESS_RANGE+20'h30000
161	#define RDC_RED_PARA_END FZC_DMC_ADDRESS_RANGE+20'h303c0
162	#define RDC_RED_PARA_STEP 8'h40
163	#define RED_DIS_CNT_START FZC_DMC_ADDRESS_RANGE+20'h30008
164	#define RED_DIS_CNT_END FZC_DMC_ADDRESS_RANGE+20'h303c8
165	#define RED_DIS_CNT_STEP 8'h40
166	#define RXDMA_CFIG1_START DMC_ADDRESS_RANGE+20'h00000
167	#define RXDMA_CFIG1_END DMC_ADDRESS_RANGE+20'h01e00
168	#define RXDMA_CFIG2_START DMC_ADDRESS_RANGE+20'h00008
169	#define RXDMA_CFIG2_END DMC_ADDRESS_RANGE+20'h01e08
170	#define RBR_CFIG_A_START DMC_ADDRESS_RANGE+20'h00010
171	#define RBR_CFIG_A_END DMC_ADDRESS_RANGE+20'h01e10
172	#define RBR_CFIG_B_START DMC_ADDRESS_RANGE+20'h00018
173	#define RBR_CFIG_B_END DMC_ADDRESS_RANGE+20'h01e18
174	#define RBR_KICK_START DMC_ADDRESS_RANGE+20'h00020
175	#define RBR_KICK_END DMC_ADDRESS_RANGE+20'h01e20
176	#define RBR_STAT_START DMC_ADDRESS_RANGE+20'h00028
177	#define RBR_STAT_END DMC_ADDRESS_RANGE+20'h01e28
178	#define RBR_HDH_START DMC_ADDRESS_RANGE+20'h00030
179	#define RBR_HDH_END DMC_ADDRESS_RANGE+20'h01e30
180	#define RBR_HDL_START DMC_ADDRESS_RANGE+20'h00038
181	#define RBR_HDL_END DMC_ADDRESS_RANGE+20'h01e38
182	#define RCR_CFIG_A_START DMC_ADDRESS_RANGE+20'h00040
183	#define RCR_CFIG_A_END DMC_ADDRESS_RANGE+20'h01e40
184	#define RCR_CFIG_B_START DMC_ADDRESS_RANGE+20'h00048
185	#define RCR_CFIG_B_END DMC_ADDRESS_RANGE+20'h01e48
186	#define RCR_STAT_A_START DMC_ADDRESS_RANGE+20'h00050
187	#define RCR_STAT_A_END DMC_ADDRESS_RANGE+20'h01e50
188	#define RCR_STAT_B_START DMC_ADDRESS_RANGE+20'h00058
189	#define RCR_STAT_B_END DMC_ADDRESS_RANGE+20'h01e58
190	#define RCR_STAT_C_START DMC_ADDRESS_RANGE+20'h00060
191	#define RCR_STAT_C_END DMC_ADDRESS_RANGE+20'h01e60
192	#define RX_DMA_ENT_MSK_START DMC_ADDRESS_RANGE+20'h00068
193	#define RX_DMA_ENT_MSK_END DMC_ADDRESS_RANGE+20'h01e68
194	#define RX_DMA_CTL_STAT_START DMC_ADDRESS_RANGE+20'h00070
195	#define RX_DMA_CTL_STAT_END DMC_ADDRESS_RANGE+20'h01e70
196	#define RCR_FLUSH_START DMC_ADDRESS_RANGE+20'h00078
197	#define RCR_FLUSH_END DMC_ADDRESS_RANGE+20'h01e78
198	#define RX_DMA_LOGA_START DMC_ADDRESS_RANGE+20'h00080
199	#define RX_DMA_LOGA_END DMC_ADDRESS_RANGE+20'h01e80
200	#define RX_DMA_LOGB_START DMC_ADDRESS_RANGE+20'h00088
201	#define RX_DMA_LOGB_END DMC_ADDRESS_RANGE+20'h01e88
202	#define RX_MISC_START DMC_ADDRESS_RANGE+20'h00090
203	#define RX_MISC_END DMC_ADDRESS_RANGE+20'h01e90
204	#define RDC_PRE_EMPTY_START DMC_ADDRESS_RANGE+20'h000b0
205	#define RDC_PRE_EMPTY_END DMC_ADDRESS_RANGE+20'h01eb0
206	#define RX_DMA_INTR_DEBUG_START DMC_ADDRESS_RANGE+20'h00098
207	#define RX_DMA_INTR_DEBUG_END DMC_ADDRESS_RANGE+20'h01e98
208	#define RXDMA_STEP 12'h200
209
210	#define RDMC_PRE_PAR_ERR FZC_DMC_ADDRESS_RANGE+20'h00078
211	#define RDMC_SHA_PAR_ERR FZC_DMC_ADDRESS_RANGE+20'h00080
212	#define RDMC_MEM_ADDR FZC_DMC_ADDRESS_RANGE+20'h00088
213	#define RDMC_MEM_DAT0 FZC_DMC_ADDRESS_RANGE+20'h00090
214	#define RDMC_MEM_DAT1 FZC_DMC_ADDRESS_RANGE+20'h00098
215	#define RDMC_MEM_DAT2 FZC_DMC_ADDRESS_RANGE+20'h000a0
216	#define RDMC_MEM_DAT3 FZC_DMC_ADDRESS_RANGE+20'h000a8
217	#define RDMC_MEM_DAT4 FZC_DMC_ADDRESS_RANGE+20'h000b0
218
219	#define RX_CTL_DAT_FIFO_MASK FZC_DMC_ADDRESS_RANGE+20'h000c0
220	#define RX_CTL_DAT_FIFO_STAT FZC_DMC_ADDRESS_RANGE+20'h000b8
221	#define RX_CTL_DAT_FIFO_STAT_DBG FZC_DMC_ADDRESS_RANGE+20'h000d0
222	#define RDMC_TRAINING_VECTOR FZC_DMC_ADDRESS_RANGE+20'h000c8
223
224
225
226	// RDMC Register Bit definitions
227
228	// RX_DMA_ENT_MSK Register
229	#define RX_DMA_ENT_MSK_RBR_TMOUT 21
230	#define RX_DMA_ENT_MSK_RSP_CNT_ERR 20
231	#define RX_DMA_ENT_MSK_BYTE_EN_BUS 19
232	#define RX_DMA_ENT_MSK_RSP_DAT_ERR 18
233	#define RX_DMA_ENT_MSK_RCR_ACK_ERR 17
234	#define RX_DMA_ENT_MSK_DC_FIFO_ERR 16
235	#define RX_DMA_ENT_MSK_RCRTHRES 14
236	#define RX_DMA_ENT_MSK_RCRTO 13
237	#define RX_DMA_ENT_MSK_RCR_SHA_PAR 12
238	#define RX_DMA_ENT_MSK_RBR_PRE_PAR 11
239	#define RX_DMA_ENT_MSK_PORT_DROP_PKT 10
240	#define RX_DMA_ENT_MSK_WRED_DROP 9
241	#define RX_DMA_ENT_MSK_RBR_PRE_EMTY 8
242	#define RX_DMA_ENT_MSK_RCR_SHADOW_FULL 7
243	#define RX_DMA_ENT_MSK_CONFIG_ERR 6
244	#define RX_DMA_ENT_MSK_RCRINCON 5
245	#define RX_DMA_ENT_MSK_RCRFULL 4
246	#define RX_DMA_ENT_MSK_RBR_EMPTY 3
247	#define RX_DMA_ENT_MSK_RBRFULL 2
248	#define RX_DMA_ENT_MSK_RBRLOGPAGE 1
249	#define RX_DMA_ENT_MSK_CFIGLOGPAGE 0
250
251	// RX_DMA_CTL_STAT Register
252	#define RX_DMA_CTL_STAT_RBR_TMOUT 53
253	#define RX_DMA_CTL_STAT_RSP_CNT_ERR 52
254	#define RX_DMA_CTL_STAT_BYTE_EN_BUS 51
255	#define RX_DMA_CTL_STAT_RSP_DAT_ERR 50
256	#define RX_DMA_CTL_STAT_RCR_ACK_ERR 49
257	#define RX_DMA_CTL_STAT_DC_FIFO_ERR 48
258	#define RX_DMA_CTL_STAT_MEX 47
259	#define RX_DMA_CTL_STAT_RCRTHRES 46
260	#define RX_DMA_CTL_STAT_RCRTO 45
261	#define RX_DMA_CTL_STAT_RCR_SHA_PAR 44
262	#define RX_DMA_CTL_STAT_RBR_PRE_PAR 43
263	#define RX_DMA_CTL_STAT_PORT_DROP_PKT 42
264	#define RX_DMA_CTL_STAT_WRED_DROP 41
265	#define RX_DMA_CTL_STAT_RBR_PRE_EMTY 40
266	#define RX_DMA_CTL_STAT_RCR_SHADOW_FULL 39
267	#define RX_DMA_CTL_STAT_CONFIG_ERR 38
268	#define RX_DMA_CTL_STAT_RCRINCON 37
269	#define RX_DMA_CTL_STAT_RCRFULL 36
270	#define RX_DMA_CTL_STAT_RBR_EMPTY 35
271	#define RX_DMA_CTL_STAT_RBRFULL 34
272	#define RX_DMA_CTL_STAT_RBRLOGPAGE 33
273	#define RX_DMA_CTL_STAT_CFIGLOGPAGE 32
274
275	#define RX_DMA_CTL_STAT_PTRREAD 31:16
276	#define RX_DMA_CTL_STAT_PKTREAD 15:0
277
278	// RX_DMA_INTR_DEBUG Register
279	#define RX_DMA_INTR_DEBUG_RBR_TMOUT 53
280	#define RX_DMA_INTR_DEBUG_RSP_CNT_ERR 52
281	#define RX_DMA_INTR_DEBUG_BYTE_EN_BUS 51
282	#define RX_DMA_INTR_DEBUG_RSP_DAT_ERR 50
283	#define RX_DMA_INTR_DEBUG_RCR_ACK_ERR 49
284	#define RX_DMA_INTR_DEBUG_DC_FIFO_ERR 48
285	#define RX_DMA_INTR_DEBUG_MEX 47
286	#define RX_DMA_INTR_DEBUG_RCRTHRES 46
287	#define RX_DMA_INTR_DEBUG_RCRTO 45
288	#define RX_DMA_INTR_DEBUG_RCR_SHA_PAR 44
289	#define RX_DMA_INTR_DEBUG_RBR_PRE_PAR 43
290	#define RX_DMA_INTR_DEBUG_PORT_DROP_PKT 42
291	#define RX_DMA_INTR_DEBUG_WRED_DROP 41
292	#define RX_DMA_INTR_DEBUG_RBR_PRE_EMTY 40
293	#define RX_DMA_INTR_DEBUG_RCR_SHADOW_FULL 39
294	#define RX_DMA_INTR_DEBUG_CONFIG_ERR 38
295	#define RX_DMA_INTR_DEBUG_RCRINCON 37
296	#define RX_DMA_INTR_DEBUG_RCRFULL 36
297	#define RX_DMA_INTR_DEBUG_RBR_EMPTY 35
298	#define RX_DMA_INTR_DEBUG_RBRFULL 34
299	#define RX_DMA_INTR_DEBUG_RBRLOGPAGE 33
300	#define RX_DMA_INTR_DEBUG_CFIGLOGPAGE 32
301
302	#define RX_DMA_INTR_DEBUG_PTRREAD 31:16
303	#define RX_DMA_INTR_DEBUG_PKTREAD 15:0
304
305	#define RX_ADDR_MD_RAM_ACC 1
306
307	#define RDMC_MEM_ADDR_PRE_SHAD 8
308	#define RDMC_MEM_ADDR_PRE_ADDR 7:0