[OpenSPARC-T2-DV] / verif / env / niu / vera / niu_pio / include / ipp_memory_map.vri

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ipp_memory_map.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#include "neptune_memory_map.vri"

#define IPP_PORT_STEP                   16'h8000


#define IPP_CONFIG                      20'h0_0000
#define IPP_DISCARD_PKT_COUNTER         20'h0_0020
#define IPP_TCP_CHKSUM_ERR_COUNTER      20'h0_0028
#define IPP_ECC_ERR_COUNTER             20'h0_0030

// ox24 to ox34 are reserved for any new counters

#define IPP_INT_STATUS                  20'h0_0040
#define IPP_INT_MASK                    20'h0_0048

// 0x40 to 0x44 are reserved for future use

#define IPP_FIFO_RD_DATA_31_0           20'h0_0060
#define IPP_FIFO_RD_DATA_63_32          20'h0_0068
#define IPP_FIFO_RD_DATA_95_64          20'h0_0070
#define IPP_FIFO_RD_DATA_127_96         20'h0_0078
#define IPP_FIFO_RD_DATA_129_128        20'h0_0080

#define IPP_FIFO_WR_DATA_31_0           20'h0_0088
#define IPP_FIFO_WR_DATA_63_32          20'h0_0090
#define IPP_FIFO_WR_DATA_95_64          20'h0_0098
#define IPP_FIFO_WR_DATA_127_96         20'h0_00a0
#define IPP_FIFO_WR_DATA_129_128        20'h0_00a8

#define IPP_FIFO_READ_POINTER           20'h0_00b0
#define IPP_FIFO_WRITE_POINTER          20'h0_00b8

//#define IPP_POINTER_QUEUE0              20'h0_00c0
//#define IPP_POINTER_QUEUE1              20'h0_00c8
//#define IPP_POINTER_QUEUE2              20'h0_00d0
//#define IPP_POINTER_QUEUE3              20'h0_00d8
//#define IPP_POINTER_QUEUE4              20'h0_00e0
//#define IPP_POINTER_QUEUE5              20'h0_00e8
//#define IPP_POINTER_QUEUE6              20'h0_00f0
//#define IPP_POINTER_QUEUE7              20'h0_00f8

#define IPP_STATE_MACHINE0              20'h0_0080
#define IPP_STATE_MACHINE1              20'h0_0084


// 0x88 to 0x90 are added for fflp decision bypass
#define IPP_DECISION_REG1               20'h0_0110
#define IPP_DECISION_REG2               20'h0_0118
#define IPP_DECISION_REG3               20'h0_0120
#define IPP_DEBUG_REG                   20'h0_0128


// more defines for IPP
#define IPP_DFIFO_RD_PTR		20'h0_0110
#define IPP_DFIFO_WR_PTR		20'h0_0118

// BASE ADDRESS FOR EACH IPP BLOCK

#define IPP0_BASE       (IPP_ADDRESS_RANGE + IPP_0_RANGE)
#define IPP1_BASE       (IPP_ADDRESS_RANGE + IPP_1_RANGE)
#define IPP2_BASE       (IPP_ADDRESS_RANGE + IPP_2_RANGE)
#define IPP3_BASE       (IPP_ADDRESS_RANGE + IPP_3_RANGE)

// BIT DEFINES FOR IPP_INT_STAT AND IPP_INT_MSK REGISTERS

#define IPP_MASK_ECC_ERR_MX 	7
#define IPP_MASK_DFIFO_EOP_SOP 	6
#define IPP_MASK_DFIFO_UC 	5
#define IPP_MASK_PFIFO_PAR 	4
#define IPP_MASK_PFIFO_OVER 	3
#define IPP_MASK_PFIFO_UND 	2
#define IPP_MASK_BAD_CS 	1
#define IPP_MASK_PKT_DIS_CNT 	0

#define IPP_STAT_SOP_MISS 	31	// corresponds to MASK 6
#define IPP_STAT_EOP_MISS 	30	// corresponds to MASK 6
#define IPP_STAT_DFIFO_UE 	29:28	// corresponds to MASK 5
#define IPP_STAT_DFIFO_CE 	27:26
#define IPP_STAT_DFIFO_ECC 	25:24
#define IPP_STAT_DFIFO_ECC_ID 	22:12
#define IPP_STAT_PFIFO_PERR 	11	// corresponds to MASK 4
#define IPP_STAT_ECC_ERR_MA 	10	// corresponds to MASK 7
#define IPP_STAT_PFIFO_ERR_ID 	9:4
#define IPP_STAT_PFIFO_OVER 	3	// corresponds to MASK 3
#define IPP_STAT_PFIFO_UND 	2	// corresponds to MASK 2
#define IPP_STAT_BAD_CS_MX 	1	// corresponds to MASK 1
#define IPP_STAT_PKT_DIS_MX 	0	// corresponds to MASK 0
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: ipp_memory_map.vri
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	#include "neptune_memory_map.vri"
	36
	37	#define IPP_PORT_STEP 16'h8000
	38
	39
	40	#define IPP_CONFIG 20'h0_0000
	41	#define IPP_DISCARD_PKT_COUNTER 20'h0_0020
	42	#define IPP_TCP_CHKSUM_ERR_COUNTER 20'h0_0028
	43	#define IPP_ECC_ERR_COUNTER 20'h0_0030
	44
	45	// ox24 to ox34 are reserved for any new counters
	46
	47	#define IPP_INT_STATUS 20'h0_0040
	48	#define IPP_INT_MASK 20'h0_0048
	49
	50	// 0x40 to 0x44 are reserved for future use
	51
	52	#define IPP_FIFO_RD_DATA_31_0 20'h0_0060
	53	#define IPP_FIFO_RD_DATA_63_32 20'h0_0068
	54	#define IPP_FIFO_RD_DATA_95_64 20'h0_0070
	55	#define IPP_FIFO_RD_DATA_127_96 20'h0_0078
	56	#define IPP_FIFO_RD_DATA_129_128 20'h0_0080
	57
	58	#define IPP_FIFO_WR_DATA_31_0 20'h0_0088
	59	#define IPP_FIFO_WR_DATA_63_32 20'h0_0090
	60	#define IPP_FIFO_WR_DATA_95_64 20'h0_0098
	61	#define IPP_FIFO_WR_DATA_127_96 20'h0_00a0
	62	#define IPP_FIFO_WR_DATA_129_128 20'h0_00a8
	63
	64	#define IPP_FIFO_READ_POINTER 20'h0_00b0
65	#define IPP_FIFO_WRITE_POINTER 20'h0_00b8
66
67	//#define IPP_POINTER_QUEUE0 20'h0_00c0
68	//#define IPP_POINTER_QUEUE1 20'h0_00c8
69	//#define IPP_POINTER_QUEUE2 20'h0_00d0
70	//#define IPP_POINTER_QUEUE3 20'h0_00d8
71	//#define IPP_POINTER_QUEUE4 20'h0_00e0
72	//#define IPP_POINTER_QUEUE5 20'h0_00e8
73	//#define IPP_POINTER_QUEUE6 20'h0_00f0
74	//#define IPP_POINTER_QUEUE7 20'h0_00f8
75
76	#define IPP_STATE_MACHINE0 20'h0_0080
77	#define IPP_STATE_MACHINE1 20'h0_0084
78
79
80	// 0x88 to 0x90 are added for fflp decision bypass
81	#define IPP_DECISION_REG1 20'h0_0110
82	#define IPP_DECISION_REG2 20'h0_0118
83	#define IPP_DECISION_REG3 20'h0_0120
84	#define IPP_DEBUG_REG 20'h0_0128
85
86
87	// more defines for IPP
88	#define IPP_DFIFO_RD_PTR 20'h0_0110
89	#define IPP_DFIFO_WR_PTR 20'h0_0118
90
91	// BASE ADDRESS FOR EACH IPP BLOCK
92
93	#define IPP0_BASE (IPP_ADDRESS_RANGE + IPP_0_RANGE)
94	#define IPP1_BASE (IPP_ADDRESS_RANGE + IPP_1_RANGE)
95	#define IPP2_BASE (IPP_ADDRESS_RANGE + IPP_2_RANGE)
96	#define IPP3_BASE (IPP_ADDRESS_RANGE + IPP_3_RANGE)
97
98	// BIT DEFINES FOR IPP_INT_STAT AND IPP_INT_MSK REGISTERS
99
100	#define IPP_MASK_ECC_ERR_MX 7
101	#define IPP_MASK_DFIFO_EOP_SOP 6
102	#define IPP_MASK_DFIFO_UC 5
103	#define IPP_MASK_PFIFO_PAR 4
104	#define IPP_MASK_PFIFO_OVER 3
105	#define IPP_MASK_PFIFO_UND 2
106	#define IPP_MASK_BAD_CS 1
107	#define IPP_MASK_PKT_DIS_CNT 0
108
109	#define IPP_STAT_SOP_MISS 31 // corresponds to MASK 6
110	#define IPP_STAT_EOP_MISS 30 // corresponds to MASK 6
111	#define IPP_STAT_DFIFO_UE 29:28 // corresponds to MASK 5
112	#define IPP_STAT_DFIFO_CE 27:26
113	#define IPP_STAT_DFIFO_ECC 25:24
114	#define IPP_STAT_DFIFO_ECC_ID 22:12
115	#define IPP_STAT_PFIFO_PERR 11 // corresponds to MASK 4
116	#define IPP_STAT_ECC_ERR_MA 10 // corresponds to MASK 7
117	#define IPP_STAT_PFIFO_ERR_ID 9:4
118	#define IPP_STAT_PFIFO_OVER 3 // corresponds to MASK 3
119	#define IPP_STAT_PFIFO_UND 2 // corresponds to MASK 2
120	#define IPP_STAT_BAD_CS_MX 1 // corresponds to MASK 1
121	#define IPP_STAT_PKT_DIS_MX 0 // corresponds to MASK 0
122