[OpenSPARC-T2-DV] / verif / env / niu / vera / niu_pio / include / neptune_memory_map.vri

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: neptune_memory_map.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#define  ADDRESS_RANGE_MASK   32'h01FF_0000

   // In case of N2, the base address is 0x8100000000
   #define NIU_BASE_ADDRESS 40'h8100000000

#define NEPTUNE_BASE_ADDRESS  NIU_BASE_ADDRESS

/* PIO Block */
#define PIO_BASE_ADDRESS 	24'h000000
#define FZC_PIO_BASE_ADDRESS	24'h080000 

/*PIO Virtual DMA Address */
#define PIO_VADDR_BASE_ADDR 24'h400000 


/* MAC BLOCK:  0x18_0000 - 0x18_FFFF */
#define FZC_MAC_BASE_ADDRESS	24'h180000 
/* IPP BLOCK:  0x28_0000 - 0x28_FFFF */
#define FZC_IPP_BASE_ADDRESS	24'h280000 
/* FFLP BLOCK:  0x38_0000 - 0x37_FFFF */
#define FFLP_BASE_ADDRESS	24'h300000 
/* FFLP BLOCK:  0x38_0000 - 0x38_FFFF */
#define FZC_FFLP_BASE_ADDRESS	24'h380000 
#define FZC_FFLP_BASE_OFFSET	24'h020000 
#define FZC_FFLP_BASE_OFFSET1   24'h040000
/* ZCP BLOCK:  0x50_0000 - 0x57_FFFF */
#define ZCP_BASE_ADDRESS	24'h500000 
/* ZCP BLOCK:  0x58_0000 - 0x58_FFFF */
#define FZC_ZCP_BASE_ADDRESS	24'h580000 
#define DMC_BASE_ADDRESS	24'h600000 
#define FZC_DMC_BASE_ADDRESS	24'h680000 
#define TXC_BASE_ADDRESS	24'h700000 
#define FZC_TXC_BASE_ADDRESS	24'h780000 
#define FZC_PROM_BASE_ADDRESS	24'hC80000

#define PIO_LDSV_BASE_ADDRESS	24'h800000 
#define PIO_LDGIM_BASE_ADDRESS	24'h900000 
#define PIO_IMASK0_BASE_ADDRESS	24'hA00000 
#define PIO_IMASK1_BASE_ADDRESS	24'hB00000 


/* Many address ranges are subdivided by port.
   For each port, there is an identical memory
   map.  To determine the port subdivision, the
   original address is masked with PORT_RANGE_MASK.
   A compare-to register is initialized to zero.
   This compare-to register is compared to the
   result of masking the original address - a
   compare indicates port 0.  The compare_to
   register is incremented by PORT_OFFSET
   to check for port 1. This process is repeated
   for each port.

   When using memory references associated with
   a particular port, add the offset of the port
   number to the base address:
   (XXX_STATUS_REG + port_num*PORT_OFFSET)

   The port range values are used by the pio fake
   module and the shadow space module.
*/

#define  MAC_ADDRESS_RANGE  	NEPTUNE_BASE_ADDRESS + FZC_MAC_BASE_ADDRESS   
#define  IPP_ADDRESS_RANGE  	NEPTUNE_BASE_ADDRESS + FZC_IPP_BASE_ADDRESS   

#define  TXC_ADDRESS_RANGE  	NEPTUNE_BASE_ADDRESS + TXC_BASE_ADDRESS   
#define  FZC_TXC_ADDRESS_RANGE  NEPTUNE_BASE_ADDRESS + FZC_TXC_BASE_ADDRESS   


#define DMC_ADDRESS_RANGE   	NEPTUNE_BASE_ADDRESS + DMC_BASE_ADDRESS
#define FZC_DMC_ADDRESS_RANGE   NEPTUNE_BASE_ADDRESS + FZC_DMC_BASE_ADDRESS

#define FFLP_VLAN_TBL_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + FZC_FFLP_BASE_ADDRESS
#define FFLP_ADDRESS_RANGE      NEPTUNE_BASE_ADDRESS + FZC_FFLP_BASE_ADDRESS + \
                                FZC_FFLP_BASE_OFFSET 
#define FFLP_HASH_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + FFLP_BASE_ADDRESS

#define FFLP_FLOW_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + FZC_FFLP_BASE_ADDRESS + \
                                FZC_FFLP_BASE_OFFSET1

#define ZCP_ADDRESS_RANGE       NEPTUNE_BASE_ADDRESS + ZCP_BASE_ADDRESS
#define FZC_ZCP_ADDRESS_RANGE   NEPTUNE_BASE_ADDRESS +  FZC_ZCP_BASE_ADDRESS
#define FZC_PROM_ADDRESS_RANGE   NEPTUNE_BASE_ADDRESS +  FZC_PROM_BASE_ADDRESS 

#define PIO_BASE_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + PIO_BASE_ADDRESS
#define FZC_PIO_BASE_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + FZC_PIO_BASE_ADDRESS
#define PIO_VADDR_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + PIO_VADDR_BASE_ADDR

#define PIO_LDSV_BASE_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + PIO_LDSV_BASE_ADDRESS
#define PIO_LDGIM_BASE_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + PIO_LDGIM_BASE_ADDRESS
#define PIO_IMASK0_BASE_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + PIO_IMASK0_BASE_ADDRESS
#define PIO_IMASK1_BASE_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + PIO_IMASK1_BASE_ADDRESS

#define FUNC0_MNT NEPTUNE_BASE_ADDRESS + 40'h000_0000
#define FUNC0_VIR NEPTUNE_BASE_ADDRESS + 40'h100_0000
#define FUNC1_MNT NEPTUNE_BASE_ADDRESS + 40'h200_0000
#define FUNC1_VIR NEPTUNE_BASE_ADDRESS + 40'h300_0000
#define FUNC2_MNT NEPTUNE_BASE_ADDRESS + 40'h400_0000
#define FUNC2_VIR NEPTUNE_BASE_ADDRESS + 40'h500_0000
#define FUNC3_MNT NEPTUNE_BASE_ADDRESS + 40'h600_0000
#define FUNC3_VIR NEPTUNE_BASE_ADDRESS + 40'h700_0000

/*MAC Sub Blocks */

#define  PORT_RANGE_MASK   32'h0000_F000
#define  PORT_OFFSET       32'h0000_1000
#define  PORT_0_RANGE      32'h0000_0000 
#define  XPCS_0_RANGE      (32'h0000_1000 << 1) 
#define  PCS_0_RANGE       (32'h0000_2000 << 1) 
#define  PORT_1_RANGE      (32'h0000_3000 << 1) 
#define  XPCS_1_RANGE      (32'h0000_4000 << 1) 
#define  PCS_1_RANGE       (32'h0000_5000 << 1) 
#define  PORT_2_RANGE      (32'h0000_6000 << 1)
#define  PCS_2_RANGE       (32'h0000_7000 << 1) 
#define  PORT_3_RANGE      (32'h0000_8000 << 1) 
#define  PCS_3_RANGE       (32'h0000_9000 << 1) 
#define  ESER_RANGE        (32'h0000_a000 << 1) 
#define  MIF_RANGE         (32'h0000_b000 << 1) 


/*IPP Ports */

#define  IPP_0_RANGE      32'h0000_0000 
#define  IPP_2_RANGE      32'h0000_4000 
#define  IPP_1_RANGE      32'h0000_8000 
#define  IPP_3_RANGE      32'h0000_c000
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: neptune_memory_map.vri
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	#define ADDRESS_RANGE_MASK 32'h01FF_0000
	36
	37	// In case of N2, the base address is 0x8100000000
	38	#define NIU_BASE_ADDRESS 40'h8100000000
	39
	40	#define NEPTUNE_BASE_ADDRESS NIU_BASE_ADDRESS
	41
	42	/* PIO Block */
	43	#define PIO_BASE_ADDRESS 24'h000000
	44	#define FZC_PIO_BASE_ADDRESS 24'h080000
	45
	46	/PIO Virtual DMA Address /
	47	#define PIO_VADDR_BASE_ADDR 24'h400000
	48
	49
	50	/* MAC BLOCK: 0x18_0000 - 0x18_FFFF */
	51	#define FZC_MAC_BASE_ADDRESS 24'h180000
	52	/* IPP BLOCK: 0x28_0000 - 0x28_FFFF */
	53	#define FZC_IPP_BASE_ADDRESS 24'h280000
	54	/* FFLP BLOCK: 0x38_0000 - 0x37_FFFF */
	55	#define FFLP_BASE_ADDRESS 24'h300000
	56	/* FFLP BLOCK: 0x38_0000 - 0x38_FFFF */
	57	#define FZC_FFLP_BASE_ADDRESS 24'h380000
	58	#define FZC_FFLP_BASE_OFFSET 24'h020000
	59	#define FZC_FFLP_BASE_OFFSET1 24'h040000
	60	/* ZCP BLOCK: 0x50_0000 - 0x57_FFFF */
	61	#define ZCP_BASE_ADDRESS 24'h500000
	62	/* ZCP BLOCK: 0x58_0000 - 0x58_FFFF */
	63	#define FZC_ZCP_BASE_ADDRESS 24'h580000
	64	#define DMC_BASE_ADDRESS 24'h600000
65	#define FZC_DMC_BASE_ADDRESS 24'h680000
66	#define TXC_BASE_ADDRESS 24'h700000
67	#define FZC_TXC_BASE_ADDRESS 24'h780000
68	#define FZC_PROM_BASE_ADDRESS 24'hC80000
69
70	#define PIO_LDSV_BASE_ADDRESS 24'h800000
71	#define PIO_LDGIM_BASE_ADDRESS 24'h900000
72	#define PIO_IMASK0_BASE_ADDRESS 24'hA00000
73	#define PIO_IMASK1_BASE_ADDRESS 24'hB00000
74
75
76
77
78	/* Many address ranges are subdivided by port.
79	For each port, there is an identical memory
80	map. To determine the port subdivision, the
81	original address is masked with PORT_RANGE_MASK.
82	A compare-to register is initialized to zero.
83	This compare-to register is compared to the
84	result of masking the original address - a
85	compare indicates port 0. The compare_to
86	register is incremented by PORT_OFFSET
87	to check for port 1. This process is repeated
88	for each port.
89
90	When using memory references associated with
91	a particular port, add the offset of the port
92	number to the base address:
93	(XXX_STATUS_REG + port_num*PORT_OFFSET)
94
95	The port range values are used by the pio fake
96	module and the shadow space module.
97	*/
98
99	#define MAC_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + FZC_MAC_BASE_ADDRESS
100	#define IPP_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + FZC_IPP_BASE_ADDRESS
101
102	#define TXC_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + TXC_BASE_ADDRESS
103	#define FZC_TXC_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + FZC_TXC_BASE_ADDRESS
104
105
106	#define DMC_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + DMC_BASE_ADDRESS
107	#define FZC_DMC_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + FZC_DMC_BASE_ADDRESS
108
109	#define FFLP_VLAN_TBL_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + FZC_FFLP_BASE_ADDRESS
110	#define FFLP_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + FZC_FFLP_BASE_ADDRESS + \
111	FZC_FFLP_BASE_OFFSET
112	#define FFLP_HASH_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + FFLP_BASE_ADDRESS
113
114	#define FFLP_FLOW_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + FZC_FFLP_BASE_ADDRESS + \
115	FZC_FFLP_BASE_OFFSET1
116
117	#define ZCP_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + ZCP_BASE_ADDRESS
118	#define FZC_ZCP_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + FZC_ZCP_BASE_ADDRESS
119	#define FZC_PROM_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + FZC_PROM_BASE_ADDRESS
120
121	#define PIO_BASE_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + PIO_BASE_ADDRESS
122	#define FZC_PIO_BASE_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + FZC_PIO_BASE_ADDRESS
123	#define PIO_VADDR_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + PIO_VADDR_BASE_ADDR
124
125	#define PIO_LDSV_BASE_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + PIO_LDSV_BASE_ADDRESS
126	#define PIO_LDGIM_BASE_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + PIO_LDGIM_BASE_ADDRESS
127	#define PIO_IMASK0_BASE_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + PIO_IMASK0_BASE_ADDRESS
128	#define PIO_IMASK1_BASE_ADDRESS_RANGE NEPTUNE_BASE_ADDRESS + PIO_IMASK1_BASE_ADDRESS
129
130	#define FUNC0_MNT NEPTUNE_BASE_ADDRESS + 40'h000_0000
131	#define FUNC0_VIR NEPTUNE_BASE_ADDRESS + 40'h100_0000
132	#define FUNC1_MNT NEPTUNE_BASE_ADDRESS + 40'h200_0000
133	#define FUNC1_VIR NEPTUNE_BASE_ADDRESS + 40'h300_0000
134	#define FUNC2_MNT NEPTUNE_BASE_ADDRESS + 40'h400_0000
135	#define FUNC2_VIR NEPTUNE_BASE_ADDRESS + 40'h500_0000
136	#define FUNC3_MNT NEPTUNE_BASE_ADDRESS + 40'h600_0000
137	#define FUNC3_VIR NEPTUNE_BASE_ADDRESS + 40'h700_0000
138
139	/MAC Sub Blocks /
140
141	#define PORT_RANGE_MASK 32'h0000_F000
142	#define PORT_OFFSET 32'h0000_1000
143	#define PORT_0_RANGE 32'h0000_0000
144	#define XPCS_0_RANGE (32'h0000_1000 << 1)
145	#define PCS_0_RANGE (32'h0000_2000 << 1)
146	#define PORT_1_RANGE (32'h0000_3000 << 1)
147	#define XPCS_1_RANGE (32'h0000_4000 << 1)
148	#define PCS_1_RANGE (32'h0000_5000 << 1)
149	#define PORT_2_RANGE (32'h0000_6000 << 1)
150	#define PCS_2_RANGE (32'h0000_7000 << 1)
151	#define PORT_3_RANGE (32'h0000_8000 << 1)
152	#define PCS_3_RANGE (32'h0000_9000 << 1)
153	#define ESER_RANGE (32'h0000_a000 << 1)
154	#define MIF_RANGE (32'h0000_b000 << 1)
155
156
157	/IPP Ports /
158
159	#define IPP_0_RANGE 32'h0000_0000
160	#define IPP_2_RANGE 32'h0000_4000
161	#define IPP_1_RANGE 32'h0000_8000
162	#define IPP_3_RANGE 32'h0000_c000
163