Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / niu / vera / niu_pio / include / pio_memory_map.vri
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: pio_memory_map.vri
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include "neptune_memory_map.vri"
36
37#define DEV_FUNC_SR PIO_BASE_ADDRESS_RANGE + 20'h10000
38#define MULTI_PART_CTL FZC_PIO_BASE_ADDRESS_RANGE +20'h0
39#define DMA_BIND FZC_PIO_BASE_ADDRESS_RANGE +20'h10000
40#define LDG_NUM FZC_PIO_BASE_ADDRESS_RANGE +20'h20000
41#define LDSV0 PIO_LDSV_BASE_ADDRESS_RANGE + 20'h00000
42#define LDSV1 PIO_LDSV_BASE_ADDRESS_RANGE + 20'h00008
43#define LDSV2 PIO_LDSV_BASE_ADDRESS_RANGE + 20'h00010
44#define LD_IM0 PIO_IMASK0_BASE_ADDRESS_RANGE + 20'h00000
45#define LD_IM1 PIO_IMASK1_BASE_ADDRESS_RANGE + 20'h00000
46#define LDGIMGN PIO_LDSV_BASE_ADDRESS_RANGE + 20'h00018
47#define LDGITMRES FZC_PIO_BASE_ADDRESS_RANGE + 20'h00008
48#define NIU_SID FZC_PIO_BASE_ADDRESS_RANGE + 20'h10200
49#define RST_CTL FZC_PIO_BASE_ADDRESS_RANGE + 20'h00038
50#define SYS_ERR_MASK FZC_PIO_BASE_ADDRESS_RANGE + 20'h00090
51#define SYS_ERR_STAT FZC_PIO_BASE_ADDRESS_RANGE + 20'h00098
52#define DIRTY_TID_CTL FZC_PIO_BASE_ADDRESS_RANGE +20'h00010
53#define DIRTY_TID_STAT FZC_PIO_BASE_ADDRESS_RANGE +20'h00018
54#define SMX_CFIG_DAT FZC_PIO_BASE_ADDRESS_RANGE + 20'h00040
55#define SMX_INT_STAT FZC_PIO_BASE_ADDRESS_RANGE + 20'h00048
56#define SMX_CTL FZC_PIO_BASE_ADDRESS_RANGE + 20'h00050
57#define SMX_DBG_VEC FZC_PIO_BASE_ADDRESS_RANGE + 20'h00058
58