Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / niu / vera / smx_drv / include / niu_rxc_mon.if.vri
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_rxc_mon.if.vri
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
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30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#ifdef NIU_GATE
36 // Do nothing
37#else
38
39#ifndef NIU_RXC_IF
40#define NIU_RXC_IF
41
42#define OUTPUT_EDGE PHOLD
43#define INPUT_EDGE PSAMPLE #-1
44#define OUTPUT_SKEW #1
45
46#define NIU_RXC_PATH NIU_DUV_PATH.rtx.rxc
47
48interface mac_ipp_ports_if
49{
50 input clk CLOCK verilog_node NIU_RXC_PATH.niu_clk";
51
52 input rxc_mac_req0 INPUT_EDGE verilog_node NIU_RXC_PATH.rxc_mac_req0";
53 input mac_rxc_tag0 INPUT_EDGE verilog_node NIU_RXC_PATH.mac_rxc_tag0";
54 input mac_rxc_ack0 INPUT_EDGE verilog_node NIU_RXC_PATH.mac_rxc_ack0";
55 input [63:0] mac_rxc_data0 INPUT_EDGE verilog_node NIU_RXC_PATH.mac_rxc_data0";
56 input mac_rxc_ctrl0 INPUT_EDGE verilog_node NIU_RXC_PATH.mac_rxc_ctrl0";
57 input [22:0] mac_rxc_stat0 INPUT_EDGE verilog_node NIU_RXC_PATH.mac_rxc_stat0";
58
59 input rxc_mac_req1 INPUT_EDGE verilog_node NIU_RXC_PATH.rxc_mac_req1";
60 input mac_rxc_tag1 INPUT_EDGE verilog_node NIU_RXC_PATH.mac_rxc_tag1";
61 input mac_rxc_ack1 INPUT_EDGE verilog_node NIU_RXC_PATH.mac_rxc_ack1";
62 input [63:0] mac_rxc_data1 INPUT_EDGE verilog_node NIU_RXC_PATH.mac_rxc_data1";
63 input mac_rxc_ctrl1 INPUT_EDGE verilog_node NIU_RXC_PATH.mac_rxc_ctrl1";
64 input [22:0] mac_rxc_stat1 INPUT_EDGE verilog_node NIU_RXC_PATH.mac_rxc_stat1";
65
66}
67
68port mac_ipp_port
69{
70 clk;
71 req;
72 tag;
73 ack;
74 data;
75 ctrl;
76 stat;
77}
78
79bind mac_ipp_port mac_ipp_port0_bind
80{
81 clk mac_ipp_ports_if.clk;
82 req mac_ipp_ports_if.rxc_mac_req0;
83 tag mac_ipp_ports_if.mac_rxc_tag0;
84 ack mac_ipp_ports_if.mac_rxc_ack0;
85 data mac_ipp_ports_if.mac_rxc_data0;
86 ctrl mac_ipp_ports_if.mac_rxc_ctrl0;
87 stat mac_ipp_ports_if.mac_rxc_stat0;
88}
89
90bind mac_ipp_port mac_ipp_port1_bind
91{
92 clk mac_ipp_ports_if.clk;
93 req mac_ipp_ports_if.rxc_mac_req1;
94 tag mac_ipp_ports_if.mac_rxc_tag1;
95 ack mac_ipp_ports_if.mac_rxc_ack1;
96 data mac_ipp_ports_if.mac_rxc_data1;
97 ctrl mac_ipp_ports_if.mac_rxc_ctrl1;
98 stat mac_ipp_ports_if.mac_rxc_stat1;
99}
100
101
102#endif // NIU_RXC_IF
103#endif // if NIU_GATE... else...endif
104
105// End