Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / tcu / tcu_top.h
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1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: tcu_top.h
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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37*/
38`ifdef PALLADIUM
39`else
40`timescale 1ps/1ps
41`endif
42
43`ifdef TOP
44// External environment should specify TOP
45`else
46`define TOP tb_top
47`endif
48
49// Dispmon defines (See also N2 :/verif/env/common/verilog/misc)
50`include "dispmonDefines.vh"
51
52
53// These defines are used for all environments (TCU_SAT, FC, DFT_SAT)
54`define TCK_HALF_PERIOD 25400 // ps., 20Mhz == 50000ps 19.7Mhz = 25400
55`define SYS_HALF_PERIOD 2500 // ps., 200Mhz == 5000ps
56
57// Monitors and aids to 0-in
58`define MONTCU `TOP.tcu_mon // Verilog DUT monitors
59`define MONCCU `TOP.ccu_mon // Verilog DUT monitors
60`define MONRST `TOP.rst_mon // Verilog DUT monitors
61
62`ifdef TCU_SAT
63// These are used in the verilog finishVera() call
64`ifdef DFT_CFG
65`define TOP_SHELL dft_top_shell
66`else
67`define TOP_SHELL tcu_top_shell
68`endif
69
70// Timeout for simulation
71`define TOP_MAX_CYCLE 50_000
72
73// These should be defined in higher level simulation
74`define CPU `TOP.cpu // Chip level
75`define TCU `CPU.tcu // Test control unit
76`define CCU `CPU.ccu // Clock control unit
77`define RST `CPU.rst // Reset logic unit
78`define EFU `CPU.efu // Electronic fuse unit
79`define NCU `CPU.ncu // Non-cacheable unit
80`define SII `CPU.sii // sii unit
81`define SIO `CPU.sio // sio unit
82
83`endif