verif/env/tcu/tcu_top.h

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* OpenSPARC T2 Processor File: tcu_top.h
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`ifdef PALLADIUM
`else
`timescale      1ps/1ps
`endif

`ifdef TOP
// External environment should specify TOP
`else
`define TOP     tb_top
`endif

// Dispmon defines (See also N2 :/verif/env/common/verilog/misc)
`include "dispmonDefines.vh"


// These defines are used for all environments (TCU_SAT, FC, DFT_SAT)
`define TCK_HALF_PERIOD     25400    // ps., 20Mhz  == 50000ps 19.7Mhz = 25400
`define SYS_HALF_PERIOD      2500    // ps., 200Mhz == 5000ps

// Monitors and aids to 0-in
`define MONTCU  `TOP.tcu_mon    // Verilog DUT monitors
`define MONCCU  `TOP.ccu_mon    // Verilog DUT monitors
`define MONRST  `TOP.rst_mon    // Verilog DUT monitors

`ifdef TCU_SAT
// These are used in the verilog finishVera() call
`ifdef DFT_CFG
`define TOP_SHELL dft_top_shell
`else
`define TOP_SHELL tcu_top_shell
`endif

// Timeout for simulation
`define TOP_MAX_CYCLE      50_000

// These should be defined in higher level simulation
`define CPU     `TOP.cpu    // Chip level
`define TCU     `CPU.tcu    // Test control unit
`define CCU     `CPU.ccu    // Clock control unit
`define RST     `CPU.rst    // Reset logic unit
`define EFU     `CPU.efu    // Electronic fuse unit
`define NCU     `CPU.ncu    // Non-cacheable unit
`define SII     `CPU.sii    // sii unit
`define SIO     `CPU.sio    // sio unit

`endif