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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ccu.if.vri | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #ifndef INC_CCU_IF_VRI | |
36 | #define INC_CCU_IF_VRI | |
37 | ||
38 | #include "fc_top_defines.vri" | |
39 | ||
40 | //====================================================== | |
41 | //=== define one Vera interface for each signal ==== | |
42 | //=== (ie. each signal is a VERA CLOCK) ==== | |
43 | //=== Naming convention: prepend 'ccu_' if signal ==== | |
44 | //=== does not start with "ccu_" ==== | |
45 | //====================================================== | |
46 | ||
47 | interface ccu_pll_sys_clk_p_if { | |
48 | input pll_sys_clk_p CLOCK verilog_node "`CCU.pll_sys_clk_p"; | |
49 | } | |
50 | ||
51 | interface ccu_cmp_pll_clk_if { | |
52 | input cmp_pll_clk CLOCK verilog_node "`CCU.cmp_pll_clk"; | |
53 | } | |
54 | ||
55 | interface ccu_rst_ccu_pll_if { | |
56 | input rst_ccu_pll_ CLOCK verilog_node "`CCU.rst_ccu_pll_"; | |
57 | } | |
58 | ||
59 | interface ccu_io2x_out_if { | |
60 | input ccu_io2x_out CLOCK verilog_node "`CCU.ccu_io2x_out"; | |
61 | } | |
62 | ||
63 | #ifndef GATESIM | |
64 | interface ccu_rst_sys_clk_if { | |
65 | input ccu_rst_sys_clk CLOCK verilog_node "`CCU.ccu_rst_sys_clk"; | |
66 | } | |
67 | ||
68 | interface ccu_gclk_if { | |
69 | input gclk CLOCK verilog_node "`CCU.gclk"; | |
70 | } | |
71 | ||
72 | interface ccu_dr_pll_clk_if { | |
73 | input dr_pll_clk CLOCK verilog_node "`CCU.dr_pll_clk"; | |
74 | } | |
75 | ||
76 | interface ccu_io_out_if { | |
77 | input ccu_io_out CLOCK verilog_node "`CCU.ccu_io_out"; | |
78 | } | |
79 | ||
80 | interface ccu_cmp_io_sync_en_if { | |
81 | input ccu_cmp_io_sync_en CLOCK verilog_node "`CCU.ccu_cmp_io_sync_en"; | |
82 | } | |
83 | ||
84 | interface ccu_io_cmp_sync_en_if { | |
85 | input ccu_io_cmp_sync_en CLOCK verilog_node "`CCU.ccu_io_cmp_sync_en"; | |
86 | } | |
87 | ||
88 | interface ccu_dr_sync_en_if { | |
89 | input ccu_dr_sync_en CLOCK verilog_node "`CCU.ccu_dr_sync_en"; | |
90 | } | |
91 | ||
92 | interface ccu_io2x_sync_en_if { | |
93 | input ccu_io2x_sync_en CLOCK verilog_node "`CCU.ccu_io2x_sync_en"; | |
94 | } | |
95 | ||
96 | interface ccu_cmp_sys_sync_en_if { | |
97 | input ccu_cmp_sys_sync_en CLOCK verilog_node "`CCU.ccu_cmp_sys_sync_en"; | |
98 | } | |
99 | ||
100 | interface ccu_sys_cmp_sync_en_if { | |
101 | input ccu_sys_cmp_sync_en CLOCK verilog_node "`CCU.ccu_sys_cmp_sync_en"; | |
102 | } | |
103 | ||
104 | interface ccu_rst_ccu_if { | |
105 | input rst_ccu_ CLOCK verilog_node "`CCU.rst_ccu_"; | |
106 | } | |
107 | ||
108 | interface ccu_rst_sync_stable_if { | |
109 | input ccu_rst_sync_stable CLOCK verilog_node "`CCU.ccu_rst_sync_stable"; | |
110 | } | |
111 | ||
112 | interface ccu_rst_change_if { | |
113 | input ccu_rst_change CLOCK verilog_node "`CCU.ccu_rst_change"; | |
114 | } | |
115 | ||
116 | interface ccu_vco_aligned_if { | |
117 | input ccu_vco_aligned CLOCK verilog_node "`CCU.ccu_vco_aligned"; | |
118 | } | |
119 | ||
120 | interface ccu_gclk_aligned_if { | |
121 | input gclk_aligned CLOCK verilog_node "`CCU.gclk_aligned"; | |
122 | } | |
123 | ||
124 | interface gl_ccu_clk_stop_if { | |
125 | input gl_ccu_clk_stop CLOCK verilog_node "`CCU.gl_ccu_clk_stop"; | |
126 | } | |
127 | ||
128 | interface gl_ccu_io_clk_stop_if { | |
129 | input gl_ccu_io_clk_stop CLOCK verilog_node "`CCU.gl_ccu_io_clk_stop"; | |
130 | } | |
131 | ||
132 | interface tcu_atpg_mode_if { | |
133 | input tcu_atpg_mode CLOCK verilog_node "`CCU.tcu_atpg_mode"; | |
134 | } | |
135 | ||
136 | interface ccu_ref_clk_if { | |
137 | input ref_clk CLOCK verilog_node "`CCU.ref_clk"; | |
138 | } | |
139 | ||
140 | #endif | |
141 | //====================================================== | |
142 | //=== Monitor interface | |
143 | //====================================================== | |
144 | #ifndef GATESIM | |
145 | interface ccu_mon_if { | |
146 | input cmp_pll_clk CLOCK verilog_node "`CCU.cmp_pll_clk"; | |
147 | ||
148 | input ccu_cmp_io_sync_en PSAMPLE #-1 verilog_node "`CCU.ccu_cmp_io_sync_en"; | |
149 | input ccu_cmp_sys_sync_en PSAMPLE #-1 verilog_node "`CCU.ccu_cmp_sys_sync_en"; | |
150 | input ccu_dbg1_serdes_dtm PSAMPLE #-1 verilog_node "`CCU.ccu_dbg1_serdes_dtm"; | |
151 | input ccu_dr_sync_en PSAMPLE #-1 verilog_node "`CCU.ccu_dr_sync_en"; | |
152 | input ccu_io2x_out PSAMPLE #-1 verilog_node "`CCU.ccu_io2x_out"; | |
153 | input ccu_io2x_sync_en PSAMPLE #-1 verilog_node "`CCU.ccu_io2x_sync_en"; | |
154 | input ccu_io_cmp_sync_en PSAMPLE #-1 verilog_node "`CCU.ccu_io_cmp_sync_en"; | |
155 | input ccu_io_out PSAMPLE #-1 verilog_node "`CCU.ccu_io_out"; | |
156 | input [1:0] ccu_mio_pll_char_out PSAMPLE #-1 verilog_node "`CCU.ccu_mio_pll_char_out"; | |
157 | input ccu_mio_serdes_dtm PSAMPLE #-1 verilog_node "`CCU.ccu_mio_serdes_dtm"; | |
158 | input ccu_rst_change PSAMPLE #-1 verilog_node "`CCU.ccu_rst_change"; | |
159 | input ccu_rst_sync_stable PSAMPLE #-1 verilog_node "`CCU.ccu_rst_sync_stable"; | |
160 | input ccu_rst_sys_clk PSAMPLE #-1 verilog_node "`CCU.ccu_rst_sys_clk"; | |
161 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CCU.ccu_serdes_dtm"; | |
162 | input ccu_sys_cmp_sync_en PSAMPLE #-1 verilog_node "`CCU.ccu_sys_cmp_sync_en"; | |
163 | input ccu_vco_aligned PSAMPLE #-1 verilog_node "`CCU.ccu_vco_aligned"; | |
164 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CCU.cluster_arst_l"; | |
165 | input gclk PSAMPLE #-1 verilog_node "`CCU.gclk"; | |
166 | input dr_pll_clk PSAMPLE #-1 verilog_node "`CCU.dr_pll_clk"; | |
167 | input gclk_aligned PSAMPLE #-1 verilog_node "`CCU.gclk_aligned"; | |
168 | input gl_ccu_clk_stop PSAMPLE #-1 verilog_node "`CCU.gl_ccu_clk_stop"; | |
169 | input gl_ccu_io_clk_stop PSAMPLE #-1 verilog_node "`CCU.gl_ccu_io_clk_stop"; | |
170 | input gl_ccu_io_out PSAMPLE #-1 verilog_node "`CCU.gl_ccu_io_out"; | |
171 | input mio_ccu_pll_char_in PSAMPLE #-1 verilog_node "`CCU.mio_ccu_pll_char_in"; | |
172 | input mio_ccu_pll_clamp_fltr PSAMPLE #-1 verilog_node "`CCU.mio_ccu_pll_clamp_fltr"; | |
173 | input [5:0] mio_ccu_pll_div2 PSAMPLE #-1 verilog_node "`CCU.mio_ccu_pll_div2"; | |
174 | input [6:0] mio_ccu_pll_div4 PSAMPLE #-1 verilog_node "`CCU.mio_ccu_pll_div4"; | |
175 | input mio_ccu_pll_trst_l PSAMPLE #-1 verilog_node "`CCU.mio_ccu_pll_trst_l"; | |
176 | input mio_ccu_vreg_selbg_l PSAMPLE #-1 verilog_node "`CCU.mio_ccu_vreg_selbg_l"; | |
177 | input mio_pll_testmode PSAMPLE #-1 verilog_node "`CCU.mio_pll_testmode"; | |
178 | input pll_sys_clk_n PSAMPLE #-1 verilog_node "`CCU.pll_sys_clk_n"; | |
179 | input pll_sys_clk_p PSAMPLE #-1 verilog_node "`CCU.pll_sys_clk_p"; | |
180 | input pll_vdd PSAMPLE #-1 verilog_node "`CCU.pll_vdd"; | |
181 | input [1:0] rng_anlg_sel PSAMPLE #-1 verilog_node "`CCU.rng_anlg_sel"; | |
182 | input rng_arst_l PSAMPLE #-1 verilog_node "`CCU.rng_arst_l"; | |
183 | input rng_bypass PSAMPLE #-1 verilog_node "`CCU.rng_bypass"; | |
184 | input [1:0] rng_ch_sel PSAMPLE #-1 verilog_node "`CCU.rng_ch_sel"; | |
185 | input rng_data PSAMPLE #-1 verilog_node "`CCU.rng_data"; | |
186 | input [1:0] rng_vcoctrl_sel PSAMPLE #-1 verilog_node "`CCU.rng_vcoctrl_sel"; | |
187 | input rst_ccu_ PSAMPLE #-1 verilog_node "`CCU.rst_ccu_"; | |
188 | input rst_ccu_pll_ PSAMPLE #-1 verilog_node "`CCU.rst_ccu_pll_"; | |
189 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CCU.rst_wmr_protect"; | |
190 | input scan_in PSAMPLE #-1 verilog_node "`CCU.scan_in"; | |
191 | input scan_out PSAMPLE #-1 verilog_node "`CCU.scan_out"; | |
192 | input tcu_aclk PSAMPLE #-1 verilog_node "`CCU.tcu_aclk"; | |
193 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CCU.tcu_atpg_mode"; | |
194 | input tcu_bclk PSAMPLE #-1 verilog_node "`CCU.tcu_bclk"; | |
195 | input tcu_ccu_clk_stretch PSAMPLE #-1 verilog_node "`CCU.tcu_ccu_clk_stretch"; | |
196 | input tcu_ccu_ext_cmp_clk PSAMPLE #-1 verilog_node "`CCU.tcu_ccu_ext_cmp_clk"; | |
197 | input tcu_ccu_ext_dr_clk PSAMPLE #-1 verilog_node "`CCU.tcu_ccu_ext_dr_clk"; | |
198 | input [1:0] tcu_ccu_mux_sel PSAMPLE #-1 verilog_node "`CCU.tcu_ccu_mux_sel"; | |
199 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CCU.tcu_pce_ov"; | |
200 | input tcu_scan_en PSAMPLE #-1 verilog_node "`CCU.tcu_scan_en"; | |
201 | //---internal signals-- | |
202 | input ref_clk PSAMPLE #-1 verilog_node "`CCU.ref_clk"; | |
203 | input [5:0] pll_div1 PSAMPLE #-1 verilog_node "`CCU.csr_blk.pll_div1"; | |
204 | input [5:0] pll_div2 PSAMPLE #-1 verilog_node "`CCU.csr_blk.pll_div2"; | |
205 | input [5:0] pll_div3 PSAMPLE #-1 verilog_node "`CCU.csr_blk.pll_div3"; | |
206 | input [6:0] pll_div4 PSAMPLE #-1 verilog_node "`CCU.csr_blk.pll_div4"; | |
207 | input serdes_dtm1 PSAMPLE #-1 verilog_node "`CCU.csr_blk.serdes_dtm1"; | |
208 | input serdes_dtm2 PSAMPLE #-1 verilog_node "`CCU.csr_blk.serdes_dtm2"; | |
209 | } | |
210 | ||
211 | //====================================================== | |
212 | //=== Interface for sigs clocked by IO clock | |
213 | //====================================================== | |
214 | ||
215 | interface ccu_mon_ioclk_if { | |
216 | input iol2clk CLOCK verilog_node "`CCU.iol2clk"; | |
217 | input rd_req_vld PSAMPLE #-1 verilog_node "`CCU.csr_blk.rd_req_vld"; | |
218 | input rd_ack_vld PSAMPLE #-1 verilog_node "`CCU.csr_blk.rd_ack_vld"; | |
219 | input [63:0] lfsr_data PSAMPLE #-1 verilog_node "`CCU.csr_blk.lfsr_data"; | |
220 | } | |
221 | ||
222 | //====================================================== | |
223 | //=== Vera interfaces for internal signals needed ==== | |
224 | //=== for clocking verification ==== | |
225 | //====================================================== | |
226 | ||
227 | // | |
228 | // WHAT: for checking sys_sync_en inside the RST block | |
229 | // | |
230 | interface ccu_rst_sys_sync_en_if { | |
231 | input l2clk CLOCK verilog_node "`RST.l2clk"; | |
232 | input ccu_cmp_sys_sync_en PSAMPLE #-1 verilog_node "`RST.ccu_cmp_sys_sync_en"; | |
233 | input ccu_cmp_sys_sync_en3 PSAMPLE #-1 verilog_node "`RST.rst_cmp_ctl.ccu_cmp_sys_sync_en3"; | |
234 | input ccu_sys_cmp_sync_en PSAMPLE #-1 verilog_node "`RST.ccu_sys_cmp_sync_en"; | |
235 | input ccu_sys_cmp_sync_en3 PSAMPLE #-1 verilog_node "`RST.rst_cmp_ctl.ccu_sys_cmp_sync_en3"; | |
236 | } | |
237 | #endif | |
238 | #endif |