verif/env/tcu/vera/include/ccu.if.vri

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: ccu.if.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
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// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
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// ========== Copyright Header End ============================================
#ifndef INC_CCU_IF_VRI
#define INC_CCU_IF_VRI

#include "fc_top_defines.vri"

//======================================================
//=== define one Vera interface for each signal     ====
//=== (ie. each signal is a VERA CLOCK)             ====
//=== Naming convention: prepend 'ccu_' if signal   ====
//===    does not start with "ccu_"                 ====
//======================================================

interface ccu_pll_sys_clk_p_if {
  input pll_sys_clk_p  CLOCK verilog_node "`CCU.pll_sys_clk_p";
}

interface ccu_cmp_pll_clk_if {
  input cmp_pll_clk  CLOCK verilog_node "`CCU.cmp_pll_clk";
}

interface ccu_rst_ccu_pll_if {
  input rst_ccu_pll_  CLOCK verilog_node "`CCU.rst_ccu_pll_";
}

interface ccu_io2x_out_if {
  input ccu_io2x_out  CLOCK verilog_node "`CCU.ccu_io2x_out";
}

#ifndef GATESIM
interface ccu_rst_sys_clk_if {
  input ccu_rst_sys_clk  CLOCK verilog_node "`CCU.ccu_rst_sys_clk";
}

interface ccu_gclk_if {
  input gclk  CLOCK verilog_node "`CCU.gclk";
}

interface ccu_dr_pll_clk_if {
  input dr_pll_clk  CLOCK verilog_node "`CCU.dr_pll_clk";
}

interface ccu_io_out_if {
  input ccu_io_out  CLOCK verilog_node "`CCU.ccu_io_out";
}

interface ccu_cmp_io_sync_en_if {
  input ccu_cmp_io_sync_en  CLOCK verilog_node "`CCU.ccu_cmp_io_sync_en";
}

interface ccu_io_cmp_sync_en_if {
  input ccu_io_cmp_sync_en  CLOCK verilog_node "`CCU.ccu_io_cmp_sync_en";
}

interface ccu_dr_sync_en_if {
  input ccu_dr_sync_en  CLOCK verilog_node "`CCU.ccu_dr_sync_en";
}

interface ccu_io2x_sync_en_if {
  input ccu_io2x_sync_en  CLOCK verilog_node "`CCU.ccu_io2x_sync_en";
}

interface ccu_cmp_sys_sync_en_if {
  input ccu_cmp_sys_sync_en  CLOCK verilog_node "`CCU.ccu_cmp_sys_sync_en";
}

interface ccu_sys_cmp_sync_en_if {
  input ccu_sys_cmp_sync_en  CLOCK verilog_node "`CCU.ccu_sys_cmp_sync_en";
}

interface ccu_rst_ccu_if {
  input rst_ccu_  CLOCK verilog_node "`CCU.rst_ccu_";
}

interface ccu_rst_sync_stable_if {
  input ccu_rst_sync_stable  CLOCK verilog_node "`CCU.ccu_rst_sync_stable";
}

interface ccu_rst_change_if {
  input ccu_rst_change  CLOCK verilog_node "`CCU.ccu_rst_change";
}

interface ccu_vco_aligned_if {
  input ccu_vco_aligned  CLOCK verilog_node "`CCU.ccu_vco_aligned";
}

interface ccu_gclk_aligned_if {
  input gclk_aligned  CLOCK verilog_node "`CCU.gclk_aligned";
}

interface gl_ccu_clk_stop_if {
  input gl_ccu_clk_stop CLOCK  verilog_node "`CCU.gl_ccu_clk_stop";
}

interface gl_ccu_io_clk_stop_if {
  input gl_ccu_io_clk_stop CLOCK  verilog_node "`CCU.gl_ccu_io_clk_stop";
}

interface tcu_atpg_mode_if {
  input tcu_atpg_mode CLOCK verilog_node "`CCU.tcu_atpg_mode";
}

interface ccu_ref_clk_if {
  input ref_clk  CLOCK verilog_node "`CCU.ref_clk";
}

#endif
//======================================================
//=== Monitor interface
//======================================================
#ifndef GATESIM
interface ccu_mon_if {
  input cmp_pll_clk                   CLOCK                  verilog_node "`CCU.cmp_pll_clk";

  input ccu_cmp_io_sync_en            PSAMPLE #-1  verilog_node "`CCU.ccu_cmp_io_sync_en";
  input ccu_cmp_sys_sync_en           PSAMPLE #-1  verilog_node "`CCU.ccu_cmp_sys_sync_en";
  input ccu_dbg1_serdes_dtm           PSAMPLE #-1  verilog_node "`CCU.ccu_dbg1_serdes_dtm";
  input ccu_dr_sync_en                PSAMPLE #-1  verilog_node "`CCU.ccu_dr_sync_en";
  input ccu_io2x_out                  PSAMPLE #-1  verilog_node "`CCU.ccu_io2x_out";
  input ccu_io2x_sync_en              PSAMPLE #-1  verilog_node "`CCU.ccu_io2x_sync_en";
  input ccu_io_cmp_sync_en            PSAMPLE #-1  verilog_node "`CCU.ccu_io_cmp_sync_en";
  input ccu_io_out                    PSAMPLE #-1  verilog_node "`CCU.ccu_io_out";
  input [1:0] ccu_mio_pll_char_out    PSAMPLE #-1  verilog_node "`CCU.ccu_mio_pll_char_out";
  input ccu_mio_serdes_dtm            PSAMPLE #-1  verilog_node "`CCU.ccu_mio_serdes_dtm";
  input ccu_rst_change                PSAMPLE #-1  verilog_node "`CCU.ccu_rst_change";
  input ccu_rst_sync_stable           PSAMPLE #-1  verilog_node "`CCU.ccu_rst_sync_stable";
  input ccu_rst_sys_clk               PSAMPLE #-1  verilog_node "`CCU.ccu_rst_sys_clk";
  input ccu_serdes_dtm                PSAMPLE #-1  verilog_node "`CCU.ccu_serdes_dtm";
  input ccu_sys_cmp_sync_en           PSAMPLE #-1  verilog_node "`CCU.ccu_sys_cmp_sync_en";
  input ccu_vco_aligned               PSAMPLE #-1  verilog_node "`CCU.ccu_vco_aligned";
  input cluster_arst_l                PSAMPLE #-1  verilog_node "`CCU.cluster_arst_l";
  input gclk                              PSAMPLE #-1  verilog_node "`CCU.gclk";
  input dr_pll_clk                    PSAMPLE #-1  verilog_node "`CCU.dr_pll_clk";
  input gclk_aligned                  PSAMPLE #-1  verilog_node "`CCU.gclk_aligned";
  input gl_ccu_clk_stop               PSAMPLE #-1  verilog_node "`CCU.gl_ccu_clk_stop";
  input gl_ccu_io_clk_stop            PSAMPLE #-1  verilog_node "`CCU.gl_ccu_io_clk_stop";
  input gl_ccu_io_out                 PSAMPLE #-1  verilog_node "`CCU.gl_ccu_io_out";
  input mio_ccu_pll_char_in           PSAMPLE #-1  verilog_node "`CCU.mio_ccu_pll_char_in";
  input mio_ccu_pll_clamp_fltr        PSAMPLE #-1  verilog_node "`CCU.mio_ccu_pll_clamp_fltr";
  input [5:0] mio_ccu_pll_div2        PSAMPLE #-1  verilog_node "`CCU.mio_ccu_pll_div2";
  input [6:0] mio_ccu_pll_div4        PSAMPLE #-1  verilog_node "`CCU.mio_ccu_pll_div4";
  input mio_ccu_pll_trst_l            PSAMPLE #-1  verilog_node "`CCU.mio_ccu_pll_trst_l";
  input mio_ccu_vreg_selbg_l          PSAMPLE #-1  verilog_node "`CCU.mio_ccu_vreg_selbg_l";
  input mio_pll_testmode              PSAMPLE #-1  verilog_node "`CCU.mio_pll_testmode";
  input pll_sys_clk_n                 PSAMPLE #-1  verilog_node "`CCU.pll_sys_clk_n";
  input pll_sys_clk_p                 PSAMPLE #-1  verilog_node "`CCU.pll_sys_clk_p";
  input pll_vdd                       PSAMPLE #-1  verilog_node "`CCU.pll_vdd";
  input [1:0] rng_anlg_sel            PSAMPLE #-1  verilog_node "`CCU.rng_anlg_sel";
  input rng_arst_l                    PSAMPLE #-1  verilog_node "`CCU.rng_arst_l";
  input rng_bypass                    PSAMPLE #-1  verilog_node "`CCU.rng_bypass";
  input [1:0] rng_ch_sel              PSAMPLE #-1  verilog_node "`CCU.rng_ch_sel";
  input rng_data                      PSAMPLE #-1  verilog_node "`CCU.rng_data";
  input [1:0] rng_vcoctrl_sel         PSAMPLE #-1  verilog_node "`CCU.rng_vcoctrl_sel";
  input rst_ccu_                      PSAMPLE #-1  verilog_node "`CCU.rst_ccu_";
  input rst_ccu_pll_                  PSAMPLE #-1  verilog_node "`CCU.rst_ccu_pll_";
  input rst_wmr_protect               PSAMPLE #-1  verilog_node "`CCU.rst_wmr_protect";
  input scan_in                       PSAMPLE #-1  verilog_node "`CCU.scan_in";
  input scan_out                      PSAMPLE #-1  verilog_node "`CCU.scan_out";
  input tcu_aclk                      PSAMPLE #-1  verilog_node "`CCU.tcu_aclk";
  input tcu_atpg_mode                 PSAMPLE #-1  verilog_node "`CCU.tcu_atpg_mode";
  input tcu_bclk                      PSAMPLE #-1  verilog_node "`CCU.tcu_bclk";
  input tcu_ccu_clk_stretch           PSAMPLE #-1  verilog_node "`CCU.tcu_ccu_clk_stretch";
  input tcu_ccu_ext_cmp_clk           PSAMPLE #-1  verilog_node "`CCU.tcu_ccu_ext_cmp_clk";
  input tcu_ccu_ext_dr_clk            PSAMPLE #-1  verilog_node "`CCU.tcu_ccu_ext_dr_clk";
  input [1:0] tcu_ccu_mux_sel         PSAMPLE #-1  verilog_node "`CCU.tcu_ccu_mux_sel";
  input tcu_pce_ov                    PSAMPLE #-1  verilog_node "`CCU.tcu_pce_ov";
  input tcu_scan_en                   PSAMPLE #-1  verilog_node "`CCU.tcu_scan_en";
  //---internal signals--
  input ref_clk                       PSAMPLE #-1  verilog_node "`CCU.ref_clk";
  input [5:0] pll_div1                PSAMPLE #-1  verilog_node "`CCU.csr_blk.pll_div1";
  input [5:0] pll_div2                PSAMPLE #-1  verilog_node "`CCU.csr_blk.pll_div2";
  input [5:0] pll_div3                PSAMPLE #-1  verilog_node "`CCU.csr_blk.pll_div3";
  input [6:0] pll_div4                PSAMPLE #-1  verilog_node "`CCU.csr_blk.pll_div4";
  input serdes_dtm1                   PSAMPLE #-1  verilog_node "`CCU.csr_blk.serdes_dtm1";
  input serdes_dtm2                   PSAMPLE #-1  verilog_node "`CCU.csr_blk.serdes_dtm2";
}

//======================================================
//=== Interface for sigs clocked by IO clock
//======================================================

interface ccu_mon_ioclk_if {
  input iol2clk       CLOCK        verilog_node "`CCU.iol2clk";
  input rd_req_vld           PSAMPLE #-1  verilog_node "`CCU.csr_blk.rd_req_vld";
  input rd_ack_vld           PSAMPLE #-1  verilog_node "`CCU.csr_blk.rd_ack_vld";
  input [63:0] lfsr_data     PSAMPLE #-1  verilog_node "`CCU.csr_blk.lfsr_data";
}

//======================================================
//=== Vera interfaces for internal signals needed   ====
//=== for clocking verification                     ====
//======================================================

//
// WHAT: for checking sys_sync_en inside the RST block
//
interface ccu_rst_sys_sync_en_if {
  input l2clk                 CLOCK        verilog_node "`RST.l2clk";
  input ccu_cmp_sys_sync_en   PSAMPLE #-1  verilog_node "`RST.ccu_cmp_sys_sync_en";
  input ccu_cmp_sys_sync_en3  PSAMPLE #-1  verilog_node "`RST.rst_cmp_ctl.ccu_cmp_sys_sync_en3";
  input ccu_sys_cmp_sync_en   PSAMPLE #-1  verilog_node "`RST.ccu_sys_cmp_sync_en";
  input ccu_sys_cmp_sync_en3  PSAMPLE #-1  verilog_node "`RST.rst_cmp_ctl.ccu_sys_cmp_sync_en3";
}
#endif
#endif