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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: cluster_hdr.if.vri | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #ifndef INC_CLUSTER_HDR_IF_VRI | |
36 | #define INC_CLUSTER_HDR_IF_VRI | |
37 | ||
38 | #include "fc_top_defines.vri" | |
39 | ||
40 | // | |
41 | // WARNING: this file is generated by script gen_cluster_hdr.pl. Do not modify. | |
42 | // | |
43 | ||
44 | //########################################################### | |
45 | //### interfaces for DR and IO2X headers in ccu_mon module ## | |
46 | //########################################################### | |
47 | interface clkgen_ccumon_dr_l2clk_if { | |
48 | input l2clk CLOCK verilog_node "`TOP.ccu_mon.clkgen_dr.l2clk"; | |
49 | } | |
50 | interface clkgen_ccumon_io2x_l2clk_if { | |
51 | input l2clk CLOCK verilog_node "`TOP.ccu_mon.clkgen_io2x.l2clk"; | |
52 | } | |
53 | //########################################################## | |
54 | //### interfaces for cluster headers (blocks in TCU SAT) ### | |
55 | //########################################################## | |
56 | ||
57 | //----- VERA interfaces for clkgen_ccu_cmp ----- | |
58 | ||
59 | interface clkgen_ccu_cmp_gclk_if { | |
60 | input gclk CLOCK verilog_node "`CPU.ccu.clkgen_cmp.gclk"; // Vera interface clock | |
61 | ||
62 | input aclk PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.aclk"; | |
63 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.aclk_wmr"; | |
64 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.array_wr_inhibit"; | |
65 | input bclk PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.bclk"; | |
66 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.ccu_cmp_slow_sync_en"; | |
67 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.ccu_div_ph"; | |
68 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.ccu_serdes_dtm"; | |
69 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.ccu_slow_cmp_sync_en"; | |
70 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.clk_ext"; | |
71 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.cluster_arst_l"; | |
72 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.cluster_div_en"; | |
73 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.cmp_slow_sync_en"; | |
74 | input l2clk PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.l2clk"; | |
75 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.pce_ov"; | |
76 | input por_ PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.por_"; | |
77 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.rst_por_"; | |
78 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.rst_wmr_"; | |
79 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.rst_wmr_protect"; | |
80 | input scan_en PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.scan_en"; | |
81 | input scan_in PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.scan_in"; | |
82 | input scan_out PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.scan_out"; | |
83 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.slow_cmp_sync_en"; | |
84 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.tcu_aclk"; | |
85 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.tcu_atpg_mode"; | |
86 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.tcu_bclk"; | |
87 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.tcu_clk_stop"; | |
88 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.tcu_div_bypass"; | |
89 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.tcu_pce_ov"; | |
90 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.tcu_wr_inhibit"; | |
91 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.wmr_"; | |
92 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.wmr_protect"; | |
93 | } | |
94 | ||
95 | interface clkgen_ccu_cmp_l2clk_if { | |
96 | input l2clk CLOCK verilog_node "`CPU.ccu.clkgen_cmp.l2clk"; // Vera interface clock | |
97 | ||
98 | input aclk PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.aclk"; | |
99 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.aclk_wmr"; | |
100 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.array_wr_inhibit"; | |
101 | input bclk PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.bclk"; | |
102 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.cmp_slow_sync_en"; | |
103 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.pce_ov"; | |
104 | input por_ PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.por_"; | |
105 | input scan_out PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.scan_out"; | |
106 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.slow_cmp_sync_en"; | |
107 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.wmr_"; | |
108 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.wmr_protect"; | |
109 | } | |
110 | ||
111 | //----- VERA interfaces for clkgen_ccu_io ----- | |
112 | ||
113 | interface clkgen_ccu_io_gclk_if { | |
114 | input gclk CLOCK verilog_node "`CPU.ccu.clkgen_io.gclk"; // Vera interface clock | |
115 | ||
116 | input aclk PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.aclk"; | |
117 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.aclk_wmr"; | |
118 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.array_wr_inhibit"; | |
119 | input bclk PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.bclk"; | |
120 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.ccu_cmp_slow_sync_en"; | |
121 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.ccu_div_ph"; | |
122 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.ccu_serdes_dtm"; | |
123 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.ccu_slow_cmp_sync_en"; | |
124 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.clk_ext"; | |
125 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.cluster_arst_l"; | |
126 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.cluster_div_en"; | |
127 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.cmp_slow_sync_en"; | |
128 | input l2clk PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.l2clk"; | |
129 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.pce_ov"; | |
130 | input por_ PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.por_"; | |
131 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.rst_por_"; | |
132 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.rst_wmr_"; | |
133 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.rst_wmr_protect"; | |
134 | input scan_en PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.scan_en"; | |
135 | input scan_in PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.scan_in"; | |
136 | input scan_out PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.scan_out"; | |
137 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.slow_cmp_sync_en"; | |
138 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.tcu_aclk"; | |
139 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.tcu_atpg_mode"; | |
140 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.tcu_bclk"; | |
141 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.tcu_clk_stop"; | |
142 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.tcu_div_bypass"; | |
143 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.tcu_pce_ov"; | |
144 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.tcu_wr_inhibit"; | |
145 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.wmr_"; | |
146 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.wmr_protect"; | |
147 | } | |
148 | ||
149 | interface clkgen_ccu_io_l2clk_if { | |
150 | input l2clk CLOCK verilog_node "`CPU.ccu.clkgen_io.l2clk"; // Vera interface clock | |
151 | ||
152 | input aclk PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.aclk"; | |
153 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.aclk_wmr"; | |
154 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.array_wr_inhibit"; | |
155 | input bclk PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.bclk"; | |
156 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.cmp_slow_sync_en"; | |
157 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.pce_ov"; | |
158 | input por_ PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.por_"; | |
159 | input scan_out PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.scan_out"; | |
160 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.slow_cmp_sync_en"; | |
161 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.wmr_"; | |
162 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.wmr_protect"; | |
163 | } | |
164 | ||
165 | //----- VERA interfaces for clkgen_db0_cmp ----- | |
166 | ||
167 | interface clkgen_db0_cmp_gclk_if { | |
168 | input gclk CLOCK verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.gclk"; // Vera interface clock | |
169 | ||
170 | input aclk PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.aclk"; | |
171 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.aclk_wmr"; | |
172 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.array_wr_inhibit"; | |
173 | input bclk PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.bclk"; | |
174 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.ccu_cmp_slow_sync_en"; | |
175 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.ccu_div_ph"; | |
176 | input ccu_dr_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.ccu_dr_sync_en"; | |
177 | input ccu_io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.ccu_io2x_sync_en"; | |
178 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.ccu_serdes_dtm"; | |
179 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.ccu_slow_cmp_sync_en"; | |
180 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.clk_ext"; | |
181 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.cluster_arst_l"; | |
182 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.cluster_div_en"; | |
183 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.cmp_slow_sync_en"; | |
184 | input dr_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.dr_sync_en"; | |
185 | input io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.io2x_sync_en"; | |
186 | input l2clk PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.l2clk"; | |
187 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.pce_ov"; | |
188 | input por_ PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.por_"; | |
189 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.rst_por_"; | |
190 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.rst_wmr_"; | |
191 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.rst_wmr_protect"; | |
192 | input scan_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.scan_en"; | |
193 | input scan_in PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.scan_in"; | |
194 | input scan_out PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.scan_out"; | |
195 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.slow_cmp_sync_en"; | |
196 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.tcu_aclk"; | |
197 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.tcu_atpg_mode"; | |
198 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.tcu_bclk"; | |
199 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.tcu_clk_stop"; | |
200 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.tcu_div_bypass"; | |
201 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.tcu_pce_ov"; | |
202 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.tcu_wr_inhibit"; | |
203 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.wmr_"; | |
204 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.wmr_protect"; | |
205 | } | |
206 | ||
207 | interface clkgen_db0_cmp_l2clk_if { | |
208 | input l2clk CLOCK verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.l2clk"; // Vera interface clock | |
209 | ||
210 | input aclk PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.aclk"; | |
211 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.aclk_wmr"; | |
212 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.array_wr_inhibit"; | |
213 | input bclk PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.bclk"; | |
214 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.cmp_slow_sync_en"; | |
215 | input dr_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.dr_sync_en"; | |
216 | input io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.io2x_sync_en"; | |
217 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.pce_ov"; | |
218 | input por_ PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.por_"; | |
219 | input scan_out PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.scan_out"; | |
220 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.slow_cmp_sync_en"; | |
221 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.wmr_"; | |
222 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.wmr_protect"; | |
223 | } | |
224 | ||
225 | //----- VERA interfaces for clkgen_db0_io ----- | |
226 | ||
227 | interface clkgen_db0_io_gclk_if { | |
228 | input gclk CLOCK verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.gclk"; // Vera interface clock | |
229 | ||
230 | input aclk PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.aclk"; | |
231 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.aclk_wmr"; | |
232 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.array_wr_inhibit"; | |
233 | input bclk PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.bclk"; | |
234 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.ccu_cmp_slow_sync_en"; | |
235 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.ccu_div_ph"; | |
236 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.ccu_serdes_dtm"; | |
237 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.ccu_slow_cmp_sync_en"; | |
238 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.clk_ext"; | |
239 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.cluster_arst_l"; | |
240 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.cluster_div_en"; | |
241 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.cmp_slow_sync_en"; | |
242 | input l2clk PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.l2clk"; | |
243 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.pce_ov"; | |
244 | input por_ PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.por_"; | |
245 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.rst_por_"; | |
246 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.rst_wmr_"; | |
247 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.rst_wmr_protect"; | |
248 | input scan_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.scan_en"; | |
249 | input scan_in PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.scan_in"; | |
250 | input scan_out PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.scan_out"; | |
251 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.slow_cmp_sync_en"; | |
252 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.tcu_aclk"; | |
253 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.tcu_atpg_mode"; | |
254 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.tcu_bclk"; | |
255 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.tcu_clk_stop"; | |
256 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.tcu_div_bypass"; | |
257 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.tcu_pce_ov"; | |
258 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.tcu_wr_inhibit"; | |
259 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.wmr_"; | |
260 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.wmr_protect"; | |
261 | } | |
262 | ||
263 | interface clkgen_db0_io_l2clk_if { | |
264 | input l2clk CLOCK verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.l2clk"; // Vera interface clock | |
265 | ||
266 | input aclk PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.aclk"; | |
267 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.aclk_wmr"; | |
268 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.array_wr_inhibit"; | |
269 | input bclk PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.bclk"; | |
270 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.cmp_slow_sync_en"; | |
271 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.pce_ov"; | |
272 | input por_ PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.por_"; | |
273 | input scan_out PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.scan_out"; | |
274 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.slow_cmp_sync_en"; | |
275 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.wmr_"; | |
276 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.wmr_protect"; | |
277 | } | |
278 | ||
279 | //----- VERA interfaces for clkgen_db1_cmp ----- | |
280 | ||
281 | interface clkgen_db1_cmp_gclk_if { | |
282 | input gclk CLOCK verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.gclk"; // Vera interface clock | |
283 | ||
284 | input aclk PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.aclk"; | |
285 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.aclk_wmr"; | |
286 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.array_wr_inhibit"; | |
287 | input bclk PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.bclk"; | |
288 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.ccu_cmp_slow_sync_en"; | |
289 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.ccu_div_ph"; | |
290 | input ccu_dr_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.ccu_dr_sync_en"; | |
291 | input ccu_io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.ccu_io2x_sync_en"; | |
292 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.ccu_serdes_dtm"; | |
293 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.ccu_slow_cmp_sync_en"; | |
294 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.clk_ext"; | |
295 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.cluster_arst_l"; | |
296 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.cluster_div_en"; | |
297 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.cmp_slow_sync_en"; | |
298 | input dr_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.dr_sync_en"; | |
299 | input io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.io2x_sync_en"; | |
300 | input l2clk PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.l2clk"; | |
301 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.pce_ov"; | |
302 | input por_ PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.por_"; | |
303 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.rst_por_"; | |
304 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.rst_wmr_"; | |
305 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.rst_wmr_protect"; | |
306 | input scan_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.scan_en"; | |
307 | input scan_in PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.scan_in"; | |
308 | input scan_out PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.scan_out"; | |
309 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.slow_cmp_sync_en"; | |
310 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.tcu_aclk"; | |
311 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.tcu_atpg_mode"; | |
312 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.tcu_bclk"; | |
313 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.tcu_clk_stop"; | |
314 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.tcu_div_bypass"; | |
315 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.tcu_pce_ov"; | |
316 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.tcu_wr_inhibit"; | |
317 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.wmr_"; | |
318 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.wmr_protect"; | |
319 | } | |
320 | ||
321 | interface clkgen_db1_cmp_l2clk_if { | |
322 | input l2clk CLOCK verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.l2clk"; // Vera interface clock | |
323 | ||
324 | input aclk PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.aclk"; | |
325 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.aclk_wmr"; | |
326 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.array_wr_inhibit"; | |
327 | input bclk PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.bclk"; | |
328 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.cmp_slow_sync_en"; | |
329 | input dr_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.dr_sync_en"; | |
330 | input io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.io2x_sync_en"; | |
331 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.pce_ov"; | |
332 | input por_ PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.por_"; | |
333 | input scan_out PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.scan_out"; | |
334 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.slow_cmp_sync_en"; | |
335 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.wmr_"; | |
336 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.wmr_protect"; | |
337 | } | |
338 | ||
339 | //----- VERA interfaces for clkgen_db1_io ----- | |
340 | ||
341 | interface clkgen_db1_io_gclk_if { | |
342 | input gclk CLOCK verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.gclk"; // Vera interface clock | |
343 | ||
344 | input aclk PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.aclk"; | |
345 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.aclk_wmr"; | |
346 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.array_wr_inhibit"; | |
347 | input bclk PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.bclk"; | |
348 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.ccu_cmp_slow_sync_en"; | |
349 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.ccu_div_ph"; | |
350 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.ccu_serdes_dtm"; | |
351 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.ccu_slow_cmp_sync_en"; | |
352 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.clk_ext"; | |
353 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.cluster_arst_l"; | |
354 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.cluster_div_en"; | |
355 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.cmp_slow_sync_en"; | |
356 | input l2clk PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.l2clk"; | |
357 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.pce_ov"; | |
358 | input por_ PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.por_"; | |
359 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.rst_por_"; | |
360 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.rst_wmr_"; | |
361 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.rst_wmr_protect"; | |
362 | input scan_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.scan_en"; | |
363 | input scan_in PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.scan_in"; | |
364 | input scan_out PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.scan_out"; | |
365 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.slow_cmp_sync_en"; | |
366 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.tcu_aclk"; | |
367 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.tcu_atpg_mode"; | |
368 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.tcu_bclk"; | |
369 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.tcu_clk_stop"; | |
370 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.tcu_div_bypass"; | |
371 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.tcu_pce_ov"; | |
372 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.tcu_wr_inhibit"; | |
373 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.wmr_"; | |
374 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.wmr_protect"; | |
375 | } | |
376 | ||
377 | interface clkgen_db1_io_l2clk_if { | |
378 | input l2clk CLOCK verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.l2clk"; // Vera interface clock | |
379 | ||
380 | input aclk PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.aclk"; | |
381 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.aclk_wmr"; | |
382 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.array_wr_inhibit"; | |
383 | input bclk PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.bclk"; | |
384 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.cmp_slow_sync_en"; | |
385 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.pce_ov"; | |
386 | input por_ PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.por_"; | |
387 | input scan_out PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.scan_out"; | |
388 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.slow_cmp_sync_en"; | |
389 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.wmr_"; | |
390 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.wmr_protect"; | |
391 | } | |
392 | ||
393 | //----- VERA interfaces for clkgen_efu_io ----- | |
394 | ||
395 | interface clkgen_efu_io_gclk_if { | |
396 | input gclk CLOCK verilog_node "`CPU.efu.efu_ioclk_header.gclk"; // Vera interface clock | |
397 | ||
398 | input aclk PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.aclk"; | |
399 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.aclk_wmr"; | |
400 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.array_wr_inhibit"; | |
401 | input bclk PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.bclk"; | |
402 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.ccu_cmp_slow_sync_en"; | |
403 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.ccu_div_ph"; | |
404 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.ccu_serdes_dtm"; | |
405 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.ccu_slow_cmp_sync_en"; | |
406 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.clk_ext"; | |
407 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.cluster_arst_l"; | |
408 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.cluster_div_en"; | |
409 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.cmp_slow_sync_en"; | |
410 | input l2clk PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.l2clk"; | |
411 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.pce_ov"; | |
412 | input por_ PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.por_"; | |
413 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.rst_por_"; | |
414 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.rst_wmr_"; | |
415 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.rst_wmr_protect"; | |
416 | input scan_en PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.scan_en"; | |
417 | input scan_in PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.scan_in"; | |
418 | input scan_out PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.scan_out"; | |
419 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.slow_cmp_sync_en"; | |
420 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.tcu_aclk"; | |
421 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.tcu_atpg_mode"; | |
422 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.tcu_bclk"; | |
423 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.tcu_clk_stop"; | |
424 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.tcu_div_bypass"; | |
425 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.tcu_pce_ov"; | |
426 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.tcu_wr_inhibit"; | |
427 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.wmr_"; | |
428 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.wmr_protect"; | |
429 | } | |
430 | ||
431 | interface clkgen_efu_io_l2clk_if { | |
432 | input l2clk CLOCK verilog_node "`CPU.efu.efu_ioclk_header.l2clk"; // Vera interface clock | |
433 | ||
434 | input aclk PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.aclk"; | |
435 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.aclk_wmr"; | |
436 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.array_wr_inhibit"; | |
437 | input bclk PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.bclk"; | |
438 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.cmp_slow_sync_en"; | |
439 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.pce_ov"; | |
440 | input por_ PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.por_"; | |
441 | input scan_out PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.scan_out"; | |
442 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.slow_cmp_sync_en"; | |
443 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.wmr_"; | |
444 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.wmr_protect"; | |
445 | } | |
446 | ||
447 | //----- VERA interfaces for clkgen_efu_cmp ----- | |
448 | ||
449 | interface clkgen_efu_cmp_gclk_if { | |
450 | input gclk CLOCK verilog_node "`CPU.efu.l2t_clk_header.gclk"; // Vera interface clock | |
451 | ||
452 | input aclk PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.aclk"; | |
453 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.aclk_wmr"; | |
454 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.array_wr_inhibit"; | |
455 | input bclk PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.bclk"; | |
456 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.ccu_cmp_slow_sync_en"; | |
457 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.ccu_div_ph"; | |
458 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.ccu_serdes_dtm"; | |
459 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.ccu_slow_cmp_sync_en"; | |
460 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.clk_ext"; | |
461 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.cluster_arst_l"; | |
462 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.cluster_div_en"; | |
463 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.cmp_slow_sync_en"; | |
464 | input l2clk PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.l2clk"; | |
465 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.pce_ov"; | |
466 | input por_ PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.por_"; | |
467 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.rst_por_"; | |
468 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.rst_wmr_"; | |
469 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.rst_wmr_protect"; | |
470 | input scan_en PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.scan_en"; | |
471 | input scan_in PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.scan_in"; | |
472 | input scan_out PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.scan_out"; | |
473 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.slow_cmp_sync_en"; | |
474 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.tcu_aclk"; | |
475 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.tcu_atpg_mode"; | |
476 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.tcu_bclk"; | |
477 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.tcu_clk_stop"; | |
478 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.tcu_div_bypass"; | |
479 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.tcu_pce_ov"; | |
480 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.tcu_wr_inhibit"; | |
481 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.wmr_"; | |
482 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.wmr_protect"; | |
483 | } | |
484 | ||
485 | interface clkgen_efu_cmp_l2clk_if { | |
486 | input l2clk CLOCK verilog_node "`CPU.efu.l2t_clk_header.l2clk"; // Vera interface clock | |
487 | ||
488 | input aclk PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.aclk"; | |
489 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.aclk_wmr"; | |
490 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.array_wr_inhibit"; | |
491 | input bclk PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.bclk"; | |
492 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.cmp_slow_sync_en"; | |
493 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.pce_ov"; | |
494 | input por_ PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.por_"; | |
495 | input scan_out PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.scan_out"; | |
496 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.slow_cmp_sync_en"; | |
497 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.wmr_"; | |
498 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.wmr_protect"; | |
499 | } | |
500 | ||
501 | //----- VERA interfaces for clkgen_mio_0_cmp ----- | |
502 | ||
503 | interface clkgen_mio_0_cmp_gclk_if { | |
504 | input gclk CLOCK verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.gclk"; // Vera interface clock | |
505 | ||
506 | input aclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.aclk"; | |
507 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.aclk_wmr"; | |
508 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.array_wr_inhibit"; | |
509 | input bclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.bclk"; | |
510 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.ccu_cmp_slow_sync_en"; | |
511 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.ccu_div_ph"; | |
512 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.ccu_serdes_dtm"; | |
513 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.ccu_slow_cmp_sync_en"; | |
514 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.clk_ext"; | |
515 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.cluster_arst_l"; | |
516 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.cluster_div_en"; | |
517 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.cmp_slow_sync_en"; | |
518 | input l2clk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.l2clk"; | |
519 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.pce_ov"; | |
520 | input por_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.por_"; | |
521 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.rst_por_"; | |
522 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.rst_wmr_"; | |
523 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.rst_wmr_protect"; | |
524 | input scan_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.scan_en"; | |
525 | input scan_in PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.scan_in"; | |
526 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.scan_out"; | |
527 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.slow_cmp_sync_en"; | |
528 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.tcu_aclk"; | |
529 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.tcu_atpg_mode"; | |
530 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.tcu_bclk"; | |
531 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.tcu_clk_stop"; | |
532 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.tcu_div_bypass"; | |
533 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.tcu_pce_ov"; | |
534 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.tcu_wr_inhibit"; | |
535 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.wmr_"; | |
536 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.wmr_protect"; | |
537 | } | |
538 | ||
539 | interface clkgen_mio_0_cmp_l2clk_if { | |
540 | input l2clk CLOCK verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.l2clk"; // Vera interface clock | |
541 | ||
542 | input aclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.aclk"; | |
543 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.aclk_wmr"; | |
544 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.array_wr_inhibit"; | |
545 | input bclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.bclk"; | |
546 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.cmp_slow_sync_en"; | |
547 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.pce_ov"; | |
548 | input por_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.por_"; | |
549 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.scan_out"; | |
550 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.slow_cmp_sync_en"; | |
551 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.wmr_"; | |
552 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.wmr_protect"; | |
553 | } | |
554 | ||
555 | //----- VERA interfaces for clkgen_mio_1_cmp ----- | |
556 | ||
557 | interface clkgen_mio_1_cmp_gclk_if { | |
558 | input gclk CLOCK verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.gclk"; // Vera interface clock | |
559 | ||
560 | input aclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.aclk"; | |
561 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.aclk_wmr"; | |
562 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.array_wr_inhibit"; | |
563 | input bclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.bclk"; | |
564 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.ccu_cmp_slow_sync_en"; | |
565 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.ccu_div_ph"; | |
566 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.ccu_serdes_dtm"; | |
567 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.ccu_slow_cmp_sync_en"; | |
568 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.clk_ext"; | |
569 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.cluster_arst_l"; | |
570 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.cluster_div_en"; | |
571 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.cmp_slow_sync_en"; | |
572 | input l2clk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.l2clk"; | |
573 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.pce_ov"; | |
574 | input por_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.por_"; | |
575 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.rst_por_"; | |
576 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.rst_wmr_"; | |
577 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.rst_wmr_protect"; | |
578 | input scan_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.scan_en"; | |
579 | input scan_in PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.scan_in"; | |
580 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.scan_out"; | |
581 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.slow_cmp_sync_en"; | |
582 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.tcu_aclk"; | |
583 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.tcu_atpg_mode"; | |
584 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.tcu_bclk"; | |
585 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.tcu_clk_stop"; | |
586 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.tcu_div_bypass"; | |
587 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.tcu_pce_ov"; | |
588 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.tcu_wr_inhibit"; | |
589 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.wmr_"; | |
590 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.wmr_protect"; | |
591 | } | |
592 | ||
593 | interface clkgen_mio_1_cmp_l2clk_if { | |
594 | input l2clk CLOCK verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.l2clk"; // Vera interface clock | |
595 | ||
596 | input aclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.aclk"; | |
597 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.aclk_wmr"; | |
598 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.array_wr_inhibit"; | |
599 | input bclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.bclk"; | |
600 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.cmp_slow_sync_en"; | |
601 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.pce_ov"; | |
602 | input por_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.por_"; | |
603 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.scan_out"; | |
604 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.slow_cmp_sync_en"; | |
605 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.wmr_"; | |
606 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.wmr_protect"; | |
607 | } | |
608 | ||
609 | //----- VERA interfaces for clkgen_mio_2_cmp ----- | |
610 | ||
611 | interface clkgen_mio_2_cmp_gclk_if { | |
612 | input gclk CLOCK verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.gclk"; // Vera interface clock | |
613 | ||
614 | input aclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.aclk"; | |
615 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.aclk_wmr"; | |
616 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.array_wr_inhibit"; | |
617 | input bclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.bclk"; | |
618 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.ccu_cmp_slow_sync_en"; | |
619 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.ccu_div_ph"; | |
620 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.ccu_serdes_dtm"; | |
621 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.ccu_slow_cmp_sync_en"; | |
622 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.clk_ext"; | |
623 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.cluster_arst_l"; | |
624 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.cluster_div_en"; | |
625 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.cmp_slow_sync_en"; | |
626 | input l2clk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.l2clk"; | |
627 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.pce_ov"; | |
628 | input por_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.por_"; | |
629 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.rst_por_"; | |
630 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.rst_wmr_"; | |
631 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.rst_wmr_protect"; | |
632 | input scan_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.scan_en"; | |
633 | input scan_in PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.scan_in"; | |
634 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.scan_out"; | |
635 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.slow_cmp_sync_en"; | |
636 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.tcu_aclk"; | |
637 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.tcu_atpg_mode"; | |
638 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.tcu_bclk"; | |
639 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.tcu_clk_stop"; | |
640 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.tcu_div_bypass"; | |
641 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.tcu_pce_ov"; | |
642 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.tcu_wr_inhibit"; | |
643 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.wmr_"; | |
644 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.wmr_protect"; | |
645 | } | |
646 | ||
647 | interface clkgen_mio_2_cmp_l2clk_if { | |
648 | input l2clk CLOCK verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.l2clk"; // Vera interface clock | |
649 | ||
650 | input aclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.aclk"; | |
651 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.aclk_wmr"; | |
652 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.array_wr_inhibit"; | |
653 | input bclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.bclk"; | |
654 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.cmp_slow_sync_en"; | |
655 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.pce_ov"; | |
656 | input por_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.por_"; | |
657 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.scan_out"; | |
658 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.slow_cmp_sync_en"; | |
659 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.wmr_"; | |
660 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.wmr_protect"; | |
661 | } | |
662 | ||
663 | //----- VERA interfaces for clkgen_mio_3_cmp ----- | |
664 | ||
665 | interface clkgen_mio_3_cmp_gclk_if { | |
666 | input gclk CLOCK verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.gclk"; // Vera interface clock | |
667 | ||
668 | input aclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.aclk"; | |
669 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.aclk_wmr"; | |
670 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.array_wr_inhibit"; | |
671 | input bclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.bclk"; | |
672 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.ccu_cmp_slow_sync_en"; | |
673 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.ccu_div_ph"; | |
674 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.ccu_serdes_dtm"; | |
675 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.ccu_slow_cmp_sync_en"; | |
676 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.clk_ext"; | |
677 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.cluster_arst_l"; | |
678 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.cluster_div_en"; | |
679 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.cmp_slow_sync_en"; | |
680 | input l2clk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.l2clk"; | |
681 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.pce_ov"; | |
682 | input por_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.por_"; | |
683 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.rst_por_"; | |
684 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.rst_wmr_"; | |
685 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.rst_wmr_protect"; | |
686 | input scan_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.scan_en"; | |
687 | input scan_in PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.scan_in"; | |
688 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.scan_out"; | |
689 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.slow_cmp_sync_en"; | |
690 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.tcu_aclk"; | |
691 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.tcu_atpg_mode"; | |
692 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.tcu_bclk"; | |
693 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.tcu_clk_stop"; | |
694 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.tcu_div_bypass"; | |
695 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.tcu_pce_ov"; | |
696 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.tcu_wr_inhibit"; | |
697 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.wmr_"; | |
698 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.wmr_protect"; | |
699 | } | |
700 | ||
701 | interface clkgen_mio_3_cmp_l2clk_if { | |
702 | input l2clk CLOCK verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.l2clk"; // Vera interface clock | |
703 | ||
704 | input aclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.aclk"; | |
705 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.aclk_wmr"; | |
706 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.array_wr_inhibit"; | |
707 | input bclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.bclk"; | |
708 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.cmp_slow_sync_en"; | |
709 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.pce_ov"; | |
710 | input por_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.por_"; | |
711 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.scan_out"; | |
712 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.slow_cmp_sync_en"; | |
713 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.wmr_"; | |
714 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.wmr_protect"; | |
715 | } | |
716 | ||
717 | //----- VERA interfaces for clkgen_mio_io ----- | |
718 | ||
719 | interface clkgen_mio_io_gclk_if { | |
720 | input gclk CLOCK verilog_node "`CPU.mio.mio_clk_header_iol2clk.gclk"; // Vera interface clock | |
721 | ||
722 | input aclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.aclk"; | |
723 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.aclk_wmr"; | |
724 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.array_wr_inhibit"; | |
725 | input bclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.bclk"; | |
726 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.ccu_cmp_slow_sync_en"; | |
727 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.ccu_div_ph"; | |
728 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.ccu_serdes_dtm"; | |
729 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.ccu_slow_cmp_sync_en"; | |
730 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.clk_ext"; | |
731 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.cluster_arst_l"; | |
732 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.cluster_div_en"; | |
733 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.cmp_slow_sync_en"; | |
734 | input l2clk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.l2clk"; | |
735 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.pce_ov"; | |
736 | input por_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.por_"; | |
737 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.rst_por_"; | |
738 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.rst_wmr_"; | |
739 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.rst_wmr_protect"; | |
740 | input scan_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.scan_en"; | |
741 | input scan_in PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.scan_in"; | |
742 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.scan_out"; | |
743 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.slow_cmp_sync_en"; | |
744 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.tcu_aclk"; | |
745 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.tcu_atpg_mode"; | |
746 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.tcu_bclk"; | |
747 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.tcu_clk_stop"; | |
748 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.tcu_div_bypass"; | |
749 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.tcu_pce_ov"; | |
750 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.tcu_wr_inhibit"; | |
751 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.wmr_"; | |
752 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.wmr_protect"; | |
753 | } | |
754 | ||
755 | interface clkgen_mio_io_l2clk_if { | |
756 | input l2clk CLOCK verilog_node "`CPU.mio.mio_clk_header_iol2clk.l2clk"; // Vera interface clock | |
757 | ||
758 | input aclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.aclk"; | |
759 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.aclk_wmr"; | |
760 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.array_wr_inhibit"; | |
761 | input bclk PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.bclk"; | |
762 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.cmp_slow_sync_en"; | |
763 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.pce_ov"; | |
764 | input por_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.por_"; | |
765 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.scan_out"; | |
766 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.slow_cmp_sync_en"; | |
767 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.wmr_"; | |
768 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.wmr_protect"; | |
769 | } | |
770 | ||
771 | //----- VERA interfaces for clkgen_ncu_cmp ----- | |
772 | ||
773 | interface clkgen_ncu_cmp_gclk_if { | |
774 | input gclk CLOCK verilog_node "`CPU.ncu.clkgen_ncu_cmp.gclk"; // Vera interface clock | |
775 | ||
776 | input aclk PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.aclk"; | |
777 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.aclk_wmr"; | |
778 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.array_wr_inhibit"; | |
779 | input bclk PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.bclk"; | |
780 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.ccu_cmp_slow_sync_en"; | |
781 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.ccu_div_ph"; | |
782 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.ccu_serdes_dtm"; | |
783 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.ccu_slow_cmp_sync_en"; | |
784 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.clk_ext"; | |
785 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.cluster_arst_l"; | |
786 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.cluster_div_en"; | |
787 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.cmp_slow_sync_en"; | |
788 | input l2clk PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.l2clk"; | |
789 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.pce_ov"; | |
790 | input por_ PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.por_"; | |
791 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.rst_por_"; | |
792 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.rst_wmr_"; | |
793 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.rst_wmr_protect"; | |
794 | input scan_en PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.scan_en"; | |
795 | input scan_in PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.scan_in"; | |
796 | input scan_out PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.scan_out"; | |
797 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.slow_cmp_sync_en"; | |
798 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.tcu_aclk"; | |
799 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.tcu_atpg_mode"; | |
800 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.tcu_bclk"; | |
801 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.tcu_clk_stop"; | |
802 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.tcu_div_bypass"; | |
803 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.tcu_pce_ov"; | |
804 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.tcu_wr_inhibit"; | |
805 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.wmr_"; | |
806 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.wmr_protect"; | |
807 | } | |
808 | ||
809 | interface clkgen_ncu_cmp_l2clk_if { | |
810 | input l2clk CLOCK verilog_node "`CPU.ncu.clkgen_ncu_cmp.l2clk"; // Vera interface clock | |
811 | ||
812 | input aclk PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.aclk"; | |
813 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.aclk_wmr"; | |
814 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.array_wr_inhibit"; | |
815 | input bclk PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.bclk"; | |
816 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.cmp_slow_sync_en"; | |
817 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.pce_ov"; | |
818 | input por_ PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.por_"; | |
819 | input scan_out PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.scan_out"; | |
820 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.slow_cmp_sync_en"; | |
821 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.wmr_"; | |
822 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.wmr_protect"; | |
823 | } | |
824 | ||
825 | //----- VERA interfaces for clkgen_ncu_io ----- | |
826 | ||
827 | interface clkgen_ncu_io_gclk_if { | |
828 | input gclk CLOCK verilog_node "`CPU.ncu.clkgen_ncu_io.gclk"; // Vera interface clock | |
829 | ||
830 | input aclk PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.aclk"; | |
831 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.aclk_wmr"; | |
832 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.array_wr_inhibit"; | |
833 | input bclk PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.bclk"; | |
834 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.ccu_cmp_slow_sync_en"; | |
835 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.ccu_div_ph"; | |
836 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.ccu_serdes_dtm"; | |
837 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.ccu_slow_cmp_sync_en"; | |
838 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.clk_ext"; | |
839 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.cluster_arst_l"; | |
840 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.cluster_div_en"; | |
841 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.cmp_slow_sync_en"; | |
842 | input l2clk PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.l2clk"; | |
843 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.pce_ov"; | |
844 | input por_ PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.por_"; | |
845 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.rst_por_"; | |
846 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.rst_wmr_"; | |
847 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.rst_wmr_protect"; | |
848 | input scan_en PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.scan_en"; | |
849 | input scan_in PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.scan_in"; | |
850 | input scan_out PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.scan_out"; | |
851 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.slow_cmp_sync_en"; | |
852 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.tcu_aclk"; | |
853 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.tcu_atpg_mode"; | |
854 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.tcu_bclk"; | |
855 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.tcu_clk_stop"; | |
856 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.tcu_div_bypass"; | |
857 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.tcu_pce_ov"; | |
858 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.tcu_wr_inhibit"; | |
859 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.wmr_"; | |
860 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.wmr_protect"; | |
861 | } | |
862 | ||
863 | interface clkgen_ncu_io_l2clk_if { | |
864 | input l2clk CLOCK verilog_node "`CPU.ncu.clkgen_ncu_io.l2clk"; // Vera interface clock | |
865 | ||
866 | input aclk PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.aclk"; | |
867 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.aclk_wmr"; | |
868 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.array_wr_inhibit"; | |
869 | input bclk PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.bclk"; | |
870 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.cmp_slow_sync_en"; | |
871 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.pce_ov"; | |
872 | input por_ PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.por_"; | |
873 | input scan_out PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.scan_out"; | |
874 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.slow_cmp_sync_en"; | |
875 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.wmr_"; | |
876 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.wmr_protect"; | |
877 | } | |
878 | ||
879 | //----- VERA interfaces for clkgen_rst_cmp ----- | |
880 | ||
881 | interface clkgen_rst_cmp_gclk_if { | |
882 | input gclk CLOCK verilog_node "`CPU.rst.clkgen_rst_cmp.gclk"; // Vera interface clock | |
883 | ||
884 | input aclk PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.aclk"; | |
885 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.aclk_wmr"; | |
886 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.array_wr_inhibit"; | |
887 | input bclk PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.bclk"; | |
888 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.ccu_cmp_slow_sync_en"; | |
889 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.ccu_div_ph"; | |
890 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.ccu_serdes_dtm"; | |
891 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.ccu_slow_cmp_sync_en"; | |
892 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.clk_ext"; | |
893 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.cluster_arst_l"; | |
894 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.cluster_div_en"; | |
895 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.cmp_slow_sync_en"; | |
896 | input l2clk PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.l2clk"; | |
897 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.pce_ov"; | |
898 | input por_ PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.por_"; | |
899 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.rst_por_"; | |
900 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.rst_wmr_"; | |
901 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.rst_wmr_protect"; | |
902 | input scan_en PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.scan_en"; | |
903 | input scan_in PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.scan_in"; | |
904 | input scan_out PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.scan_out"; | |
905 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.slow_cmp_sync_en"; | |
906 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.tcu_aclk"; | |
907 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.tcu_atpg_mode"; | |
908 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.tcu_bclk"; | |
909 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.tcu_clk_stop"; | |
910 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.tcu_div_bypass"; | |
911 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.tcu_pce_ov"; | |
912 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.tcu_wr_inhibit"; | |
913 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.wmr_"; | |
914 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.wmr_protect"; | |
915 | } | |
916 | ||
917 | interface clkgen_rst_cmp_l2clk_if { | |
918 | input l2clk CLOCK verilog_node "`CPU.rst.clkgen_rst_cmp.l2clk"; // Vera interface clock | |
919 | ||
920 | input aclk PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.aclk"; | |
921 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.aclk_wmr"; | |
922 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.array_wr_inhibit"; | |
923 | input bclk PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.bclk"; | |
924 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.cmp_slow_sync_en"; | |
925 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.pce_ov"; | |
926 | input por_ PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.por_"; | |
927 | input scan_out PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.scan_out"; | |
928 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.slow_cmp_sync_en"; | |
929 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.wmr_"; | |
930 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.wmr_protect"; | |
931 | } | |
932 | ||
933 | //----- VERA interfaces for clkgen_rst_io ----- | |
934 | ||
935 | interface clkgen_rst_io_gclk_if { | |
936 | input gclk CLOCK verilog_node "`CPU.rst.clkgen_rst_io.gclk"; // Vera interface clock | |
937 | ||
938 | input aclk PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.aclk"; | |
939 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.aclk_wmr"; | |
940 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.array_wr_inhibit"; | |
941 | input bclk PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.bclk"; | |
942 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.ccu_cmp_slow_sync_en"; | |
943 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.ccu_div_ph"; | |
944 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.ccu_serdes_dtm"; | |
945 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.ccu_slow_cmp_sync_en"; | |
946 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.clk_ext"; | |
947 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.cluster_arst_l"; | |
948 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.cluster_div_en"; | |
949 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.cmp_slow_sync_en"; | |
950 | input l2clk PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.l2clk"; | |
951 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.pce_ov"; | |
952 | input por_ PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.por_"; | |
953 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.rst_por_"; | |
954 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.rst_wmr_"; | |
955 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.rst_wmr_protect"; | |
956 | input scan_en PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.scan_en"; | |
957 | input scan_in PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.scan_in"; | |
958 | input scan_out PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.scan_out"; | |
959 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.slow_cmp_sync_en"; | |
960 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.tcu_aclk"; | |
961 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.tcu_atpg_mode"; | |
962 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.tcu_bclk"; | |
963 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.tcu_clk_stop"; | |
964 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.tcu_div_bypass"; | |
965 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.tcu_pce_ov"; | |
966 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.tcu_wr_inhibit"; | |
967 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.wmr_"; | |
968 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.wmr_protect"; | |
969 | } | |
970 | ||
971 | interface clkgen_rst_io_l2clk_if { | |
972 | input l2clk CLOCK verilog_node "`CPU.rst.clkgen_rst_io.l2clk"; // Vera interface clock | |
973 | ||
974 | input aclk PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.aclk"; | |
975 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.aclk_wmr"; | |
976 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.array_wr_inhibit"; | |
977 | input bclk PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.bclk"; | |
978 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.cmp_slow_sync_en"; | |
979 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.pce_ov"; | |
980 | input por_ PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.por_"; | |
981 | input scan_out PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.scan_out"; | |
982 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.slow_cmp_sync_en"; | |
983 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.wmr_"; | |
984 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.wmr_protect"; | |
985 | } | |
986 | ||
987 | //----- VERA interfaces for clkgen_tcu_cmp ----- | |
988 | ||
989 | interface clkgen_tcu_cmp_gclk_if { | |
990 | input gclk CLOCK verilog_node "`CPU.tcu.clkgen_tcu_cmp.gclk"; // Vera interface clock | |
991 | ||
992 | input aclk PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.aclk"; | |
993 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.aclk_wmr"; | |
994 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.array_wr_inhibit"; | |
995 | input bclk PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.bclk"; | |
996 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.ccu_cmp_slow_sync_en"; | |
997 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.ccu_div_ph"; | |
998 | input ccu_dr_sync_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.ccu_dr_sync_en"; | |
999 | input ccu_io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.ccu_io2x_sync_en"; | |
1000 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.ccu_serdes_dtm"; | |
1001 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.ccu_slow_cmp_sync_en"; | |
1002 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.clk_ext"; | |
1003 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.cluster_arst_l"; | |
1004 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.cluster_div_en"; | |
1005 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.cmp_slow_sync_en"; | |
1006 | input dr_sync_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.dr_sync_en"; | |
1007 | input io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.io2x_sync_en"; | |
1008 | input l2clk PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.l2clk"; | |
1009 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.pce_ov"; | |
1010 | input por_ PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.por_"; | |
1011 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.rst_por_"; | |
1012 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.rst_wmr_"; | |
1013 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.rst_wmr_protect"; | |
1014 | input scan_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.scan_en"; | |
1015 | input scan_in PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.scan_in"; | |
1016 | input scan_out PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.scan_out"; | |
1017 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.slow_cmp_sync_en"; | |
1018 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.tcu_aclk"; | |
1019 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.tcu_atpg_mode"; | |
1020 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.tcu_bclk"; | |
1021 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.tcu_clk_stop"; | |
1022 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.tcu_div_bypass"; | |
1023 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.tcu_pce_ov"; | |
1024 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.tcu_wr_inhibit"; | |
1025 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.wmr_"; | |
1026 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.wmr_protect"; | |
1027 | } | |
1028 | ||
1029 | interface clkgen_tcu_cmp_l2clk_if { | |
1030 | input l2clk CLOCK verilog_node "`CPU.tcu.clkgen_tcu_cmp.l2clk"; // Vera interface clock | |
1031 | ||
1032 | input aclk PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.aclk"; | |
1033 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.aclk_wmr"; | |
1034 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.array_wr_inhibit"; | |
1035 | input bclk PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.bclk"; | |
1036 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.cmp_slow_sync_en"; | |
1037 | input dr_sync_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.dr_sync_en"; | |
1038 | input io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.io2x_sync_en"; | |
1039 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.pce_ov"; | |
1040 | input por_ PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.por_"; | |
1041 | input scan_out PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.scan_out"; | |
1042 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.slow_cmp_sync_en"; | |
1043 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.wmr_"; | |
1044 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.wmr_protect"; | |
1045 | } | |
1046 | ||
1047 | //----- VERA interfaces for clkgen_tcu_io ----- | |
1048 | ||
1049 | interface clkgen_tcu_io_gclk_if { | |
1050 | input gclk CLOCK verilog_node "`CPU.tcu.clkgen_tcu_io.gclk"; // Vera interface clock | |
1051 | ||
1052 | input aclk PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.aclk"; | |
1053 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.aclk_wmr"; | |
1054 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.array_wr_inhibit"; | |
1055 | input bclk PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.bclk"; | |
1056 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.ccu_cmp_slow_sync_en"; | |
1057 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.ccu_div_ph"; | |
1058 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.ccu_serdes_dtm"; | |
1059 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.ccu_slow_cmp_sync_en"; | |
1060 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.clk_ext"; | |
1061 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.cluster_arst_l"; | |
1062 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.cluster_div_en"; | |
1063 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.cmp_slow_sync_en"; | |
1064 | input l2clk PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.l2clk"; | |
1065 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.pce_ov"; | |
1066 | input por_ PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.por_"; | |
1067 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.rst_por_"; | |
1068 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.rst_wmr_"; | |
1069 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.rst_wmr_protect"; | |
1070 | input scan_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.scan_en"; | |
1071 | input scan_in PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.scan_in"; | |
1072 | input scan_out PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.scan_out"; | |
1073 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.slow_cmp_sync_en"; | |
1074 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.tcu_aclk"; | |
1075 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.tcu_atpg_mode"; | |
1076 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.tcu_bclk"; | |
1077 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.tcu_clk_stop"; | |
1078 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.tcu_div_bypass"; | |
1079 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.tcu_pce_ov"; | |
1080 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.tcu_wr_inhibit"; | |
1081 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.wmr_"; | |
1082 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.wmr_protect"; | |
1083 | } | |
1084 | ||
1085 | interface clkgen_tcu_io_l2clk_if { | |
1086 | input l2clk CLOCK verilog_node "`CPU.tcu.clkgen_tcu_io.l2clk"; // Vera interface clock | |
1087 | ||
1088 | input aclk PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.aclk"; | |
1089 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.aclk_wmr"; | |
1090 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.array_wr_inhibit"; | |
1091 | input bclk PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.bclk"; | |
1092 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.cmp_slow_sync_en"; | |
1093 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.pce_ov"; | |
1094 | input por_ PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.por_"; | |
1095 | input scan_out PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.scan_out"; | |
1096 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.slow_cmp_sync_en"; | |
1097 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.wmr_"; | |
1098 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.wmr_protect"; | |
1099 | } | |
1100 | ||
1101 | //############################################################## | |
1102 | //### interfaces for cluster headers (blocks not in TCU SAT) ### | |
1103 | //############################################################## | |
1104 | ||
1105 | #ifdef FC_BENCH | |
1106 | ||
1107 | //----- VERA interfaces for clkgen_ccx_cmp ----- | |
1108 | ||
1109 | //--- gclk_left, tcu_clk_stop_left, tcu_div_bypass_left. Need to check them | |
1110 | //--- with 0-in assertions | |
1111 | ||
1112 | interface clkgen_ccx_cmp_gclk_if { | |
1113 | input gclk CLOCK verilog_node "`CPU.ccx.clk_ccx.gclk_right"; // Vera interface clock | |
1114 | ||
1115 | input aclk PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.aclk"; | |
1116 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.aclk_wmr"; | |
1117 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.array_wr_inhibit"; | |
1118 | input bclk PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.bclk"; | |
1119 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.ccu_cmp_slow_sync_en"; | |
1120 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.ccu_div_ph"; | |
1121 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.ccu_serdes_dtm"; | |
1122 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.ccu_slow_cmp_sync_en"; | |
1123 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.clk_ext"; | |
1124 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.cluster_arst_l_right"; | |
1125 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.cluster_div_en"; | |
1126 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.cmp_slow_sync_en"; | |
1127 | input l2clk PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.l2clk"; | |
1128 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.pce_ov"; | |
1129 | input por_ PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.por_"; | |
1130 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.rst_por_"; | |
1131 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.rst_wmr_"; | |
1132 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.rst_wmr_protect"; | |
1133 | input scan_en PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.scan_en"; | |
1134 | input scan_in PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.scan_in"; | |
1135 | input scan_out PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.scan_out"; | |
1136 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.slow_cmp_sync_en"; | |
1137 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.tcu_aclk"; | |
1138 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.tcu_atpg_mode"; | |
1139 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.tcu_bclk"; | |
1140 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.tcu_clk_stop_right"; | |
1141 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.tcu_div_bypass_right"; | |
1142 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.tcu_pce_ov"; | |
1143 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.tcu_wr_inhibit"; | |
1144 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.wmr_"; | |
1145 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.wmr_protect"; | |
1146 | } | |
1147 | ||
1148 | interface clkgen_ccx_cmp_l2clk_if { | |
1149 | input l2clk CLOCK verilog_node "`CPU.ccx.clk_ccx.l2clk"; // Vera interface clock | |
1150 | ||
1151 | input aclk PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.aclk"; | |
1152 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.aclk_wmr"; | |
1153 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.array_wr_inhibit"; | |
1154 | input bclk PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.bclk"; | |
1155 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.cmp_slow_sync_en"; | |
1156 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.pce_ov"; | |
1157 | input por_ PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.por_"; | |
1158 | input scan_out PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.scan_out"; | |
1159 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.slow_cmp_sync_en"; | |
1160 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.wmr_"; | |
1161 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.wmr_protect"; | |
1162 | } | |
1163 | ||
1164 | //----- VERA interfaces for clkgen_dmu_io ----- | |
1165 | ||
1166 | interface clkgen_dmu_io_gclk_if { | |
1167 | input gclk CLOCK verilog_node "`CPU.dmu.dmu_clkgen.gclk"; // Vera interface clock | |
1168 | ||
1169 | input aclk PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.aclk"; | |
1170 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.aclk_wmr"; | |
1171 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.array_wr_inhibit"; | |
1172 | input bclk PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.bclk"; | |
1173 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.ccu_cmp_slow_sync_en"; | |
1174 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.ccu_div_ph"; | |
1175 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.ccu_serdes_dtm"; | |
1176 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.ccu_slow_cmp_sync_en"; | |
1177 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.clk_ext"; | |
1178 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.cluster_arst_l"; | |
1179 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.cluster_div_en"; | |
1180 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.cmp_slow_sync_en"; | |
1181 | input l2clk PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.l2clk"; | |
1182 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.pce_ov"; | |
1183 | input por_ PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.por_"; | |
1184 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.rst_por_"; | |
1185 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.rst_wmr_"; | |
1186 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.rst_wmr_protect"; | |
1187 | input scan_en PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.scan_en"; | |
1188 | input scan_in PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.scan_in"; | |
1189 | input scan_out PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.scan_out"; | |
1190 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.slow_cmp_sync_en"; | |
1191 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.tcu_aclk"; | |
1192 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.tcu_atpg_mode"; | |
1193 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.tcu_bclk"; | |
1194 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.tcu_clk_stop"; | |
1195 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.tcu_div_bypass"; | |
1196 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.tcu_pce_ov"; | |
1197 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.tcu_wr_inhibit"; | |
1198 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.wmr_"; | |
1199 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.wmr_protect"; | |
1200 | } | |
1201 | ||
1202 | interface clkgen_dmu_io_l2clk_if { | |
1203 | input l2clk CLOCK verilog_node "`CPU.dmu.dmu_clkgen.l2clk"; // Vera interface clock | |
1204 | ||
1205 | input aclk PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.aclk"; | |
1206 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.aclk_wmr"; | |
1207 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.array_wr_inhibit"; | |
1208 | input bclk PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.bclk"; | |
1209 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.cmp_slow_sync_en"; | |
1210 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.pce_ov"; | |
1211 | input por_ PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.por_"; | |
1212 | input scan_out PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.scan_out"; | |
1213 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.slow_cmp_sync_en"; | |
1214 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.wmr_"; | |
1215 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.wmr_protect"; | |
1216 | } | |
1217 | ||
1218 | //----- VERA interfaces for clkgen_l2b0_cmp ----- | |
1219 | ||
1220 | interface clkgen_l2b0_cmp_gclk_if { | |
1221 | input gclk CLOCK verilog_node "`CPU.l2b0.clock_header.gclk"; // Vera interface clock | |
1222 | ||
1223 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.aclk"; | |
1224 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.aclk_wmr"; | |
1225 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.array_wr_inhibit"; | |
1226 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.bclk"; | |
1227 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.ccu_cmp_slow_sync_en"; | |
1228 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.ccu_div_ph"; | |
1229 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.ccu_serdes_dtm"; | |
1230 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.ccu_slow_cmp_sync_en"; | |
1231 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.clk_ext"; | |
1232 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.cluster_arst_l"; | |
1233 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.cluster_div_en"; | |
1234 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.cmp_slow_sync_en"; | |
1235 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.l2clk"; | |
1236 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.pce_ov"; | |
1237 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.por_"; | |
1238 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.rst_por_"; | |
1239 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.rst_wmr_"; | |
1240 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.rst_wmr_protect"; | |
1241 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.scan_en"; | |
1242 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.scan_in"; | |
1243 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.scan_out"; | |
1244 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.slow_cmp_sync_en"; | |
1245 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.tcu_aclk"; | |
1246 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.tcu_atpg_mode"; | |
1247 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.tcu_bclk"; | |
1248 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.tcu_clk_stop"; | |
1249 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.tcu_div_bypass"; | |
1250 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.tcu_pce_ov"; | |
1251 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.tcu_wr_inhibit"; | |
1252 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.wmr_"; | |
1253 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.wmr_protect"; | |
1254 | } | |
1255 | ||
1256 | interface clkgen_l2b0_cmp_l2clk_if { | |
1257 | input l2clk CLOCK verilog_node "`CPU.l2b0.clock_header.l2clk"; // Vera interface clock | |
1258 | ||
1259 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.aclk"; | |
1260 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.aclk_wmr"; | |
1261 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.array_wr_inhibit"; | |
1262 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.bclk"; | |
1263 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.cmp_slow_sync_en"; | |
1264 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.pce_ov"; | |
1265 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.por_"; | |
1266 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.scan_out"; | |
1267 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.slow_cmp_sync_en"; | |
1268 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.wmr_"; | |
1269 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.wmr_protect"; | |
1270 | } | |
1271 | ||
1272 | //----- VERA interfaces for clkgen_l2b1_cmp ----- | |
1273 | ||
1274 | interface clkgen_l2b1_cmp_gclk_if { | |
1275 | input gclk CLOCK verilog_node "`CPU.l2b1.clock_header.gclk"; // Vera interface clock | |
1276 | ||
1277 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.aclk"; | |
1278 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.aclk_wmr"; | |
1279 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.array_wr_inhibit"; | |
1280 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.bclk"; | |
1281 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.ccu_cmp_slow_sync_en"; | |
1282 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.ccu_div_ph"; | |
1283 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.ccu_serdes_dtm"; | |
1284 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.ccu_slow_cmp_sync_en"; | |
1285 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.clk_ext"; | |
1286 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.cluster_arst_l"; | |
1287 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.cluster_div_en"; | |
1288 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.cmp_slow_sync_en"; | |
1289 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.l2clk"; | |
1290 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.pce_ov"; | |
1291 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.por_"; | |
1292 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.rst_por_"; | |
1293 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.rst_wmr_"; | |
1294 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.rst_wmr_protect"; | |
1295 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.scan_en"; | |
1296 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.scan_in"; | |
1297 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.scan_out"; | |
1298 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.slow_cmp_sync_en"; | |
1299 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.tcu_aclk"; | |
1300 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.tcu_atpg_mode"; | |
1301 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.tcu_bclk"; | |
1302 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.tcu_clk_stop"; | |
1303 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.tcu_div_bypass"; | |
1304 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.tcu_pce_ov"; | |
1305 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.tcu_wr_inhibit"; | |
1306 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.wmr_"; | |
1307 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.wmr_protect"; | |
1308 | } | |
1309 | ||
1310 | interface clkgen_l2b1_cmp_l2clk_if { | |
1311 | input l2clk CLOCK verilog_node "`CPU.l2b1.clock_header.l2clk"; // Vera interface clock | |
1312 | ||
1313 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.aclk"; | |
1314 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.aclk_wmr"; | |
1315 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.array_wr_inhibit"; | |
1316 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.bclk"; | |
1317 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.cmp_slow_sync_en"; | |
1318 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.pce_ov"; | |
1319 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.por_"; | |
1320 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.scan_out"; | |
1321 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.slow_cmp_sync_en"; | |
1322 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.wmr_"; | |
1323 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.wmr_protect"; | |
1324 | } | |
1325 | ||
1326 | //----- VERA interfaces for clkgen_l2b2_cmp ----- | |
1327 | ||
1328 | interface clkgen_l2b2_cmp_gclk_if { | |
1329 | input gclk CLOCK verilog_node "`CPU.l2b2.clock_header.gclk"; // Vera interface clock | |
1330 | ||
1331 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.aclk"; | |
1332 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.aclk_wmr"; | |
1333 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.array_wr_inhibit"; | |
1334 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.bclk"; | |
1335 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.ccu_cmp_slow_sync_en"; | |
1336 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.ccu_div_ph"; | |
1337 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.ccu_serdes_dtm"; | |
1338 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.ccu_slow_cmp_sync_en"; | |
1339 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.clk_ext"; | |
1340 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.cluster_arst_l"; | |
1341 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.cluster_div_en"; | |
1342 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.cmp_slow_sync_en"; | |
1343 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.l2clk"; | |
1344 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.pce_ov"; | |
1345 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.por_"; | |
1346 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.rst_por_"; | |
1347 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.rst_wmr_"; | |
1348 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.rst_wmr_protect"; | |
1349 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.scan_en"; | |
1350 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.scan_in"; | |
1351 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.scan_out"; | |
1352 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.slow_cmp_sync_en"; | |
1353 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.tcu_aclk"; | |
1354 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.tcu_atpg_mode"; | |
1355 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.tcu_bclk"; | |
1356 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.tcu_clk_stop"; | |
1357 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.tcu_div_bypass"; | |
1358 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.tcu_pce_ov"; | |
1359 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.tcu_wr_inhibit"; | |
1360 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.wmr_"; | |
1361 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.wmr_protect"; | |
1362 | } | |
1363 | ||
1364 | interface clkgen_l2b2_cmp_l2clk_if { | |
1365 | input l2clk CLOCK verilog_node "`CPU.l2b2.clock_header.l2clk"; // Vera interface clock | |
1366 | ||
1367 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.aclk"; | |
1368 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.aclk_wmr"; | |
1369 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.array_wr_inhibit"; | |
1370 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.bclk"; | |
1371 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.cmp_slow_sync_en"; | |
1372 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.pce_ov"; | |
1373 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.por_"; | |
1374 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.scan_out"; | |
1375 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.slow_cmp_sync_en"; | |
1376 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.wmr_"; | |
1377 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.wmr_protect"; | |
1378 | } | |
1379 | ||
1380 | //----- VERA interfaces for clkgen_l2b3_cmp ----- | |
1381 | ||
1382 | interface clkgen_l2b3_cmp_gclk_if { | |
1383 | input gclk CLOCK verilog_node "`CPU.l2b3.clock_header.gclk"; // Vera interface clock | |
1384 | ||
1385 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.aclk"; | |
1386 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.aclk_wmr"; | |
1387 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.array_wr_inhibit"; | |
1388 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.bclk"; | |
1389 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.ccu_cmp_slow_sync_en"; | |
1390 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.ccu_div_ph"; | |
1391 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.ccu_serdes_dtm"; | |
1392 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.ccu_slow_cmp_sync_en"; | |
1393 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.clk_ext"; | |
1394 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.cluster_arst_l"; | |
1395 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.cluster_div_en"; | |
1396 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.cmp_slow_sync_en"; | |
1397 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.l2clk"; | |
1398 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.pce_ov"; | |
1399 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.por_"; | |
1400 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.rst_por_"; | |
1401 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.rst_wmr_"; | |
1402 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.rst_wmr_protect"; | |
1403 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.scan_en"; | |
1404 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.scan_in"; | |
1405 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.scan_out"; | |
1406 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.slow_cmp_sync_en"; | |
1407 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.tcu_aclk"; | |
1408 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.tcu_atpg_mode"; | |
1409 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.tcu_bclk"; | |
1410 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.tcu_clk_stop"; | |
1411 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.tcu_div_bypass"; | |
1412 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.tcu_pce_ov"; | |
1413 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.tcu_wr_inhibit"; | |
1414 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.wmr_"; | |
1415 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.wmr_protect"; | |
1416 | } | |
1417 | ||
1418 | interface clkgen_l2b3_cmp_l2clk_if { | |
1419 | input l2clk CLOCK verilog_node "`CPU.l2b3.clock_header.l2clk"; // Vera interface clock | |
1420 | ||
1421 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.aclk"; | |
1422 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.aclk_wmr"; | |
1423 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.array_wr_inhibit"; | |
1424 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.bclk"; | |
1425 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.cmp_slow_sync_en"; | |
1426 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.pce_ov"; | |
1427 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.por_"; | |
1428 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.scan_out"; | |
1429 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.slow_cmp_sync_en"; | |
1430 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.wmr_"; | |
1431 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.wmr_protect"; | |
1432 | } | |
1433 | ||
1434 | //----- VERA interfaces for clkgen_l2b4_cmp ----- | |
1435 | ||
1436 | interface clkgen_l2b4_cmp_gclk_if { | |
1437 | input gclk CLOCK verilog_node "`CPU.l2b4.clock_header.gclk"; // Vera interface clock | |
1438 | ||
1439 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.aclk"; | |
1440 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.aclk_wmr"; | |
1441 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.array_wr_inhibit"; | |
1442 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.bclk"; | |
1443 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.ccu_cmp_slow_sync_en"; | |
1444 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.ccu_div_ph"; | |
1445 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.ccu_serdes_dtm"; | |
1446 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.ccu_slow_cmp_sync_en"; | |
1447 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.clk_ext"; | |
1448 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.cluster_arst_l"; | |
1449 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.cluster_div_en"; | |
1450 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.cmp_slow_sync_en"; | |
1451 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.l2clk"; | |
1452 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.pce_ov"; | |
1453 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.por_"; | |
1454 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.rst_por_"; | |
1455 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.rst_wmr_"; | |
1456 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.rst_wmr_protect"; | |
1457 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.scan_en"; | |
1458 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.scan_in"; | |
1459 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.scan_out"; | |
1460 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.slow_cmp_sync_en"; | |
1461 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.tcu_aclk"; | |
1462 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.tcu_atpg_mode"; | |
1463 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.tcu_bclk"; | |
1464 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.tcu_clk_stop"; | |
1465 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.tcu_div_bypass"; | |
1466 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.tcu_pce_ov"; | |
1467 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.tcu_wr_inhibit"; | |
1468 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.wmr_"; | |
1469 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.wmr_protect"; | |
1470 | } | |
1471 | ||
1472 | interface clkgen_l2b4_cmp_l2clk_if { | |
1473 | input l2clk CLOCK verilog_node "`CPU.l2b4.clock_header.l2clk"; // Vera interface clock | |
1474 | ||
1475 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.aclk"; | |
1476 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.aclk_wmr"; | |
1477 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.array_wr_inhibit"; | |
1478 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.bclk"; | |
1479 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.cmp_slow_sync_en"; | |
1480 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.pce_ov"; | |
1481 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.por_"; | |
1482 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.scan_out"; | |
1483 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.slow_cmp_sync_en"; | |
1484 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.wmr_"; | |
1485 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.wmr_protect"; | |
1486 | } | |
1487 | ||
1488 | //----- VERA interfaces for clkgen_l2b5_cmp ----- | |
1489 | ||
1490 | interface clkgen_l2b5_cmp_gclk_if { | |
1491 | input gclk CLOCK verilog_node "`CPU.l2b5.clock_header.gclk"; // Vera interface clock | |
1492 | ||
1493 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.aclk"; | |
1494 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.aclk_wmr"; | |
1495 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.array_wr_inhibit"; | |
1496 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.bclk"; | |
1497 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.ccu_cmp_slow_sync_en"; | |
1498 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.ccu_div_ph"; | |
1499 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.ccu_serdes_dtm"; | |
1500 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.ccu_slow_cmp_sync_en"; | |
1501 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.clk_ext"; | |
1502 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.cluster_arst_l"; | |
1503 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.cluster_div_en"; | |
1504 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.cmp_slow_sync_en"; | |
1505 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.l2clk"; | |
1506 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.pce_ov"; | |
1507 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.por_"; | |
1508 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.rst_por_"; | |
1509 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.rst_wmr_"; | |
1510 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.rst_wmr_protect"; | |
1511 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.scan_en"; | |
1512 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.scan_in"; | |
1513 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.scan_out"; | |
1514 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.slow_cmp_sync_en"; | |
1515 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.tcu_aclk"; | |
1516 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.tcu_atpg_mode"; | |
1517 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.tcu_bclk"; | |
1518 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.tcu_clk_stop"; | |
1519 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.tcu_div_bypass"; | |
1520 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.tcu_pce_ov"; | |
1521 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.tcu_wr_inhibit"; | |
1522 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.wmr_"; | |
1523 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.wmr_protect"; | |
1524 | } | |
1525 | ||
1526 | interface clkgen_l2b5_cmp_l2clk_if { | |
1527 | input l2clk CLOCK verilog_node "`CPU.l2b5.clock_header.l2clk"; // Vera interface clock | |
1528 | ||
1529 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.aclk"; | |
1530 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.aclk_wmr"; | |
1531 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.array_wr_inhibit"; | |
1532 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.bclk"; | |
1533 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.cmp_slow_sync_en"; | |
1534 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.pce_ov"; | |
1535 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.por_"; | |
1536 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.scan_out"; | |
1537 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.slow_cmp_sync_en"; | |
1538 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.wmr_"; | |
1539 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.wmr_protect"; | |
1540 | } | |
1541 | ||
1542 | //----- VERA interfaces for clkgen_l2b6_cmp ----- | |
1543 | ||
1544 | interface clkgen_l2b6_cmp_gclk_if { | |
1545 | input gclk CLOCK verilog_node "`CPU.l2b6.clock_header.gclk"; // Vera interface clock | |
1546 | ||
1547 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.aclk"; | |
1548 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.aclk_wmr"; | |
1549 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.array_wr_inhibit"; | |
1550 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.bclk"; | |
1551 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.ccu_cmp_slow_sync_en"; | |
1552 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.ccu_div_ph"; | |
1553 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.ccu_serdes_dtm"; | |
1554 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.ccu_slow_cmp_sync_en"; | |
1555 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.clk_ext"; | |
1556 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.cluster_arst_l"; | |
1557 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.cluster_div_en"; | |
1558 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.cmp_slow_sync_en"; | |
1559 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.l2clk"; | |
1560 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.pce_ov"; | |
1561 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.por_"; | |
1562 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.rst_por_"; | |
1563 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.rst_wmr_"; | |
1564 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.rst_wmr_protect"; | |
1565 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.scan_en"; | |
1566 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.scan_in"; | |
1567 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.scan_out"; | |
1568 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.slow_cmp_sync_en"; | |
1569 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.tcu_aclk"; | |
1570 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.tcu_atpg_mode"; | |
1571 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.tcu_bclk"; | |
1572 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.tcu_clk_stop"; | |
1573 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.tcu_div_bypass"; | |
1574 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.tcu_pce_ov"; | |
1575 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.tcu_wr_inhibit"; | |
1576 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.wmr_"; | |
1577 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.wmr_protect"; | |
1578 | } | |
1579 | ||
1580 | interface clkgen_l2b6_cmp_l2clk_if { | |
1581 | input l2clk CLOCK verilog_node "`CPU.l2b6.clock_header.l2clk"; // Vera interface clock | |
1582 | ||
1583 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.aclk"; | |
1584 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.aclk_wmr"; | |
1585 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.array_wr_inhibit"; | |
1586 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.bclk"; | |
1587 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.cmp_slow_sync_en"; | |
1588 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.pce_ov"; | |
1589 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.por_"; | |
1590 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.scan_out"; | |
1591 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.slow_cmp_sync_en"; | |
1592 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.wmr_"; | |
1593 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.wmr_protect"; | |
1594 | } | |
1595 | ||
1596 | //----- VERA interfaces for clkgen_l2b7_cmp ----- | |
1597 | ||
1598 | interface clkgen_l2b7_cmp_gclk_if { | |
1599 | input gclk CLOCK verilog_node "`CPU.l2b7.clock_header.gclk"; // Vera interface clock | |
1600 | ||
1601 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.aclk"; | |
1602 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.aclk_wmr"; | |
1603 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.array_wr_inhibit"; | |
1604 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.bclk"; | |
1605 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.ccu_cmp_slow_sync_en"; | |
1606 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.ccu_div_ph"; | |
1607 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.ccu_serdes_dtm"; | |
1608 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.ccu_slow_cmp_sync_en"; | |
1609 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.clk_ext"; | |
1610 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.cluster_arst_l"; | |
1611 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.cluster_div_en"; | |
1612 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.cmp_slow_sync_en"; | |
1613 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.l2clk"; | |
1614 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.pce_ov"; | |
1615 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.por_"; | |
1616 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.rst_por_"; | |
1617 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.rst_wmr_"; | |
1618 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.rst_wmr_protect"; | |
1619 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.scan_en"; | |
1620 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.scan_in"; | |
1621 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.scan_out"; | |
1622 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.slow_cmp_sync_en"; | |
1623 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.tcu_aclk"; | |
1624 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.tcu_atpg_mode"; | |
1625 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.tcu_bclk"; | |
1626 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.tcu_clk_stop"; | |
1627 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.tcu_div_bypass"; | |
1628 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.tcu_pce_ov"; | |
1629 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.tcu_wr_inhibit"; | |
1630 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.wmr_"; | |
1631 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.wmr_protect"; | |
1632 | } | |
1633 | ||
1634 | interface clkgen_l2b7_cmp_l2clk_if { | |
1635 | input l2clk CLOCK verilog_node "`CPU.l2b7.clock_header.l2clk"; // Vera interface clock | |
1636 | ||
1637 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.aclk"; | |
1638 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.aclk_wmr"; | |
1639 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.array_wr_inhibit"; | |
1640 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.bclk"; | |
1641 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.cmp_slow_sync_en"; | |
1642 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.pce_ov"; | |
1643 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.por_"; | |
1644 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.scan_out"; | |
1645 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.slow_cmp_sync_en"; | |
1646 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.wmr_"; | |
1647 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.wmr_protect"; | |
1648 | } | |
1649 | ||
1650 | //----- VERA interfaces for clkgen_l2d0_cmp ----- | |
1651 | //----- warning: l2d<n> do NOT use clkgen_l2d_cmp, but instantiates | |
1652 | //----- n2_clk_clstr_hdr_cust and pregrid drivers (ie. n2_clk_l2d_cmp_cust) directly | |
1653 | ||
1654 | interface clkgen_l2d0_cmp_gclk_if { | |
1655 | input gclk CLOCK verilog_node "`CPU.l2d0.l2d_clk_header.gclk"; // Vera interface clock | |
1656 | ||
1657 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.aclk"; | |
1658 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.aclk_wmr"; | |
1659 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.array_wr_inhibit"; | |
1660 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.bclk"; | |
1661 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.ccu_cmp_slow_sync_en"; | |
1662 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.ccu_div_ph"; | |
1663 | //input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.ccu_serdes_dtm"; // does NOT have this port | |
1664 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.ccu_slow_cmp_sync_en"; | |
1665 | //input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.clk_ext"; // does NOT have this port | |
1666 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.cluster_arst_l"; | |
1667 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.cluster_div_en"; | |
1668 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.cmp_slow_sync_en"; | |
1669 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_pregrid_drv_bot.l2clk"; // warning: this is real l2clk | |
1670 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.pce_ov"; | |
1671 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.por_"; | |
1672 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.rst_por_"; | |
1673 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.rst_wmr_"; | |
1674 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.rst_wmr_protect"; | |
1675 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.scan_en"; | |
1676 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.scan_in"; | |
1677 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.scan_out"; | |
1678 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.slow_cmp_sync_en"; | |
1679 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.tcu_aclk"; | |
1680 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.tcu_atpg_mode"; | |
1681 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.tcu_bclk"; | |
1682 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.tcu_clk_stop"; | |
1683 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.tcu_div_bypass"; | |
1684 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.tcu_pce_ov"; | |
1685 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.tcu_wr_inhibit"; | |
1686 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.wmr_"; | |
1687 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.wmr_protect"; | |
1688 | } | |
1689 | ||
1690 | interface clkgen_l2d0_cmp_l2clk_if { | |
1691 | input l2clk CLOCK verilog_node "`CPU.l2d0.l2d_pregrid_drv_bot.l2clk"; // Vera interface clock | |
1692 | ||
1693 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.aclk"; | |
1694 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.aclk_wmr"; | |
1695 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.array_wr_inhibit"; | |
1696 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.bclk"; | |
1697 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.cmp_slow_sync_en"; | |
1698 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.pce_ov"; | |
1699 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.por_"; | |
1700 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.scan_out"; | |
1701 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.slow_cmp_sync_en"; | |
1702 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.wmr_"; | |
1703 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.wmr_protect"; | |
1704 | } | |
1705 | ||
1706 | ||
1707 | //----- VERA interfaces for clkgen_l2d1_cmp ----- | |
1708 | //----- warning: l2d<n> do NOT use clkgen_l2d_cmp, but instantiates | |
1709 | //----- n2_clk_clstr_hdr_cust and pregrid drivers (ie. n2_clk_l2d_cmp_cust) directly | |
1710 | ||
1711 | interface clkgen_l2d1_cmp_gclk_if { | |
1712 | input gclk CLOCK verilog_node "`CPU.l2d1.l2d_clk_header.gclk"; // Vera interface clock | |
1713 | ||
1714 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.aclk"; | |
1715 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.aclk_wmr"; | |
1716 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.array_wr_inhibit"; | |
1717 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.bclk"; | |
1718 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.ccu_cmp_slow_sync_en"; | |
1719 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.ccu_div_ph"; | |
1720 | //input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.ccu_serdes_dtm"; // does NOT have this port | |
1721 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.ccu_slow_cmp_sync_en"; | |
1722 | //input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.clk_ext"; // does NOT have this port | |
1723 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.cluster_arst_l"; | |
1724 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.cluster_div_en"; | |
1725 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.cmp_slow_sync_en"; | |
1726 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_pregrid_drv_bot.l2clk"; // warning: this is real l2clk | |
1727 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.pce_ov"; | |
1728 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.por_"; | |
1729 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.rst_por_"; | |
1730 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.rst_wmr_"; | |
1731 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.rst_wmr_protect"; | |
1732 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.scan_en"; | |
1733 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.scan_in"; | |
1734 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.scan_out"; | |
1735 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.slow_cmp_sync_en"; | |
1736 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.tcu_aclk"; | |
1737 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.tcu_atpg_mode"; | |
1738 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.tcu_bclk"; | |
1739 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.tcu_clk_stop"; | |
1740 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.tcu_div_bypass"; | |
1741 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.tcu_pce_ov"; | |
1742 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.tcu_wr_inhibit"; | |
1743 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.wmr_"; | |
1744 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.wmr_protect"; | |
1745 | } | |
1746 | ||
1747 | interface clkgen_l2d1_cmp_l2clk_if { | |
1748 | input l2clk CLOCK verilog_node "`CPU.l2d1.l2d_pregrid_drv_bot.l2clk"; // Vera interface clock | |
1749 | ||
1750 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.aclk"; | |
1751 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.aclk_wmr"; | |
1752 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.array_wr_inhibit"; | |
1753 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.bclk"; | |
1754 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.cmp_slow_sync_en"; | |
1755 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.pce_ov"; | |
1756 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.por_"; | |
1757 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.scan_out"; | |
1758 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.slow_cmp_sync_en"; | |
1759 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.wmr_"; | |
1760 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.wmr_protect"; | |
1761 | } | |
1762 | ||
1763 | ||
1764 | //----- VERA interfaces for clkgen_l2d2_cmp ----- | |
1765 | //----- warning: l2d<n> do NOT use clkgen_l2d_cmp, but instantiates | |
1766 | //----- n2_clk_clstr_hdr_cust and pregrid drivers (ie. n2_clk_l2d_cmp_cust) directly | |
1767 | ||
1768 | interface clkgen_l2d2_cmp_gclk_if { | |
1769 | input gclk CLOCK verilog_node "`CPU.l2d2.l2d_clk_header.gclk"; // Vera interface clock | |
1770 | ||
1771 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.aclk"; | |
1772 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.aclk_wmr"; | |
1773 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.array_wr_inhibit"; | |
1774 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.bclk"; | |
1775 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.ccu_cmp_slow_sync_en"; | |
1776 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.ccu_div_ph"; | |
1777 | //input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.ccu_serdes_dtm"; // does NOT have this port | |
1778 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.ccu_slow_cmp_sync_en"; | |
1779 | //input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.clk_ext"; // does NOT have this port | |
1780 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.cluster_arst_l"; | |
1781 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.cluster_div_en"; | |
1782 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.cmp_slow_sync_en"; | |
1783 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_pregrid_drv_bot.l2clk"; // warning: this is real l2clk | |
1784 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.pce_ov"; | |
1785 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.por_"; | |
1786 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.rst_por_"; | |
1787 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.rst_wmr_"; | |
1788 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.rst_wmr_protect"; | |
1789 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.scan_en"; | |
1790 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.scan_in"; | |
1791 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.scan_out"; | |
1792 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.slow_cmp_sync_en"; | |
1793 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.tcu_aclk"; | |
1794 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.tcu_atpg_mode"; | |
1795 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.tcu_bclk"; | |
1796 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.tcu_clk_stop"; | |
1797 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.tcu_div_bypass"; | |
1798 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.tcu_pce_ov"; | |
1799 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.tcu_wr_inhibit"; | |
1800 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.wmr_"; | |
1801 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.wmr_protect"; | |
1802 | } | |
1803 | ||
1804 | interface clkgen_l2d2_cmp_l2clk_if { | |
1805 | input l2clk CLOCK verilog_node "`CPU.l2d2.l2d_pregrid_drv_bot.l2clk"; // Vera interface clock | |
1806 | ||
1807 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.aclk"; | |
1808 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.aclk_wmr"; | |
1809 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.array_wr_inhibit"; | |
1810 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.bclk"; | |
1811 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.cmp_slow_sync_en"; | |
1812 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.pce_ov"; | |
1813 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.por_"; | |
1814 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.scan_out"; | |
1815 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.slow_cmp_sync_en"; | |
1816 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.wmr_"; | |
1817 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.wmr_protect"; | |
1818 | } | |
1819 | ||
1820 | ||
1821 | //----- VERA interfaces for clkgen_l2d3_cmp ----- | |
1822 | //----- warning: l2d<n> do NOT use clkgen_l2d_cmp, but instantiates | |
1823 | //----- n2_clk_clstr_hdr_cust and pregrid drivers (ie. n2_clk_l2d_cmp_cust) directly | |
1824 | ||
1825 | interface clkgen_l2d3_cmp_gclk_if { | |
1826 | input gclk CLOCK verilog_node "`CPU.l2d3.l2d_clk_header.gclk"; // Vera interface clock | |
1827 | ||
1828 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.aclk"; | |
1829 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.aclk_wmr"; | |
1830 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.array_wr_inhibit"; | |
1831 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.bclk"; | |
1832 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.ccu_cmp_slow_sync_en"; | |
1833 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.ccu_div_ph"; | |
1834 | //input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.ccu_serdes_dtm"; // does NOT have this port | |
1835 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.ccu_slow_cmp_sync_en"; | |
1836 | //input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.clk_ext"; // does NOT have this port | |
1837 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.cluster_arst_l"; | |
1838 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.cluster_div_en"; | |
1839 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.cmp_slow_sync_en"; | |
1840 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_pregrid_drv_bot.l2clk"; // warning: this is real l2clk | |
1841 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.pce_ov"; | |
1842 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.por_"; | |
1843 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.rst_por_"; | |
1844 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.rst_wmr_"; | |
1845 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.rst_wmr_protect"; | |
1846 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.scan_en"; | |
1847 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.scan_in"; | |
1848 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.scan_out"; | |
1849 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.slow_cmp_sync_en"; | |
1850 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.tcu_aclk"; | |
1851 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.tcu_atpg_mode"; | |
1852 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.tcu_bclk"; | |
1853 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.tcu_clk_stop"; | |
1854 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.tcu_div_bypass"; | |
1855 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.tcu_pce_ov"; | |
1856 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.tcu_wr_inhibit"; | |
1857 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.wmr_"; | |
1858 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.wmr_protect"; | |
1859 | } | |
1860 | ||
1861 | interface clkgen_l2d3_cmp_l2clk_if { | |
1862 | input l2clk CLOCK verilog_node "`CPU.l2d3.l2d_pregrid_drv_bot.l2clk"; // Vera interface clock | |
1863 | ||
1864 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.aclk"; | |
1865 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.aclk_wmr"; | |
1866 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.array_wr_inhibit"; | |
1867 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.bclk"; | |
1868 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.cmp_slow_sync_en"; | |
1869 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.pce_ov"; | |
1870 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.por_"; | |
1871 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.scan_out"; | |
1872 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.slow_cmp_sync_en"; | |
1873 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.wmr_"; | |
1874 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.wmr_protect"; | |
1875 | } | |
1876 | ||
1877 | ||
1878 | //----- VERA interfaces for clkgen_l2d4_cmp ----- | |
1879 | //----- warning: l2d<n> do NOT use clkgen_l2d_cmp, but instantiates | |
1880 | //----- n2_clk_clstr_hdr_cust and pregrid drivers (ie. n2_clk_l2d_cmp_cust) directly | |
1881 | ||
1882 | interface clkgen_l2d4_cmp_gclk_if { | |
1883 | input gclk CLOCK verilog_node "`CPU.l2d4.l2d_clk_header.gclk"; // Vera interface clock | |
1884 | ||
1885 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.aclk"; | |
1886 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.aclk_wmr"; | |
1887 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.array_wr_inhibit"; | |
1888 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.bclk"; | |
1889 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.ccu_cmp_slow_sync_en"; | |
1890 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.ccu_div_ph"; | |
1891 | //input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.ccu_serdes_dtm"; // does NOT have this port | |
1892 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.ccu_slow_cmp_sync_en"; | |
1893 | //input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.clk_ext"; // does NOT have this port | |
1894 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.cluster_arst_l"; | |
1895 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.cluster_div_en"; | |
1896 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.cmp_slow_sync_en"; | |
1897 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_pregrid_drv_bot.l2clk"; // warning: this is real l2clk | |
1898 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.pce_ov"; | |
1899 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.por_"; | |
1900 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.rst_por_"; | |
1901 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.rst_wmr_"; | |
1902 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.rst_wmr_protect"; | |
1903 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.scan_en"; | |
1904 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.scan_in"; | |
1905 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.scan_out"; | |
1906 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.slow_cmp_sync_en"; | |
1907 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.tcu_aclk"; | |
1908 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.tcu_atpg_mode"; | |
1909 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.tcu_bclk"; | |
1910 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.tcu_clk_stop"; | |
1911 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.tcu_div_bypass"; | |
1912 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.tcu_pce_ov"; | |
1913 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.tcu_wr_inhibit"; | |
1914 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.wmr_"; | |
1915 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.wmr_protect"; | |
1916 | } | |
1917 | ||
1918 | interface clkgen_l2d4_cmp_l2clk_if { | |
1919 | input l2clk CLOCK verilog_node "`CPU.l2d4.l2d_pregrid_drv_bot.l2clk"; // Vera interface clock | |
1920 | ||
1921 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.aclk"; | |
1922 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.aclk_wmr"; | |
1923 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.array_wr_inhibit"; | |
1924 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.bclk"; | |
1925 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.cmp_slow_sync_en"; | |
1926 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.pce_ov"; | |
1927 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.por_"; | |
1928 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.scan_out"; | |
1929 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.slow_cmp_sync_en"; | |
1930 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.wmr_"; | |
1931 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.wmr_protect"; | |
1932 | } | |
1933 | ||
1934 | ||
1935 | //----- VERA interfaces for clkgen_l2d5_cmp ----- | |
1936 | //----- warning: l2d<n> do NOT use clkgen_l2d_cmp, but instantiates | |
1937 | //----- n2_clk_clstr_hdr_cust and pregrid drivers (ie. n2_clk_l2d_cmp_cust) directly | |
1938 | ||
1939 | interface clkgen_l2d5_cmp_gclk_if { | |
1940 | input gclk CLOCK verilog_node "`CPU.l2d5.l2d_clk_header.gclk"; // Vera interface clock | |
1941 | ||
1942 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.aclk"; | |
1943 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.aclk_wmr"; | |
1944 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.array_wr_inhibit"; | |
1945 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.bclk"; | |
1946 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.ccu_cmp_slow_sync_en"; | |
1947 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.ccu_div_ph"; | |
1948 | //input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.ccu_serdes_dtm"; // does NOT have this port | |
1949 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.ccu_slow_cmp_sync_en"; | |
1950 | //input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.clk_ext"; // does NOT have this port | |
1951 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.cluster_arst_l"; | |
1952 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.cluster_div_en"; | |
1953 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.cmp_slow_sync_en"; | |
1954 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_pregrid_drv_bot.l2clk"; // warning: this is real l2clk | |
1955 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.pce_ov"; | |
1956 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.por_"; | |
1957 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.rst_por_"; | |
1958 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.rst_wmr_"; | |
1959 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.rst_wmr_protect"; | |
1960 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.scan_en"; | |
1961 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.scan_in"; | |
1962 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.scan_out"; | |
1963 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.slow_cmp_sync_en"; | |
1964 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.tcu_aclk"; | |
1965 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.tcu_atpg_mode"; | |
1966 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.tcu_bclk"; | |
1967 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.tcu_clk_stop"; | |
1968 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.tcu_div_bypass"; | |
1969 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.tcu_pce_ov"; | |
1970 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.tcu_wr_inhibit"; | |
1971 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.wmr_"; | |
1972 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.wmr_protect"; | |
1973 | } | |
1974 | ||
1975 | interface clkgen_l2d5_cmp_l2clk_if { | |
1976 | input l2clk CLOCK verilog_node "`CPU.l2d5.l2d_pregrid_drv_bot.l2clk"; // Vera interface clock | |
1977 | ||
1978 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.aclk"; | |
1979 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.aclk_wmr"; | |
1980 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.array_wr_inhibit"; | |
1981 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.bclk"; | |
1982 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.cmp_slow_sync_en"; | |
1983 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.pce_ov"; | |
1984 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.por_"; | |
1985 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.scan_out"; | |
1986 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.slow_cmp_sync_en"; | |
1987 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.wmr_"; | |
1988 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.wmr_protect"; | |
1989 | } | |
1990 | ||
1991 | ||
1992 | //----- VERA interfaces for clkgen_l2d6_cmp ----- | |
1993 | //----- warning: l2d<n> do NOT use clkgen_l2d_cmp, but instantiates | |
1994 | //----- n2_clk_clstr_hdr_cust and pregrid drivers (ie. n2_clk_l2d_cmp_cust) directly | |
1995 | ||
1996 | interface clkgen_l2d6_cmp_gclk_if { | |
1997 | input gclk CLOCK verilog_node "`CPU.l2d6.l2d_clk_header.gclk"; // Vera interface clock | |
1998 | ||
1999 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.aclk"; | |
2000 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.aclk_wmr"; | |
2001 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.array_wr_inhibit"; | |
2002 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.bclk"; | |
2003 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.ccu_cmp_slow_sync_en"; | |
2004 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.ccu_div_ph"; | |
2005 | //input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.ccu_serdes_dtm"; // does NOT have this port | |
2006 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.ccu_slow_cmp_sync_en"; | |
2007 | //input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.clk_ext"; // does NOT have this port | |
2008 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.cluster_arst_l"; | |
2009 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.cluster_div_en"; | |
2010 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.cmp_slow_sync_en"; | |
2011 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_pregrid_drv_bot.l2clk"; // warning: this is real l2clk | |
2012 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.pce_ov"; | |
2013 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.por_"; | |
2014 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.rst_por_"; | |
2015 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.rst_wmr_"; | |
2016 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.rst_wmr_protect"; | |
2017 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.scan_en"; | |
2018 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.scan_in"; | |
2019 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.scan_out"; | |
2020 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.slow_cmp_sync_en"; | |
2021 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.tcu_aclk"; | |
2022 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.tcu_atpg_mode"; | |
2023 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.tcu_bclk"; | |
2024 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.tcu_clk_stop"; | |
2025 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.tcu_div_bypass"; | |
2026 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.tcu_pce_ov"; | |
2027 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.tcu_wr_inhibit"; | |
2028 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.wmr_"; | |
2029 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.wmr_protect"; | |
2030 | } | |
2031 | ||
2032 | interface clkgen_l2d6_cmp_l2clk_if { | |
2033 | input l2clk CLOCK verilog_node "`CPU.l2d6.l2d_pregrid_drv_bot.l2clk"; // Vera interface clock | |
2034 | ||
2035 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.aclk"; | |
2036 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.aclk_wmr"; | |
2037 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.array_wr_inhibit"; | |
2038 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.bclk"; | |
2039 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.cmp_slow_sync_en"; | |
2040 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.pce_ov"; | |
2041 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.por_"; | |
2042 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.scan_out"; | |
2043 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.slow_cmp_sync_en"; | |
2044 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.wmr_"; | |
2045 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.wmr_protect"; | |
2046 | } | |
2047 | ||
2048 | ||
2049 | //----- VERA interfaces for clkgen_l2d7_cmp ----- | |
2050 | //----- warning: l2d<n> do NOT use clkgen_l2d_cmp, but instantiates | |
2051 | //----- n2_clk_clstr_hdr_cust and pregrid drivers (ie. n2_clk_l2d_cmp_cust) directly | |
2052 | ||
2053 | interface clkgen_l2d7_cmp_gclk_if { | |
2054 | input gclk CLOCK verilog_node "`CPU.l2d7.l2d_clk_header.gclk"; // Vera interface clock | |
2055 | ||
2056 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.aclk"; | |
2057 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.aclk_wmr"; | |
2058 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.array_wr_inhibit"; | |
2059 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.bclk"; | |
2060 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.ccu_cmp_slow_sync_en"; | |
2061 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.ccu_div_ph"; | |
2062 | //input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.ccu_serdes_dtm"; // does NOT have this port | |
2063 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.ccu_slow_cmp_sync_en"; | |
2064 | //input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.clk_ext"; // does NOT have this port | |
2065 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.cluster_arst_l"; | |
2066 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.cluster_div_en"; | |
2067 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.cmp_slow_sync_en"; | |
2068 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_pregrid_drv_bot.l2clk"; // warning: this is real l2clk | |
2069 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.pce_ov"; | |
2070 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.por_"; | |
2071 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.rst_por_"; | |
2072 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.rst_wmr_"; | |
2073 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.rst_wmr_protect"; | |
2074 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.scan_en"; | |
2075 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.scan_in"; | |
2076 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.scan_out"; | |
2077 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.slow_cmp_sync_en"; | |
2078 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.tcu_aclk"; | |
2079 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.tcu_atpg_mode"; | |
2080 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.tcu_bclk"; | |
2081 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.tcu_clk_stop"; | |
2082 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.tcu_div_bypass"; | |
2083 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.tcu_pce_ov"; | |
2084 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.tcu_wr_inhibit"; | |
2085 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.wmr_"; | |
2086 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.wmr_protect"; | |
2087 | } | |
2088 | ||
2089 | interface clkgen_l2d7_cmp_l2clk_if { | |
2090 | input l2clk CLOCK verilog_node "`CPU.l2d7.l2d_pregrid_drv_bot.l2clk"; // Vera interface clock | |
2091 | ||
2092 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.aclk"; | |
2093 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.aclk_wmr"; | |
2094 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.array_wr_inhibit"; | |
2095 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.bclk"; | |
2096 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.cmp_slow_sync_en"; | |
2097 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.pce_ov"; | |
2098 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.por_"; | |
2099 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.scan_out"; | |
2100 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.slow_cmp_sync_en"; | |
2101 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.wmr_"; | |
2102 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.wmr_protect"; | |
2103 | } | |
2104 | ||
2105 | //----- VERA interfaces for clkgen_l2t0_cmp ----- | |
2106 | ||
2107 | interface clkgen_l2t0_cmp_gclk_if { | |
2108 | input gclk CLOCK verilog_node "`CPU.l2t0.l2t_clk_header.gclk"; // Vera interface clock | |
2109 | ||
2110 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.aclk"; | |
2111 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.aclk_wmr"; | |
2112 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.array_wr_inhibit"; | |
2113 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.bclk"; | |
2114 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.ccu_cmp_slow_sync_en"; | |
2115 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.ccu_div_ph"; | |
2116 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.ccu_serdes_dtm"; | |
2117 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.ccu_slow_cmp_sync_en"; | |
2118 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.clk_ext"; | |
2119 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.cluster_arst_l"; | |
2120 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.cluster_div_en"; | |
2121 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.cmp_slow_sync_en"; | |
2122 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.l2clk"; | |
2123 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.pce_ov"; | |
2124 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.por_"; | |
2125 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.rst_por_"; | |
2126 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.rst_wmr_"; | |
2127 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.rst_wmr_protect"; | |
2128 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.scan_en"; | |
2129 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.scan_in"; | |
2130 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.scan_out"; | |
2131 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.slow_cmp_sync_en"; | |
2132 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.tcu_aclk"; | |
2133 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.tcu_atpg_mode"; | |
2134 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.tcu_bclk"; | |
2135 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.tcu_clk_stop"; | |
2136 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.tcu_div_bypass"; | |
2137 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.tcu_pce_ov"; | |
2138 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.tcu_wr_inhibit"; | |
2139 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.wmr_"; | |
2140 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.wmr_protect"; | |
2141 | } | |
2142 | ||
2143 | interface clkgen_l2t0_cmp_l2clk_if { | |
2144 | input l2clk CLOCK verilog_node "`CPU.l2t0.l2t_clk_header.l2clk"; // Vera interface clock | |
2145 | ||
2146 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.aclk"; | |
2147 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.aclk_wmr"; | |
2148 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.array_wr_inhibit"; | |
2149 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.bclk"; | |
2150 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.cmp_slow_sync_en"; | |
2151 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.pce_ov"; | |
2152 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.por_"; | |
2153 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.scan_out"; | |
2154 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.slow_cmp_sync_en"; | |
2155 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.wmr_"; | |
2156 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.wmr_protect"; | |
2157 | } | |
2158 | ||
2159 | //----- VERA interfaces for clkgen_l2t1_cmp ----- | |
2160 | ||
2161 | interface clkgen_l2t1_cmp_gclk_if { | |
2162 | input gclk CLOCK verilog_node "`CPU.l2t1.l2t_clk_header.gclk"; // Vera interface clock | |
2163 | ||
2164 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.aclk"; | |
2165 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.aclk_wmr"; | |
2166 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.array_wr_inhibit"; | |
2167 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.bclk"; | |
2168 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.ccu_cmp_slow_sync_en"; | |
2169 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.ccu_div_ph"; | |
2170 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.ccu_serdes_dtm"; | |
2171 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.ccu_slow_cmp_sync_en"; | |
2172 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.clk_ext"; | |
2173 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.cluster_arst_l"; | |
2174 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.cluster_div_en"; | |
2175 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.cmp_slow_sync_en"; | |
2176 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.l2clk"; | |
2177 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.pce_ov"; | |
2178 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.por_"; | |
2179 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.rst_por_"; | |
2180 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.rst_wmr_"; | |
2181 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.rst_wmr_protect"; | |
2182 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.scan_en"; | |
2183 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.scan_in"; | |
2184 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.scan_out"; | |
2185 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.slow_cmp_sync_en"; | |
2186 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.tcu_aclk"; | |
2187 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.tcu_atpg_mode"; | |
2188 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.tcu_bclk"; | |
2189 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.tcu_clk_stop"; | |
2190 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.tcu_div_bypass"; | |
2191 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.tcu_pce_ov"; | |
2192 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.tcu_wr_inhibit"; | |
2193 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.wmr_"; | |
2194 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.wmr_protect"; | |
2195 | } | |
2196 | ||
2197 | interface clkgen_l2t1_cmp_l2clk_if { | |
2198 | input l2clk CLOCK verilog_node "`CPU.l2t1.l2t_clk_header.l2clk"; // Vera interface clock | |
2199 | ||
2200 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.aclk"; | |
2201 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.aclk_wmr"; | |
2202 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.array_wr_inhibit"; | |
2203 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.bclk"; | |
2204 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.cmp_slow_sync_en"; | |
2205 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.pce_ov"; | |
2206 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.por_"; | |
2207 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.scan_out"; | |
2208 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.slow_cmp_sync_en"; | |
2209 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.wmr_"; | |
2210 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.wmr_protect"; | |
2211 | } | |
2212 | ||
2213 | //----- VERA interfaces for clkgen_l2t2_cmp ----- | |
2214 | ||
2215 | interface clkgen_l2t2_cmp_gclk_if { | |
2216 | input gclk CLOCK verilog_node "`CPU.l2t2.l2t_clk_header.gclk"; // Vera interface clock | |
2217 | ||
2218 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.aclk"; | |
2219 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.aclk_wmr"; | |
2220 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.array_wr_inhibit"; | |
2221 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.bclk"; | |
2222 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.ccu_cmp_slow_sync_en"; | |
2223 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.ccu_div_ph"; | |
2224 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.ccu_serdes_dtm"; | |
2225 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.ccu_slow_cmp_sync_en"; | |
2226 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.clk_ext"; | |
2227 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.cluster_arst_l"; | |
2228 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.cluster_div_en"; | |
2229 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.cmp_slow_sync_en"; | |
2230 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.l2clk"; | |
2231 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.pce_ov"; | |
2232 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.por_"; | |
2233 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.rst_por_"; | |
2234 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.rst_wmr_"; | |
2235 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.rst_wmr_protect"; | |
2236 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.scan_en"; | |
2237 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.scan_in"; | |
2238 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.scan_out"; | |
2239 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.slow_cmp_sync_en"; | |
2240 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.tcu_aclk"; | |
2241 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.tcu_atpg_mode"; | |
2242 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.tcu_bclk"; | |
2243 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.tcu_clk_stop"; | |
2244 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.tcu_div_bypass"; | |
2245 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.tcu_pce_ov"; | |
2246 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.tcu_wr_inhibit"; | |
2247 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.wmr_"; | |
2248 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.wmr_protect"; | |
2249 | } | |
2250 | ||
2251 | interface clkgen_l2t2_cmp_l2clk_if { | |
2252 | input l2clk CLOCK verilog_node "`CPU.l2t2.l2t_clk_header.l2clk"; // Vera interface clock | |
2253 | ||
2254 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.aclk"; | |
2255 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.aclk_wmr"; | |
2256 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.array_wr_inhibit"; | |
2257 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.bclk"; | |
2258 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.cmp_slow_sync_en"; | |
2259 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.pce_ov"; | |
2260 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.por_"; | |
2261 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.scan_out"; | |
2262 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.slow_cmp_sync_en"; | |
2263 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.wmr_"; | |
2264 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.wmr_protect"; | |
2265 | } | |
2266 | ||
2267 | //----- VERA interfaces for clkgen_l2t3_cmp ----- | |
2268 | ||
2269 | interface clkgen_l2t3_cmp_gclk_if { | |
2270 | input gclk CLOCK verilog_node "`CPU.l2t3.l2t_clk_header.gclk"; // Vera interface clock | |
2271 | ||
2272 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.aclk"; | |
2273 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.aclk_wmr"; | |
2274 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.array_wr_inhibit"; | |
2275 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.bclk"; | |
2276 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.ccu_cmp_slow_sync_en"; | |
2277 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.ccu_div_ph"; | |
2278 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.ccu_serdes_dtm"; | |
2279 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.ccu_slow_cmp_sync_en"; | |
2280 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.clk_ext"; | |
2281 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.cluster_arst_l"; | |
2282 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.cluster_div_en"; | |
2283 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.cmp_slow_sync_en"; | |
2284 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.l2clk"; | |
2285 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.pce_ov"; | |
2286 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.por_"; | |
2287 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.rst_por_"; | |
2288 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.rst_wmr_"; | |
2289 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.rst_wmr_protect"; | |
2290 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.scan_en"; | |
2291 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.scan_in"; | |
2292 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.scan_out"; | |
2293 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.slow_cmp_sync_en"; | |
2294 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.tcu_aclk"; | |
2295 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.tcu_atpg_mode"; | |
2296 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.tcu_bclk"; | |
2297 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.tcu_clk_stop"; | |
2298 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.tcu_div_bypass"; | |
2299 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.tcu_pce_ov"; | |
2300 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.tcu_wr_inhibit"; | |
2301 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.wmr_"; | |
2302 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.wmr_protect"; | |
2303 | } | |
2304 | ||
2305 | interface clkgen_l2t3_cmp_l2clk_if { | |
2306 | input l2clk CLOCK verilog_node "`CPU.l2t3.l2t_clk_header.l2clk"; // Vera interface clock | |
2307 | ||
2308 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.aclk"; | |
2309 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.aclk_wmr"; | |
2310 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.array_wr_inhibit"; | |
2311 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.bclk"; | |
2312 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.cmp_slow_sync_en"; | |
2313 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.pce_ov"; | |
2314 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.por_"; | |
2315 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.scan_out"; | |
2316 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.slow_cmp_sync_en"; | |
2317 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.wmr_"; | |
2318 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.wmr_protect"; | |
2319 | } | |
2320 | ||
2321 | //----- VERA interfaces for clkgen_l2t4_cmp ----- | |
2322 | ||
2323 | interface clkgen_l2t4_cmp_gclk_if { | |
2324 | input gclk CLOCK verilog_node "`CPU.l2t4.l2t_clk_header.gclk"; // Vera interface clock | |
2325 | ||
2326 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.aclk"; | |
2327 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.aclk_wmr"; | |
2328 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.array_wr_inhibit"; | |
2329 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.bclk"; | |
2330 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.ccu_cmp_slow_sync_en"; | |
2331 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.ccu_div_ph"; | |
2332 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.ccu_serdes_dtm"; | |
2333 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.ccu_slow_cmp_sync_en"; | |
2334 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.clk_ext"; | |
2335 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.cluster_arst_l"; | |
2336 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.cluster_div_en"; | |
2337 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.cmp_slow_sync_en"; | |
2338 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.l2clk"; | |
2339 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.pce_ov"; | |
2340 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.por_"; | |
2341 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.rst_por_"; | |
2342 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.rst_wmr_"; | |
2343 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.rst_wmr_protect"; | |
2344 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.scan_en"; | |
2345 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.scan_in"; | |
2346 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.scan_out"; | |
2347 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.slow_cmp_sync_en"; | |
2348 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.tcu_aclk"; | |
2349 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.tcu_atpg_mode"; | |
2350 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.tcu_bclk"; | |
2351 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.tcu_clk_stop"; | |
2352 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.tcu_div_bypass"; | |
2353 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.tcu_pce_ov"; | |
2354 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.tcu_wr_inhibit"; | |
2355 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.wmr_"; | |
2356 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.wmr_protect"; | |
2357 | } | |
2358 | ||
2359 | interface clkgen_l2t4_cmp_l2clk_if { | |
2360 | input l2clk CLOCK verilog_node "`CPU.l2t4.l2t_clk_header.l2clk"; // Vera interface clock | |
2361 | ||
2362 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.aclk"; | |
2363 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.aclk_wmr"; | |
2364 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.array_wr_inhibit"; | |
2365 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.bclk"; | |
2366 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.cmp_slow_sync_en"; | |
2367 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.pce_ov"; | |
2368 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.por_"; | |
2369 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.scan_out"; | |
2370 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.slow_cmp_sync_en"; | |
2371 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.wmr_"; | |
2372 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.wmr_protect"; | |
2373 | } | |
2374 | ||
2375 | //----- VERA interfaces for clkgen_l2t5_cmp ----- | |
2376 | ||
2377 | interface clkgen_l2t5_cmp_gclk_if { | |
2378 | input gclk CLOCK verilog_node "`CPU.l2t5.l2t_clk_header.gclk"; // Vera interface clock | |
2379 | ||
2380 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.aclk"; | |
2381 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.aclk_wmr"; | |
2382 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.array_wr_inhibit"; | |
2383 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.bclk"; | |
2384 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.ccu_cmp_slow_sync_en"; | |
2385 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.ccu_div_ph"; | |
2386 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.ccu_serdes_dtm"; | |
2387 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.ccu_slow_cmp_sync_en"; | |
2388 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.clk_ext"; | |
2389 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.cluster_arst_l"; | |
2390 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.cluster_div_en"; | |
2391 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.cmp_slow_sync_en"; | |
2392 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.l2clk"; | |
2393 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.pce_ov"; | |
2394 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.por_"; | |
2395 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.rst_por_"; | |
2396 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.rst_wmr_"; | |
2397 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.rst_wmr_protect"; | |
2398 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.scan_en"; | |
2399 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.scan_in"; | |
2400 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.scan_out"; | |
2401 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.slow_cmp_sync_en"; | |
2402 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.tcu_aclk"; | |
2403 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.tcu_atpg_mode"; | |
2404 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.tcu_bclk"; | |
2405 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.tcu_clk_stop"; | |
2406 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.tcu_div_bypass"; | |
2407 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.tcu_pce_ov"; | |
2408 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.tcu_wr_inhibit"; | |
2409 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.wmr_"; | |
2410 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.wmr_protect"; | |
2411 | } | |
2412 | ||
2413 | interface clkgen_l2t5_cmp_l2clk_if { | |
2414 | input l2clk CLOCK verilog_node "`CPU.l2t5.l2t_clk_header.l2clk"; // Vera interface clock | |
2415 | ||
2416 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.aclk"; | |
2417 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.aclk_wmr"; | |
2418 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.array_wr_inhibit"; | |
2419 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.bclk"; | |
2420 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.cmp_slow_sync_en"; | |
2421 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.pce_ov"; | |
2422 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.por_"; | |
2423 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.scan_out"; | |
2424 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.slow_cmp_sync_en"; | |
2425 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.wmr_"; | |
2426 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.wmr_protect"; | |
2427 | } | |
2428 | ||
2429 | //----- VERA interfaces for clkgen_l2t6_cmp ----- | |
2430 | ||
2431 | interface clkgen_l2t6_cmp_gclk_if { | |
2432 | input gclk CLOCK verilog_node "`CPU.l2t6.l2t_clk_header.gclk"; // Vera interface clock | |
2433 | ||
2434 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.aclk"; | |
2435 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.aclk_wmr"; | |
2436 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.array_wr_inhibit"; | |
2437 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.bclk"; | |
2438 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.ccu_cmp_slow_sync_en"; | |
2439 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.ccu_div_ph"; | |
2440 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.ccu_serdes_dtm"; | |
2441 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.ccu_slow_cmp_sync_en"; | |
2442 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.clk_ext"; | |
2443 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.cluster_arst_l"; | |
2444 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.cluster_div_en"; | |
2445 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.cmp_slow_sync_en"; | |
2446 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.l2clk"; | |
2447 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.pce_ov"; | |
2448 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.por_"; | |
2449 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.rst_por_"; | |
2450 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.rst_wmr_"; | |
2451 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.rst_wmr_protect"; | |
2452 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.scan_en"; | |
2453 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.scan_in"; | |
2454 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.scan_out"; | |
2455 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.slow_cmp_sync_en"; | |
2456 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.tcu_aclk"; | |
2457 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.tcu_atpg_mode"; | |
2458 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.tcu_bclk"; | |
2459 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.tcu_clk_stop"; | |
2460 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.tcu_div_bypass"; | |
2461 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.tcu_pce_ov"; | |
2462 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.tcu_wr_inhibit"; | |
2463 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.wmr_"; | |
2464 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.wmr_protect"; | |
2465 | } | |
2466 | ||
2467 | interface clkgen_l2t6_cmp_l2clk_if { | |
2468 | input l2clk CLOCK verilog_node "`CPU.l2t6.l2t_clk_header.l2clk"; // Vera interface clock | |
2469 | ||
2470 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.aclk"; | |
2471 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.aclk_wmr"; | |
2472 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.array_wr_inhibit"; | |
2473 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.bclk"; | |
2474 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.cmp_slow_sync_en"; | |
2475 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.pce_ov"; | |
2476 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.por_"; | |
2477 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.scan_out"; | |
2478 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.slow_cmp_sync_en"; | |
2479 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.wmr_"; | |
2480 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.wmr_protect"; | |
2481 | } | |
2482 | ||
2483 | //----- VERA interfaces for clkgen_l2t7_cmp ----- | |
2484 | ||
2485 | interface clkgen_l2t7_cmp_gclk_if { | |
2486 | input gclk CLOCK verilog_node "`CPU.l2t7.l2t_clk_header.gclk"; // Vera interface clock | |
2487 | ||
2488 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.aclk"; | |
2489 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.aclk_wmr"; | |
2490 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.array_wr_inhibit"; | |
2491 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.bclk"; | |
2492 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.ccu_cmp_slow_sync_en"; | |
2493 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.ccu_div_ph"; | |
2494 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.ccu_serdes_dtm"; | |
2495 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.ccu_slow_cmp_sync_en"; | |
2496 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.clk_ext"; | |
2497 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.cluster_arst_l"; | |
2498 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.cluster_div_en"; | |
2499 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.cmp_slow_sync_en"; | |
2500 | input l2clk PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.l2clk"; | |
2501 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.pce_ov"; | |
2502 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.por_"; | |
2503 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.rst_por_"; | |
2504 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.rst_wmr_"; | |
2505 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.rst_wmr_protect"; | |
2506 | input scan_en PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.scan_en"; | |
2507 | input scan_in PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.scan_in"; | |
2508 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.scan_out"; | |
2509 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.slow_cmp_sync_en"; | |
2510 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.tcu_aclk"; | |
2511 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.tcu_atpg_mode"; | |
2512 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.tcu_bclk"; | |
2513 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.tcu_clk_stop"; | |
2514 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.tcu_div_bypass"; | |
2515 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.tcu_pce_ov"; | |
2516 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.tcu_wr_inhibit"; | |
2517 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.wmr_"; | |
2518 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.wmr_protect"; | |
2519 | } | |
2520 | ||
2521 | interface clkgen_l2t7_cmp_l2clk_if { | |
2522 | input l2clk CLOCK verilog_node "`CPU.l2t7.l2t_clk_header.l2clk"; // Vera interface clock | |
2523 | ||
2524 | input aclk PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.aclk"; | |
2525 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.aclk_wmr"; | |
2526 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.array_wr_inhibit"; | |
2527 | input bclk PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.bclk"; | |
2528 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.cmp_slow_sync_en"; | |
2529 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.pce_ov"; | |
2530 | input por_ PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.por_"; | |
2531 | input scan_out PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.scan_out"; | |
2532 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.slow_cmp_sync_en"; | |
2533 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.wmr_"; | |
2534 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.wmr_protect"; | |
2535 | } | |
2536 | ||
2537 | #ifndef FC_NO_NIU_T2 | |
2538 | #ifndef NIU_SYSTEMC_T2 | |
2539 | //----- VERA interfaces for clkgen_mac_io ----- | |
2540 | ||
2541 | interface clkgen_mac_io_gclk_if { | |
2542 | input gclk CLOCK verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.gclk"; // Vera interface clock | |
2543 | ||
2544 | input aclk PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.aclk"; | |
2545 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.aclk_wmr"; | |
2546 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.array_wr_inhibit"; | |
2547 | input bclk PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.bclk"; | |
2548 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.ccu_cmp_slow_sync_en"; | |
2549 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.ccu_div_ph"; | |
2550 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.ccu_serdes_dtm"; | |
2551 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.ccu_slow_cmp_sync_en"; | |
2552 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.clk_ext"; | |
2553 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.cluster_arst_l"; | |
2554 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.cluster_div_en"; | |
2555 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.cmp_slow_sync_en"; | |
2556 | input l2clk PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.l2clk"; | |
2557 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.pce_ov"; | |
2558 | input por_ PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.por_"; | |
2559 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.rst_por_"; | |
2560 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.rst_wmr_"; | |
2561 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.rst_wmr_protect"; | |
2562 | input scan_en PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.scan_en"; | |
2563 | input scan_in PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.scan_in"; | |
2564 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.scan_out"; | |
2565 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.slow_cmp_sync_en"; | |
2566 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.tcu_aclk"; | |
2567 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.tcu_atpg_mode"; | |
2568 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.tcu_bclk"; | |
2569 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.tcu_clk_stop"; | |
2570 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.tcu_div_bypass"; | |
2571 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.tcu_pce_ov"; | |
2572 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.tcu_wr_inhibit"; | |
2573 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.wmr_"; | |
2574 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.wmr_protect"; | |
2575 | } | |
2576 | ||
2577 | interface clkgen_mac_io_l2clk_if { | |
2578 | input l2clk CLOCK verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.l2clk"; // Vera interface clock | |
2579 | ||
2580 | input aclk PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.aclk"; | |
2581 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.aclk_wmr"; | |
2582 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.array_wr_inhibit"; | |
2583 | input bclk PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.bclk"; | |
2584 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.cmp_slow_sync_en"; | |
2585 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.pce_ov"; | |
2586 | input por_ PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.por_"; | |
2587 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.scan_out"; | |
2588 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.slow_cmp_sync_en"; | |
2589 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.wmr_"; | |
2590 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.wmr_protect"; | |
2591 | } | |
2592 | #endif | |
2593 | #endif | |
2594 | ||
2595 | //----- VERA interfaces for clkgen_mcu0_cmp ----- | |
2596 | ||
2597 | interface clkgen_mcu0_cmp_gclk_if { | |
2598 | input gclk CLOCK verilog_node "`CPU.mcu0.clkgen_cmp.gclk"; // Vera interface clock | |
2599 | ||
2600 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.aclk"; | |
2601 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.aclk_wmr"; | |
2602 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.array_wr_inhibit"; | |
2603 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.bclk"; | |
2604 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.ccu_cmp_slow_sync_en"; | |
2605 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.ccu_div_ph"; | |
2606 | input ccu_dr_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.ccu_dr_sync_en"; | |
2607 | input ccu_io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.ccu_io2x_sync_en"; | |
2608 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.ccu_serdes_dtm"; | |
2609 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.ccu_slow_cmp_sync_en"; | |
2610 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.clk_ext"; | |
2611 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.cluster_arst_l"; | |
2612 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.cluster_div_en"; | |
2613 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.cmp_slow_sync_en"; | |
2614 | input dr_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.dr_sync_en"; | |
2615 | input io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.io2x_sync_en"; | |
2616 | input l2clk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.l2clk"; | |
2617 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.pce_ov"; | |
2618 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.por_"; | |
2619 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.rst_por_"; | |
2620 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.rst_wmr_"; | |
2621 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.rst_wmr_protect"; | |
2622 | input scan_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.scan_en"; | |
2623 | input scan_in PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.scan_in"; | |
2624 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.scan_out"; | |
2625 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.slow_cmp_sync_en"; | |
2626 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.tcu_aclk"; | |
2627 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.tcu_atpg_mode"; | |
2628 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.tcu_bclk"; | |
2629 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.tcu_clk_stop"; | |
2630 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.tcu_div_bypass"; | |
2631 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.tcu_pce_ov"; | |
2632 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.tcu_wr_inhibit"; | |
2633 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.wmr_"; | |
2634 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.wmr_protect"; | |
2635 | } | |
2636 | ||
2637 | interface clkgen_mcu0_cmp_l2clk_if { | |
2638 | input l2clk CLOCK verilog_node "`CPU.mcu0.clkgen_cmp.l2clk"; // Vera interface clock | |
2639 | ||
2640 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.aclk"; | |
2641 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.aclk_wmr"; | |
2642 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.array_wr_inhibit"; | |
2643 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.bclk"; | |
2644 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.cmp_slow_sync_en"; | |
2645 | input dr_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.dr_sync_en"; | |
2646 | input io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.io2x_sync_en"; | |
2647 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.pce_ov"; | |
2648 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.por_"; | |
2649 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.scan_out"; | |
2650 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.slow_cmp_sync_en"; | |
2651 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.wmr_"; | |
2652 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.wmr_protect"; | |
2653 | } | |
2654 | ||
2655 | //----- VERA interfaces for clkgen_mcu0_dr ----- | |
2656 | ||
2657 | interface clkgen_mcu0_dr_gclk_if { | |
2658 | input gclk CLOCK verilog_node "`CPU.mcu0.clkgen_dr.gclk"; // Vera interface clock | |
2659 | ||
2660 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.aclk"; | |
2661 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.aclk_wmr"; | |
2662 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.array_wr_inhibit"; | |
2663 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.bclk"; | |
2664 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.ccu_cmp_slow_sync_en"; | |
2665 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.ccu_div_ph"; | |
2666 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.ccu_serdes_dtm"; | |
2667 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.ccu_slow_cmp_sync_en"; | |
2668 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.clk_ext"; | |
2669 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.cluster_arst_l"; | |
2670 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.cluster_div_en"; | |
2671 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.cmp_slow_sync_en"; | |
2672 | input l2clk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.l2clk"; | |
2673 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.pce_ov"; | |
2674 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.por_"; | |
2675 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.rst_por_"; | |
2676 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.rst_wmr_"; | |
2677 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.rst_wmr_protect"; | |
2678 | input scan_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.scan_en"; | |
2679 | input scan_in PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.scan_in"; | |
2680 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.scan_out"; | |
2681 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.slow_cmp_sync_en"; | |
2682 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.tcu_aclk"; | |
2683 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.tcu_atpg_mode"; | |
2684 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.tcu_bclk"; | |
2685 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.tcu_clk_stop"; | |
2686 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.tcu_div_bypass"; | |
2687 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.tcu_pce_ov"; | |
2688 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.tcu_wr_inhibit"; | |
2689 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.wmr_"; | |
2690 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.wmr_protect"; | |
2691 | } | |
2692 | ||
2693 | interface clkgen_mcu0_dr_l2clk_if { | |
2694 | input l2clk CLOCK verilog_node "`CPU.mcu0.clkgen_dr.l2clk"; // Vera interface clock | |
2695 | ||
2696 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.aclk"; | |
2697 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.aclk_wmr"; | |
2698 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.array_wr_inhibit"; | |
2699 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.bclk"; | |
2700 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.cmp_slow_sync_en"; | |
2701 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.pce_ov"; | |
2702 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.por_"; | |
2703 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.scan_out"; | |
2704 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.slow_cmp_sync_en"; | |
2705 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.wmr_"; | |
2706 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.wmr_protect"; | |
2707 | } | |
2708 | ||
2709 | //----- VERA interfaces for clkgen_mcu0_io ----- | |
2710 | ||
2711 | interface clkgen_mcu0_io_gclk_if { | |
2712 | input gclk CLOCK verilog_node "`CPU.mcu0.clkgen_io.gclk"; // Vera interface clock | |
2713 | ||
2714 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.aclk"; | |
2715 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.aclk_wmr"; | |
2716 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.array_wr_inhibit"; | |
2717 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.bclk"; | |
2718 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.ccu_cmp_slow_sync_en"; | |
2719 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.ccu_div_ph"; | |
2720 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.ccu_serdes_dtm"; | |
2721 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.ccu_slow_cmp_sync_en"; | |
2722 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.clk_ext"; | |
2723 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.cluster_arst_l"; | |
2724 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.cluster_div_en"; | |
2725 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.cmp_slow_sync_en"; | |
2726 | input l2clk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.l2clk"; | |
2727 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.pce_ov"; | |
2728 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.por_"; | |
2729 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.rst_por_"; | |
2730 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.rst_wmr_"; | |
2731 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.rst_wmr_protect"; | |
2732 | input scan_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.scan_en"; | |
2733 | input scan_in PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.scan_in"; | |
2734 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.scan_out"; | |
2735 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.slow_cmp_sync_en"; | |
2736 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.tcu_aclk"; | |
2737 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.tcu_atpg_mode"; | |
2738 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.tcu_bclk"; | |
2739 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.tcu_clk_stop"; | |
2740 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.tcu_div_bypass"; | |
2741 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.tcu_pce_ov"; | |
2742 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.tcu_wr_inhibit"; | |
2743 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.wmr_"; | |
2744 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.wmr_protect"; | |
2745 | } | |
2746 | ||
2747 | interface clkgen_mcu0_io_l2clk_if { | |
2748 | input l2clk CLOCK verilog_node "`CPU.mcu0.clkgen_io.l2clk"; // Vera interface clock | |
2749 | ||
2750 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.aclk"; | |
2751 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.aclk_wmr"; | |
2752 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.array_wr_inhibit"; | |
2753 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.bclk"; | |
2754 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.cmp_slow_sync_en"; | |
2755 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.pce_ov"; | |
2756 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.por_"; | |
2757 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.scan_out"; | |
2758 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.slow_cmp_sync_en"; | |
2759 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.wmr_"; | |
2760 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.wmr_protect"; | |
2761 | } | |
2762 | ||
2763 | //----- VERA interfaces for clkgen_mcu1_cmp ----- | |
2764 | ||
2765 | interface clkgen_mcu1_cmp_gclk_if { | |
2766 | input gclk CLOCK verilog_node "`CPU.mcu1.clkgen_cmp.gclk"; // Vera interface clock | |
2767 | ||
2768 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.aclk"; | |
2769 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.aclk_wmr"; | |
2770 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.array_wr_inhibit"; | |
2771 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.bclk"; | |
2772 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.ccu_cmp_slow_sync_en"; | |
2773 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.ccu_div_ph"; | |
2774 | input ccu_dr_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.ccu_dr_sync_en"; | |
2775 | input ccu_io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.ccu_io2x_sync_en"; | |
2776 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.ccu_serdes_dtm"; | |
2777 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.ccu_slow_cmp_sync_en"; | |
2778 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.clk_ext"; | |
2779 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.cluster_arst_l"; | |
2780 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.cluster_div_en"; | |
2781 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.cmp_slow_sync_en"; | |
2782 | input dr_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.dr_sync_en"; | |
2783 | input io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.io2x_sync_en"; | |
2784 | input l2clk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.l2clk"; | |
2785 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.pce_ov"; | |
2786 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.por_"; | |
2787 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.rst_por_"; | |
2788 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.rst_wmr_"; | |
2789 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.rst_wmr_protect"; | |
2790 | input scan_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.scan_en"; | |
2791 | input scan_in PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.scan_in"; | |
2792 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.scan_out"; | |
2793 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.slow_cmp_sync_en"; | |
2794 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.tcu_aclk"; | |
2795 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.tcu_atpg_mode"; | |
2796 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.tcu_bclk"; | |
2797 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.tcu_clk_stop"; | |
2798 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.tcu_div_bypass"; | |
2799 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.tcu_pce_ov"; | |
2800 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.tcu_wr_inhibit"; | |
2801 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.wmr_"; | |
2802 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.wmr_protect"; | |
2803 | } | |
2804 | ||
2805 | interface clkgen_mcu1_cmp_l2clk_if { | |
2806 | input l2clk CLOCK verilog_node "`CPU.mcu1.clkgen_cmp.l2clk"; // Vera interface clock | |
2807 | ||
2808 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.aclk"; | |
2809 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.aclk_wmr"; | |
2810 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.array_wr_inhibit"; | |
2811 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.bclk"; | |
2812 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.cmp_slow_sync_en"; | |
2813 | input dr_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.dr_sync_en"; | |
2814 | input io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.io2x_sync_en"; | |
2815 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.pce_ov"; | |
2816 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.por_"; | |
2817 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.scan_out"; | |
2818 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.slow_cmp_sync_en"; | |
2819 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.wmr_"; | |
2820 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.wmr_protect"; | |
2821 | } | |
2822 | ||
2823 | //----- VERA interfaces for clkgen_mcu1_dr ----- | |
2824 | ||
2825 | interface clkgen_mcu1_dr_gclk_if { | |
2826 | input gclk CLOCK verilog_node "`CPU.mcu1.clkgen_dr.gclk"; // Vera interface clock | |
2827 | ||
2828 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.aclk"; | |
2829 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.aclk_wmr"; | |
2830 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.array_wr_inhibit"; | |
2831 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.bclk"; | |
2832 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.ccu_cmp_slow_sync_en"; | |
2833 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.ccu_div_ph"; | |
2834 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.ccu_serdes_dtm"; | |
2835 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.ccu_slow_cmp_sync_en"; | |
2836 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.clk_ext"; | |
2837 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.cluster_arst_l"; | |
2838 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.cluster_div_en"; | |
2839 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.cmp_slow_sync_en"; | |
2840 | input l2clk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.l2clk"; | |
2841 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.pce_ov"; | |
2842 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.por_"; | |
2843 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.rst_por_"; | |
2844 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.rst_wmr_"; | |
2845 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.rst_wmr_protect"; | |
2846 | input scan_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.scan_en"; | |
2847 | input scan_in PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.scan_in"; | |
2848 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.scan_out"; | |
2849 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.slow_cmp_sync_en"; | |
2850 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.tcu_aclk"; | |
2851 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.tcu_atpg_mode"; | |
2852 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.tcu_bclk"; | |
2853 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.tcu_clk_stop"; | |
2854 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.tcu_div_bypass"; | |
2855 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.tcu_pce_ov"; | |
2856 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.tcu_wr_inhibit"; | |
2857 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.wmr_"; | |
2858 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.wmr_protect"; | |
2859 | } | |
2860 | ||
2861 | interface clkgen_mcu1_dr_l2clk_if { | |
2862 | input l2clk CLOCK verilog_node "`CPU.mcu1.clkgen_dr.l2clk"; // Vera interface clock | |
2863 | ||
2864 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.aclk"; | |
2865 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.aclk_wmr"; | |
2866 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.array_wr_inhibit"; | |
2867 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.bclk"; | |
2868 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.cmp_slow_sync_en"; | |
2869 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.pce_ov"; | |
2870 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.por_"; | |
2871 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.scan_out"; | |
2872 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.slow_cmp_sync_en"; | |
2873 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.wmr_"; | |
2874 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.wmr_protect"; | |
2875 | } | |
2876 | ||
2877 | //----- VERA interfaces for clkgen_mcu1_io ----- | |
2878 | ||
2879 | interface clkgen_mcu1_io_gclk_if { | |
2880 | input gclk CLOCK verilog_node "`CPU.mcu1.clkgen_io.gclk"; // Vera interface clock | |
2881 | ||
2882 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.aclk"; | |
2883 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.aclk_wmr"; | |
2884 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.array_wr_inhibit"; | |
2885 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.bclk"; | |
2886 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.ccu_cmp_slow_sync_en"; | |
2887 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.ccu_div_ph"; | |
2888 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.ccu_serdes_dtm"; | |
2889 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.ccu_slow_cmp_sync_en"; | |
2890 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.clk_ext"; | |
2891 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.cluster_arst_l"; | |
2892 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.cluster_div_en"; | |
2893 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.cmp_slow_sync_en"; | |
2894 | input l2clk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.l2clk"; | |
2895 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.pce_ov"; | |
2896 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.por_"; | |
2897 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.rst_por_"; | |
2898 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.rst_wmr_"; | |
2899 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.rst_wmr_protect"; | |
2900 | input scan_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.scan_en"; | |
2901 | input scan_in PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.scan_in"; | |
2902 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.scan_out"; | |
2903 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.slow_cmp_sync_en"; | |
2904 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.tcu_aclk"; | |
2905 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.tcu_atpg_mode"; | |
2906 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.tcu_bclk"; | |
2907 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.tcu_clk_stop"; | |
2908 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.tcu_div_bypass"; | |
2909 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.tcu_pce_ov"; | |
2910 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.tcu_wr_inhibit"; | |
2911 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.wmr_"; | |
2912 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.wmr_protect"; | |
2913 | } | |
2914 | ||
2915 | interface clkgen_mcu1_io_l2clk_if { | |
2916 | input l2clk CLOCK verilog_node "`CPU.mcu1.clkgen_io.l2clk"; // Vera interface clock | |
2917 | ||
2918 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.aclk"; | |
2919 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.aclk_wmr"; | |
2920 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.array_wr_inhibit"; | |
2921 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.bclk"; | |
2922 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.cmp_slow_sync_en"; | |
2923 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.pce_ov"; | |
2924 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.por_"; | |
2925 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.scan_out"; | |
2926 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.slow_cmp_sync_en"; | |
2927 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.wmr_"; | |
2928 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.wmr_protect"; | |
2929 | } | |
2930 | ||
2931 | //----- VERA interfaces for clkgen_mcu2_cmp ----- | |
2932 | ||
2933 | interface clkgen_mcu2_cmp_gclk_if { | |
2934 | input gclk CLOCK verilog_node "`CPU.mcu2.clkgen_cmp.gclk"; // Vera interface clock | |
2935 | ||
2936 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.aclk"; | |
2937 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.aclk_wmr"; | |
2938 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.array_wr_inhibit"; | |
2939 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.bclk"; | |
2940 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.ccu_cmp_slow_sync_en"; | |
2941 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.ccu_div_ph"; | |
2942 | input ccu_dr_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.ccu_dr_sync_en"; | |
2943 | input ccu_io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.ccu_io2x_sync_en"; | |
2944 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.ccu_serdes_dtm"; | |
2945 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.ccu_slow_cmp_sync_en"; | |
2946 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.clk_ext"; | |
2947 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.cluster_arst_l"; | |
2948 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.cluster_div_en"; | |
2949 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.cmp_slow_sync_en"; | |
2950 | input dr_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.dr_sync_en"; | |
2951 | input io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.io2x_sync_en"; | |
2952 | input l2clk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.l2clk"; | |
2953 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.pce_ov"; | |
2954 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.por_"; | |
2955 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.rst_por_"; | |
2956 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.rst_wmr_"; | |
2957 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.rst_wmr_protect"; | |
2958 | input scan_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.scan_en"; | |
2959 | input scan_in PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.scan_in"; | |
2960 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.scan_out"; | |
2961 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.slow_cmp_sync_en"; | |
2962 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.tcu_aclk"; | |
2963 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.tcu_atpg_mode"; | |
2964 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.tcu_bclk"; | |
2965 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.tcu_clk_stop"; | |
2966 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.tcu_div_bypass"; | |
2967 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.tcu_pce_ov"; | |
2968 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.tcu_wr_inhibit"; | |
2969 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.wmr_"; | |
2970 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.wmr_protect"; | |
2971 | } | |
2972 | ||
2973 | interface clkgen_mcu2_cmp_l2clk_if { | |
2974 | input l2clk CLOCK verilog_node "`CPU.mcu2.clkgen_cmp.l2clk"; // Vera interface clock | |
2975 | ||
2976 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.aclk"; | |
2977 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.aclk_wmr"; | |
2978 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.array_wr_inhibit"; | |
2979 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.bclk"; | |
2980 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.cmp_slow_sync_en"; | |
2981 | input dr_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.dr_sync_en"; | |
2982 | input io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.io2x_sync_en"; | |
2983 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.pce_ov"; | |
2984 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.por_"; | |
2985 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.scan_out"; | |
2986 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.slow_cmp_sync_en"; | |
2987 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.wmr_"; | |
2988 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.wmr_protect"; | |
2989 | } | |
2990 | ||
2991 | //----- VERA interfaces for clkgen_mcu2_dr ----- | |
2992 | ||
2993 | interface clkgen_mcu2_dr_gclk_if { | |
2994 | input gclk CLOCK verilog_node "`CPU.mcu2.clkgen_dr.gclk"; // Vera interface clock | |
2995 | ||
2996 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.aclk"; | |
2997 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.aclk_wmr"; | |
2998 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.array_wr_inhibit"; | |
2999 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.bclk"; | |
3000 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.ccu_cmp_slow_sync_en"; | |
3001 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.ccu_div_ph"; | |
3002 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.ccu_serdes_dtm"; | |
3003 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.ccu_slow_cmp_sync_en"; | |
3004 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.clk_ext"; | |
3005 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.cluster_arst_l"; | |
3006 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.cluster_div_en"; | |
3007 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.cmp_slow_sync_en"; | |
3008 | input l2clk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.l2clk"; | |
3009 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.pce_ov"; | |
3010 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.por_"; | |
3011 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.rst_por_"; | |
3012 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.rst_wmr_"; | |
3013 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.rst_wmr_protect"; | |
3014 | input scan_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.scan_en"; | |
3015 | input scan_in PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.scan_in"; | |
3016 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.scan_out"; | |
3017 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.slow_cmp_sync_en"; | |
3018 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.tcu_aclk"; | |
3019 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.tcu_atpg_mode"; | |
3020 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.tcu_bclk"; | |
3021 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.tcu_clk_stop"; | |
3022 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.tcu_div_bypass"; | |
3023 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.tcu_pce_ov"; | |
3024 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.tcu_wr_inhibit"; | |
3025 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.wmr_"; | |
3026 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.wmr_protect"; | |
3027 | } | |
3028 | ||
3029 | interface clkgen_mcu2_dr_l2clk_if { | |
3030 | input l2clk CLOCK verilog_node "`CPU.mcu2.clkgen_dr.l2clk"; // Vera interface clock | |
3031 | ||
3032 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.aclk"; | |
3033 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.aclk_wmr"; | |
3034 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.array_wr_inhibit"; | |
3035 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.bclk"; | |
3036 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.cmp_slow_sync_en"; | |
3037 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.pce_ov"; | |
3038 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.por_"; | |
3039 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.scan_out"; | |
3040 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.slow_cmp_sync_en"; | |
3041 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.wmr_"; | |
3042 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.wmr_protect"; | |
3043 | } | |
3044 | ||
3045 | //----- VERA interfaces for clkgen_mcu2_io ----- | |
3046 | ||
3047 | interface clkgen_mcu2_io_gclk_if { | |
3048 | input gclk CLOCK verilog_node "`CPU.mcu2.clkgen_io.gclk"; // Vera interface clock | |
3049 | ||
3050 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.aclk"; | |
3051 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.aclk_wmr"; | |
3052 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.array_wr_inhibit"; | |
3053 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.bclk"; | |
3054 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.ccu_cmp_slow_sync_en"; | |
3055 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.ccu_div_ph"; | |
3056 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.ccu_serdes_dtm"; | |
3057 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.ccu_slow_cmp_sync_en"; | |
3058 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.clk_ext"; | |
3059 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.cluster_arst_l"; | |
3060 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.cluster_div_en"; | |
3061 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.cmp_slow_sync_en"; | |
3062 | input l2clk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.l2clk"; | |
3063 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.pce_ov"; | |
3064 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.por_"; | |
3065 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.rst_por_"; | |
3066 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.rst_wmr_"; | |
3067 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.rst_wmr_protect"; | |
3068 | input scan_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.scan_en"; | |
3069 | input scan_in PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.scan_in"; | |
3070 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.scan_out"; | |
3071 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.slow_cmp_sync_en"; | |
3072 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.tcu_aclk"; | |
3073 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.tcu_atpg_mode"; | |
3074 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.tcu_bclk"; | |
3075 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.tcu_clk_stop"; | |
3076 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.tcu_div_bypass"; | |
3077 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.tcu_pce_ov"; | |
3078 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.tcu_wr_inhibit"; | |
3079 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.wmr_"; | |
3080 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.wmr_protect"; | |
3081 | } | |
3082 | ||
3083 | interface clkgen_mcu2_io_l2clk_if { | |
3084 | input l2clk CLOCK verilog_node "`CPU.mcu2.clkgen_io.l2clk"; // Vera interface clock | |
3085 | ||
3086 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.aclk"; | |
3087 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.aclk_wmr"; | |
3088 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.array_wr_inhibit"; | |
3089 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.bclk"; | |
3090 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.cmp_slow_sync_en"; | |
3091 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.pce_ov"; | |
3092 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.por_"; | |
3093 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.scan_out"; | |
3094 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.slow_cmp_sync_en"; | |
3095 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.wmr_"; | |
3096 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.wmr_protect"; | |
3097 | } | |
3098 | ||
3099 | //----- VERA interfaces for clkgen_mcu3_cmp ----- | |
3100 | ||
3101 | interface clkgen_mcu3_cmp_gclk_if { | |
3102 | input gclk CLOCK verilog_node "`CPU.mcu3.clkgen_cmp.gclk"; // Vera interface clock | |
3103 | ||
3104 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.aclk"; | |
3105 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.aclk_wmr"; | |
3106 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.array_wr_inhibit"; | |
3107 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.bclk"; | |
3108 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.ccu_cmp_slow_sync_en"; | |
3109 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.ccu_div_ph"; | |
3110 | input ccu_dr_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.ccu_dr_sync_en"; | |
3111 | input ccu_io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.ccu_io2x_sync_en"; | |
3112 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.ccu_serdes_dtm"; | |
3113 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.ccu_slow_cmp_sync_en"; | |
3114 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.clk_ext"; | |
3115 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.cluster_arst_l"; | |
3116 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.cluster_div_en"; | |
3117 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.cmp_slow_sync_en"; | |
3118 | input dr_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.dr_sync_en"; | |
3119 | input io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.io2x_sync_en"; | |
3120 | input l2clk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.l2clk"; | |
3121 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.pce_ov"; | |
3122 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.por_"; | |
3123 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.rst_por_"; | |
3124 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.rst_wmr_"; | |
3125 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.rst_wmr_protect"; | |
3126 | input scan_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.scan_en"; | |
3127 | input scan_in PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.scan_in"; | |
3128 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.scan_out"; | |
3129 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.slow_cmp_sync_en"; | |
3130 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.tcu_aclk"; | |
3131 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.tcu_atpg_mode"; | |
3132 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.tcu_bclk"; | |
3133 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.tcu_clk_stop"; | |
3134 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.tcu_div_bypass"; | |
3135 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.tcu_pce_ov"; | |
3136 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.tcu_wr_inhibit"; | |
3137 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.wmr_"; | |
3138 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.wmr_protect"; | |
3139 | } | |
3140 | ||
3141 | interface clkgen_mcu3_cmp_l2clk_if { | |
3142 | input l2clk CLOCK verilog_node "`CPU.mcu3.clkgen_cmp.l2clk"; // Vera interface clock | |
3143 | ||
3144 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.aclk"; | |
3145 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.aclk_wmr"; | |
3146 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.array_wr_inhibit"; | |
3147 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.bclk"; | |
3148 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.cmp_slow_sync_en"; | |
3149 | input dr_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.dr_sync_en"; | |
3150 | input io2x_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.io2x_sync_en"; | |
3151 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.pce_ov"; | |
3152 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.por_"; | |
3153 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.scan_out"; | |
3154 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.slow_cmp_sync_en"; | |
3155 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.wmr_"; | |
3156 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.wmr_protect"; | |
3157 | } | |
3158 | ||
3159 | //----- VERA interfaces for clkgen_mcu3_dr ----- | |
3160 | ||
3161 | interface clkgen_mcu3_dr_gclk_if { | |
3162 | input gclk CLOCK verilog_node "`CPU.mcu3.clkgen_dr.gclk"; // Vera interface clock | |
3163 | ||
3164 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.aclk"; | |
3165 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.aclk_wmr"; | |
3166 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.array_wr_inhibit"; | |
3167 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.bclk"; | |
3168 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.ccu_cmp_slow_sync_en"; | |
3169 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.ccu_div_ph"; | |
3170 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.ccu_serdes_dtm"; | |
3171 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.ccu_slow_cmp_sync_en"; | |
3172 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.clk_ext"; | |
3173 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.cluster_arst_l"; | |
3174 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.cluster_div_en"; | |
3175 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.cmp_slow_sync_en"; | |
3176 | input l2clk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.l2clk"; | |
3177 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.pce_ov"; | |
3178 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.por_"; | |
3179 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.rst_por_"; | |
3180 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.rst_wmr_"; | |
3181 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.rst_wmr_protect"; | |
3182 | input scan_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.scan_en"; | |
3183 | input scan_in PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.scan_in"; | |
3184 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.scan_out"; | |
3185 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.slow_cmp_sync_en"; | |
3186 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.tcu_aclk"; | |
3187 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.tcu_atpg_mode"; | |
3188 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.tcu_bclk"; | |
3189 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.tcu_clk_stop"; | |
3190 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.tcu_div_bypass"; | |
3191 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.tcu_pce_ov"; | |
3192 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.tcu_wr_inhibit"; | |
3193 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.wmr_"; | |
3194 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.wmr_protect"; | |
3195 | } | |
3196 | ||
3197 | interface clkgen_mcu3_dr_l2clk_if { | |
3198 | input l2clk CLOCK verilog_node "`CPU.mcu3.clkgen_dr.l2clk"; // Vera interface clock | |
3199 | ||
3200 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.aclk"; | |
3201 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.aclk_wmr"; | |
3202 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.array_wr_inhibit"; | |
3203 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.bclk"; | |
3204 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.cmp_slow_sync_en"; | |
3205 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.pce_ov"; | |
3206 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.por_"; | |
3207 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.scan_out"; | |
3208 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.slow_cmp_sync_en"; | |
3209 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.wmr_"; | |
3210 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.wmr_protect"; | |
3211 | } | |
3212 | ||
3213 | //----- VERA interfaces for clkgen_mcu3_io ----- | |
3214 | ||
3215 | interface clkgen_mcu3_io_gclk_if { | |
3216 | input gclk CLOCK verilog_node "`CPU.mcu3.clkgen_io.gclk"; // Vera interface clock | |
3217 | ||
3218 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.aclk"; | |
3219 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.aclk_wmr"; | |
3220 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.array_wr_inhibit"; | |
3221 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.bclk"; | |
3222 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.ccu_cmp_slow_sync_en"; | |
3223 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.ccu_div_ph"; | |
3224 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.ccu_serdes_dtm"; | |
3225 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.ccu_slow_cmp_sync_en"; | |
3226 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.clk_ext"; | |
3227 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.cluster_arst_l"; | |
3228 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.cluster_div_en"; | |
3229 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.cmp_slow_sync_en"; | |
3230 | input l2clk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.l2clk"; | |
3231 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.pce_ov"; | |
3232 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.por_"; | |
3233 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.rst_por_"; | |
3234 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.rst_wmr_"; | |
3235 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.rst_wmr_protect"; | |
3236 | input scan_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.scan_en"; | |
3237 | input scan_in PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.scan_in"; | |
3238 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.scan_out"; | |
3239 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.slow_cmp_sync_en"; | |
3240 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.tcu_aclk"; | |
3241 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.tcu_atpg_mode"; | |
3242 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.tcu_bclk"; | |
3243 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.tcu_clk_stop"; | |
3244 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.tcu_div_bypass"; | |
3245 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.tcu_pce_ov"; | |
3246 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.tcu_wr_inhibit"; | |
3247 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.wmr_"; | |
3248 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.wmr_protect"; | |
3249 | } | |
3250 | ||
3251 | interface clkgen_mcu3_io_l2clk_if { | |
3252 | input l2clk CLOCK verilog_node "`CPU.mcu3.clkgen_io.l2clk"; // Vera interface clock | |
3253 | ||
3254 | input aclk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.aclk"; | |
3255 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.aclk_wmr"; | |
3256 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.array_wr_inhibit"; | |
3257 | input bclk PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.bclk"; | |
3258 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.cmp_slow_sync_en"; | |
3259 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.pce_ov"; | |
3260 | input por_ PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.por_"; | |
3261 | input scan_out PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.scan_out"; | |
3262 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.slow_cmp_sync_en"; | |
3263 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.wmr_"; | |
3264 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.wmr_protect"; | |
3265 | } | |
3266 | ||
3267 | // added this: | |
3268 | #ifndef FC_NO_PEU_VERA | |
3269 | #ifndef PEU_SYSTEMC_T2 | |
3270 | //----- VERA interfaces for clkgen_peu_io ----- | |
3271 | ||
3272 | interface clkgen_peu_io_gclk_if { | |
3273 | input gclk CLOCK verilog_node "`CPU.peu.peu_iol2clk_gen.gclk"; // Vera interface clock | |
3274 | ||
3275 | input aclk PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.aclk"; | |
3276 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.aclk_wmr"; | |
3277 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.array_wr_inhibit"; | |
3278 | input bclk PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.bclk"; | |
3279 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.ccu_cmp_slow_sync_en"; | |
3280 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.ccu_div_ph"; | |
3281 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.ccu_serdes_dtm"; | |
3282 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.ccu_slow_cmp_sync_en"; | |
3283 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.clk_ext"; | |
3284 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.cluster_arst_l"; | |
3285 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.cluster_div_en"; | |
3286 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.cmp_slow_sync_en"; | |
3287 | input l2clk PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.l2clk"; | |
3288 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.pce_ov"; | |
3289 | input por_ PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.por_"; | |
3290 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.rst_por_"; | |
3291 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.rst_wmr_"; | |
3292 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.rst_wmr_protect"; | |
3293 | input scan_en PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.scan_en"; | |
3294 | input scan_in PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.scan_in"; | |
3295 | input scan_out PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.scan_out"; | |
3296 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.slow_cmp_sync_en"; | |
3297 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.tcu_aclk"; | |
3298 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.tcu_atpg_mode"; | |
3299 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.tcu_bclk"; | |
3300 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.tcu_clk_stop"; | |
3301 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.tcu_div_bypass"; | |
3302 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.tcu_pce_ov"; | |
3303 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.tcu_wr_inhibit"; | |
3304 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.wmr_"; | |
3305 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.wmr_protect"; | |
3306 | } | |
3307 | ||
3308 | interface clkgen_peu_io_l2clk_if { | |
3309 | input l2clk CLOCK verilog_node "`CPU.peu.peu_iol2clk_gen.l2clk"; // Vera interface clock | |
3310 | ||
3311 | input aclk PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.aclk"; | |
3312 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.aclk_wmr"; | |
3313 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.array_wr_inhibit"; | |
3314 | input bclk PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.bclk"; | |
3315 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.cmp_slow_sync_en"; | |
3316 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.pce_ov"; | |
3317 | input por_ PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.por_"; | |
3318 | input scan_out PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.scan_out"; | |
3319 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.slow_cmp_sync_en"; | |
3320 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.wmr_"; | |
3321 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.wmr_protect"; | |
3322 | } | |
3323 | ||
3324 | //----- VERA interfaces for clkgen_peu_pc ----- | |
3325 | ||
3326 | interface clkgen_peu_pc_gclk_if { | |
3327 | input gclk CLOCK verilog_node "`CPU.peu.peu_pcl2clk_gen.gclk"; // Vera interface clock | |
3328 | ||
3329 | input aclk PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.aclk"; | |
3330 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.aclk_wmr"; | |
3331 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.array_wr_inhibit"; | |
3332 | input bclk PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.bclk"; | |
3333 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.ccu_div_ph"; | |
3334 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.cluster_arst_l"; | |
3335 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.cluster_div_en"; | |
3336 | input l2clk PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.l2clk"; | |
3337 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.pce_ov"; | |
3338 | input por_ PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.por_"; | |
3339 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.rst_por_"; | |
3340 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.rst_wmr_"; | |
3341 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.rst_wmr_protect"; | |
3342 | input scan_en PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.scan_en"; | |
3343 | input scan_in PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.scan_in"; | |
3344 | input scan_out PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.scan_out"; | |
3345 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.tcu_aclk"; | |
3346 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.tcu_atpg_mode"; | |
3347 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.tcu_bclk"; | |
3348 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.tcu_clk_stop"; | |
3349 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.tcu_pce_ov"; | |
3350 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.tcu_wr_inhibit"; | |
3351 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.wmr_"; | |
3352 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.wmr_protect"; | |
3353 | input pc_clk PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.pc_clk"; | |
3354 | input pc_clk_sel PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.pc_clk_sel"; | |
3355 | input test_clk PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.test_clk"; | |
3356 | input test_clk_sel PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.test_clk_sel"; | |
3357 | } | |
3358 | ||
3359 | interface clkgen_peu_pc_l2clk_if { | |
3360 | input l2clk CLOCK verilog_node "`CPU.peu.peu_pcl2clk_gen.l2clk"; // Vera interface clock | |
3361 | ||
3362 | input aclk PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.aclk"; | |
3363 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.aclk_wmr"; | |
3364 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.array_wr_inhibit"; | |
3365 | input bclk PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.bclk"; | |
3366 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.pce_ov"; | |
3367 | input por_ PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.por_"; | |
3368 | input scan_out PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.scan_out"; | |
3369 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.wmr_"; | |
3370 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.wmr_protect"; | |
3371 | } | |
3372 | #endif | |
3373 | #endif | |
3374 | ||
3375 | #ifndef FC_NO_NIU_T2 | |
3376 | #ifndef NIU_SYSTEMC_T2 | |
3377 | //----- VERA interfaces for clkgen_rdp_io ----- | |
3378 | ||
3379 | interface clkgen_rdp_io_gclk_if { | |
3380 | input gclk CLOCK verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.gclk"; // Vera interface clock | |
3381 | ||
3382 | input aclk PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.aclk"; | |
3383 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.aclk_wmr"; | |
3384 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.array_wr_inhibit"; | |
3385 | input bclk PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.bclk"; | |
3386 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.ccu_cmp_slow_sync_en"; | |
3387 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.ccu_div_ph"; | |
3388 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.ccu_serdes_dtm"; | |
3389 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.ccu_slow_cmp_sync_en"; | |
3390 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.clk_ext"; | |
3391 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.cluster_arst_l"; | |
3392 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.cluster_div_en"; | |
3393 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.cmp_slow_sync_en"; | |
3394 | input l2clk PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.l2clk"; | |
3395 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.pce_ov"; | |
3396 | input por_ PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.por_"; | |
3397 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.rst_por_"; | |
3398 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.rst_wmr_"; | |
3399 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.rst_wmr_protect"; | |
3400 | input scan_en PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.scan_en"; | |
3401 | input scan_in PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.scan_in"; | |
3402 | input scan_out PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.scan_out"; | |
3403 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.slow_cmp_sync_en"; | |
3404 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.tcu_aclk"; | |
3405 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.tcu_atpg_mode"; | |
3406 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.tcu_bclk"; | |
3407 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.tcu_clk_stop"; | |
3408 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.tcu_div_bypass"; | |
3409 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.tcu_pce_ov"; | |
3410 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.tcu_wr_inhibit"; | |
3411 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.wmr_"; | |
3412 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.wmr_protect"; | |
3413 | } | |
3414 | ||
3415 | interface clkgen_rdp_io_l2clk_if { | |
3416 | input l2clk CLOCK verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.l2clk"; // Vera interface clock | |
3417 | ||
3418 | input aclk PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.aclk"; | |
3419 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.aclk_wmr"; | |
3420 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.array_wr_inhibit"; | |
3421 | input bclk PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.bclk"; | |
3422 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.cmp_slow_sync_en"; | |
3423 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.pce_ov"; | |
3424 | input por_ PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.por_"; | |
3425 | input scan_out PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.scan_out"; | |
3426 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.slow_cmp_sync_en"; | |
3427 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.wmr_"; | |
3428 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.wmr_protect"; | |
3429 | } | |
3430 | ||
3431 | //----- VERA interfaces for clkgen_rdp_io2x ----- | |
3432 | ||
3433 | interface clkgen_rdp_io2x_gclk_if { | |
3434 | input gclk CLOCK verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.gclk"; // Vera interface clock | |
3435 | ||
3436 | input aclk PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.aclk"; | |
3437 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.aclk_wmr"; | |
3438 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.array_wr_inhibit"; | |
3439 | input bclk PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.bclk"; | |
3440 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.ccu_cmp_slow_sync_en"; | |
3441 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.ccu_div_ph"; | |
3442 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.ccu_serdes_dtm"; | |
3443 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.ccu_slow_cmp_sync_en"; | |
3444 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.clk_ext"; | |
3445 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.cluster_arst_l"; | |
3446 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.cluster_div_en"; | |
3447 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.cmp_slow_sync_en"; | |
3448 | input l2clk PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.l2clk"; | |
3449 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.pce_ov"; | |
3450 | input por_ PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.por_"; | |
3451 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.rst_por_"; | |
3452 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.rst_wmr_"; | |
3453 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.rst_wmr_protect"; | |
3454 | input scan_en PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.scan_en"; | |
3455 | input scan_in PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.scan_in"; | |
3456 | input scan_out PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.scan_out"; | |
3457 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.slow_cmp_sync_en"; | |
3458 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.tcu_aclk"; | |
3459 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.tcu_atpg_mode"; | |
3460 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.tcu_bclk"; | |
3461 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.tcu_clk_stop"; | |
3462 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.tcu_div_bypass"; | |
3463 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.tcu_pce_ov"; | |
3464 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.tcu_wr_inhibit"; | |
3465 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.wmr_"; | |
3466 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.wmr_protect"; | |
3467 | } | |
3468 | ||
3469 | interface clkgen_rdp_io2x_l2clk_if { | |
3470 | input l2clk CLOCK verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.l2clk"; // Vera interface clock | |
3471 | ||
3472 | input aclk PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.aclk"; | |
3473 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.aclk_wmr"; | |
3474 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.array_wr_inhibit"; | |
3475 | input bclk PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.bclk"; | |
3476 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.cmp_slow_sync_en"; | |
3477 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.pce_ov"; | |
3478 | input por_ PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.por_"; | |
3479 | input scan_out PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.scan_out"; | |
3480 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.slow_cmp_sync_en"; | |
3481 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.wmr_"; | |
3482 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.wmr_protect"; | |
3483 | } | |
3484 | ||
3485 | //----- VERA interfaces for clkgen_rtx_io ----- | |
3486 | ||
3487 | interface clkgen_rtx_io_gclk_if { | |
3488 | input gclk CLOCK verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.gclk"; // Vera interface clock | |
3489 | ||
3490 | input aclk PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.aclk"; | |
3491 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.aclk_wmr"; | |
3492 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.array_wr_inhibit"; | |
3493 | input bclk PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.bclk"; | |
3494 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.ccu_cmp_slow_sync_en"; | |
3495 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.ccu_div_ph"; | |
3496 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.ccu_serdes_dtm"; | |
3497 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.ccu_slow_cmp_sync_en"; | |
3498 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.clk_ext"; | |
3499 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.cluster_arst_l"; | |
3500 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.cluster_div_en"; | |
3501 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.cmp_slow_sync_en"; | |
3502 | input l2clk PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.l2clk"; | |
3503 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.pce_ov"; | |
3504 | input por_ PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.por_"; | |
3505 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.rst_por_"; | |
3506 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.rst_wmr_"; | |
3507 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.rst_wmr_protect"; | |
3508 | input scan_en PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.scan_en"; | |
3509 | input scan_in PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.scan_in"; | |
3510 | input scan_out PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.scan_out"; | |
3511 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.slow_cmp_sync_en"; | |
3512 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.tcu_aclk"; | |
3513 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.tcu_atpg_mode"; | |
3514 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.tcu_bclk"; | |
3515 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.tcu_clk_stop"; | |
3516 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.tcu_div_bypass"; | |
3517 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.tcu_pce_ov"; | |
3518 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.tcu_wr_inhibit"; | |
3519 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.wmr_"; | |
3520 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.wmr_protect"; | |
3521 | } | |
3522 | ||
3523 | interface clkgen_rtx_io_l2clk_if { | |
3524 | input l2clk CLOCK verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.l2clk"; // Vera interface clock | |
3525 | ||
3526 | input aclk PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.aclk"; | |
3527 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.aclk_wmr"; | |
3528 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.array_wr_inhibit"; | |
3529 | input bclk PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.bclk"; | |
3530 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.cmp_slow_sync_en"; | |
3531 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.pce_ov"; | |
3532 | input por_ PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.por_"; | |
3533 | input scan_out PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.scan_out"; | |
3534 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.slow_cmp_sync_en"; | |
3535 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.wmr_"; | |
3536 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.wmr_protect"; | |
3537 | } | |
3538 | ||
3539 | //----- VERA interfaces for clkgen_rtx_io2x ----- | |
3540 | ||
3541 | interface clkgen_rtx_io2x_gclk_if { | |
3542 | input gclk CLOCK verilog_node "`CPU.rtx.clkgen2x_rtx.gclk"; // Vera interface clock | |
3543 | ||
3544 | input aclk PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.aclk"; | |
3545 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.aclk_wmr"; | |
3546 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.array_wr_inhibit"; | |
3547 | input bclk PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.bclk"; | |
3548 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.ccu_cmp_slow_sync_en"; | |
3549 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.ccu_div_ph"; | |
3550 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.ccu_serdes_dtm"; | |
3551 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.ccu_slow_cmp_sync_en"; | |
3552 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.clk_ext"; | |
3553 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.cluster_arst_l"; | |
3554 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.cluster_div_en"; | |
3555 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.cmp_slow_sync_en"; | |
3556 | input l2clk PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.l2clk"; | |
3557 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.pce_ov"; | |
3558 | input por_ PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.por_"; | |
3559 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.rst_por_"; | |
3560 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.rst_wmr_"; | |
3561 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.rst_wmr_protect"; | |
3562 | input scan_en PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.scan_en"; | |
3563 | input scan_in PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.scan_in"; | |
3564 | input scan_out PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.scan_out"; | |
3565 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.slow_cmp_sync_en"; | |
3566 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.tcu_aclk"; | |
3567 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.tcu_atpg_mode"; | |
3568 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.tcu_bclk"; | |
3569 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.tcu_clk_stop"; | |
3570 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.tcu_div_bypass"; | |
3571 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.tcu_pce_ov"; | |
3572 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.tcu_wr_inhibit"; | |
3573 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.wmr_"; | |
3574 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.wmr_protect"; | |
3575 | } | |
3576 | ||
3577 | interface clkgen_rtx_io2x_l2clk_if { | |
3578 | input l2clk CLOCK verilog_node "`CPU.rtx.clkgen2x_rtx.l2clk"; // Vera interface clock | |
3579 | ||
3580 | input aclk PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.aclk"; | |
3581 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.aclk_wmr"; | |
3582 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.array_wr_inhibit"; | |
3583 | input bclk PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.bclk"; | |
3584 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.cmp_slow_sync_en"; | |
3585 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.pce_ov"; | |
3586 | input por_ PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.por_"; | |
3587 | input scan_out PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.scan_out"; | |
3588 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.slow_cmp_sync_en"; | |
3589 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.wmr_"; | |
3590 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.wmr_protect"; | |
3591 | } | |
3592 | #endif | |
3593 | #endif | |
3594 | ||
3595 | //----- VERA interfaces for clkgen_sii_cmp ----- | |
3596 | ||
3597 | interface clkgen_sii_cmp_gclk_if { | |
3598 | input gclk CLOCK verilog_node "`CPU.sii.clkgen_cmp.gclk"; // Vera interface clock | |
3599 | ||
3600 | input aclk PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.aclk"; | |
3601 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.aclk_wmr"; | |
3602 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.array_wr_inhibit"; | |
3603 | input bclk PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.bclk"; | |
3604 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.ccu_cmp_slow_sync_en"; | |
3605 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.ccu_div_ph"; | |
3606 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.ccu_serdes_dtm"; | |
3607 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.ccu_slow_cmp_sync_en"; | |
3608 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.clk_ext"; | |
3609 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.cluster_arst_l"; | |
3610 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.cluster_div_en"; | |
3611 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.cmp_slow_sync_en"; | |
3612 | input l2clk PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.l2clk"; | |
3613 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.pce_ov"; | |
3614 | input por_ PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.por_"; | |
3615 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.rst_por_"; | |
3616 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.rst_wmr_"; | |
3617 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.rst_wmr_protect"; | |
3618 | input scan_en PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.tcu_scan_en"; | |
3619 | input scan_in PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.scan_in"; | |
3620 | input scan_out PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.scan_out"; | |
3621 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.slow_cmp_sync_en"; | |
3622 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.tcu_aclk"; | |
3623 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.tcu_atpg_mode"; | |
3624 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.tcu_bclk"; | |
3625 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.tcu_clk_stop"; | |
3626 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.tcu_div_bypass"; | |
3627 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.tcu_pce_ov"; | |
3628 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.tcu_wr_inhibit"; | |
3629 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.wmr_"; | |
3630 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.wmr_protect"; | |
3631 | } | |
3632 | ||
3633 | interface clkgen_sii_cmp_l2clk_if { | |
3634 | input l2clk CLOCK verilog_node "`CPU.sii.clkgen_cmp.l2clk"; // Vera interface clock | |
3635 | ||
3636 | input aclk PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.aclk"; | |
3637 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.aclk_wmr"; | |
3638 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.array_wr_inhibit"; | |
3639 | input bclk PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.bclk"; | |
3640 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.cmp_slow_sync_en"; | |
3641 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.pce_ov"; | |
3642 | input por_ PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.por_"; | |
3643 | input scan_out PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.scan_out"; | |
3644 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.slow_cmp_sync_en"; | |
3645 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.wmr_"; | |
3646 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.wmr_protect"; | |
3647 | } | |
3648 | ||
3649 | //----- VERA interfaces for clkgen_sii_io ----- | |
3650 | ||
3651 | interface clkgen_sii_io_gclk_if { | |
3652 | input gclk CLOCK verilog_node "`CPU.sii.clkgen_io.gclk"; // Vera interface clock | |
3653 | ||
3654 | input aclk PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.aclk"; | |
3655 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.aclk_wmr"; | |
3656 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.array_wr_inhibit"; | |
3657 | input bclk PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.bclk"; | |
3658 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.ccu_cmp_slow_sync_en"; | |
3659 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.ccu_div_ph"; | |
3660 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.ccu_serdes_dtm"; | |
3661 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.ccu_slow_cmp_sync_en"; | |
3662 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.clk_ext"; | |
3663 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.cluster_arst_l"; | |
3664 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.cluster_div_en"; | |
3665 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.cmp_slow_sync_en"; | |
3666 | input l2clk PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.l2clk"; | |
3667 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.pce_ov"; | |
3668 | input por_ PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.por_"; | |
3669 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.rst_por_"; | |
3670 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.rst_wmr_"; | |
3671 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.rst_wmr_protect"; | |
3672 | input scan_en PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.tcu_scan_en"; | |
3673 | input scan_in PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.scan_in"; | |
3674 | input scan_out PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.scan_out"; | |
3675 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.slow_cmp_sync_en"; | |
3676 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.tcu_aclk"; | |
3677 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.tcu_atpg_mode"; | |
3678 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.tcu_bclk"; | |
3679 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.tcu_clk_stop"; | |
3680 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.tcu_div_bypass"; | |
3681 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.tcu_pce_ov"; | |
3682 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.tcu_wr_inhibit"; | |
3683 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.wmr_"; | |
3684 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.wmr_protect"; | |
3685 | } | |
3686 | ||
3687 | interface clkgen_sii_io_l2clk_if { | |
3688 | input l2clk CLOCK verilog_node "`CPU.sii.clkgen_io.l2clk"; // Vera interface clock | |
3689 | ||
3690 | input aclk PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.aclk"; | |
3691 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.aclk_wmr"; | |
3692 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.array_wr_inhibit"; | |
3693 | input bclk PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.bclk"; | |
3694 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.cmp_slow_sync_en"; | |
3695 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.pce_ov"; | |
3696 | input por_ PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.por_"; | |
3697 | input scan_out PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.scan_out"; | |
3698 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.slow_cmp_sync_en"; | |
3699 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.wmr_"; | |
3700 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.wmr_protect"; | |
3701 | } | |
3702 | ||
3703 | //----- VERA interfaces for clkgen_sio_cmp ----- | |
3704 | ||
3705 | interface clkgen_sio_cmp_gclk_if { | |
3706 | input gclk CLOCK verilog_node "`CPU.sio.clkgen_cmp.gclk"; // Vera interface clock | |
3707 | ||
3708 | input aclk PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.aclk"; | |
3709 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.aclk_wmr"; | |
3710 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.array_wr_inhibit"; | |
3711 | input bclk PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.bclk"; | |
3712 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.ccu_cmp_slow_sync_en"; | |
3713 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.ccu_div_ph"; | |
3714 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.ccu_serdes_dtm"; | |
3715 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.ccu_slow_cmp_sync_en"; | |
3716 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.clk_ext"; | |
3717 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.cluster_arst_l"; | |
3718 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.cluster_div_en"; | |
3719 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.cmp_slow_sync_en"; | |
3720 | input l2clk PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.l2clk"; | |
3721 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.pce_ov"; | |
3722 | input por_ PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.por_"; | |
3723 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.rst_por_"; | |
3724 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.rst_wmr_"; | |
3725 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.rst_wmr_protect"; | |
3726 | input scan_en PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.tcu_scan_en"; | |
3727 | input scan_in PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.scan_in"; | |
3728 | input scan_out PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.scan_out"; | |
3729 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.slow_cmp_sync_en"; | |
3730 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.tcu_aclk"; | |
3731 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.tcu_atpg_mode"; | |
3732 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.tcu_bclk"; | |
3733 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.tcu_clk_stop"; | |
3734 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.tcu_div_bypass"; | |
3735 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.tcu_pce_ov"; | |
3736 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.tcu_wr_inhibit"; | |
3737 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.wmr_"; | |
3738 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.wmr_protect"; | |
3739 | } | |
3740 | ||
3741 | interface clkgen_sio_cmp_l2clk_if { | |
3742 | input l2clk CLOCK verilog_node "`CPU.sio.clkgen_cmp.l2clk"; // Vera interface clock | |
3743 | ||
3744 | input aclk PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.aclk"; | |
3745 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.aclk_wmr"; | |
3746 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.array_wr_inhibit"; | |
3747 | input bclk PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.bclk"; | |
3748 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.cmp_slow_sync_en"; | |
3749 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.pce_ov"; | |
3750 | input por_ PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.por_"; | |
3751 | input scan_out PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.scan_out"; | |
3752 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.slow_cmp_sync_en"; | |
3753 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.wmr_"; | |
3754 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.wmr_protect"; | |
3755 | } | |
3756 | ||
3757 | //----- VERA interfaces for clkgen_sio_io ----- | |
3758 | ||
3759 | interface clkgen_sio_io_gclk_if { | |
3760 | input gclk CLOCK verilog_node "`CPU.sio.clkgen_io.gclk"; // Vera interface clock | |
3761 | ||
3762 | input aclk PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.aclk"; | |
3763 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.aclk_wmr"; | |
3764 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.array_wr_inhibit"; | |
3765 | input bclk PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.bclk"; | |
3766 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.ccu_cmp_slow_sync_en"; | |
3767 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.ccu_div_ph"; | |
3768 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.ccu_serdes_dtm"; | |
3769 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.ccu_slow_cmp_sync_en"; | |
3770 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.clk_ext"; | |
3771 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.cluster_arst_l"; | |
3772 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.cluster_div_en"; | |
3773 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.cmp_slow_sync_en"; | |
3774 | input l2clk PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.l2clk"; | |
3775 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.pce_ov"; | |
3776 | input por_ PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.por_"; | |
3777 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.rst_por_"; | |
3778 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.rst_wmr_"; | |
3779 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.rst_wmr_protect"; | |
3780 | input scan_en PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.tcu_scan_en"; | |
3781 | input scan_in PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.scan_in"; | |
3782 | input scan_out PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.scan_out"; | |
3783 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.slow_cmp_sync_en"; | |
3784 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.tcu_aclk"; | |
3785 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.tcu_atpg_mode"; | |
3786 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.tcu_bclk"; | |
3787 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.tcu_clk_stop"; | |
3788 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.tcu_div_bypass"; | |
3789 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.tcu_pce_ov"; | |
3790 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.tcu_wr_inhibit"; | |
3791 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.wmr_"; | |
3792 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.wmr_protect"; | |
3793 | } | |
3794 | ||
3795 | interface clkgen_sio_io_l2clk_if { | |
3796 | input l2clk CLOCK verilog_node "`CPU.sio.clkgen_io.l2clk"; // Vera interface clock | |
3797 | ||
3798 | input aclk PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.aclk"; | |
3799 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.aclk_wmr"; | |
3800 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.array_wr_inhibit"; | |
3801 | input bclk PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.bclk"; | |
3802 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.cmp_slow_sync_en"; | |
3803 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.pce_ov"; | |
3804 | input por_ PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.por_"; | |
3805 | input scan_out PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.scan_out"; | |
3806 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.slow_cmp_sync_en"; | |
3807 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.wmr_"; | |
3808 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.wmr_protect"; | |
3809 | } | |
3810 | ||
3811 | //----- VERA interfaces for clkgen_spc0_cmp ----- | |
3812 | ||
3813 | #ifndef RTL_NO_SPC0 | |
3814 | ||
3815 | interface clkgen_spc0_cmp_gclk_if { | |
3816 | input gclk CLOCK verilog_node "`CPU.spc0.clk_spc.gclk"; // Vera interface clock | |
3817 | ||
3818 | input aclk PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.aclk"; | |
3819 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.aclk_wmr"; | |
3820 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.array_wr_inhibit"; | |
3821 | input bclk PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.bclk"; | |
3822 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.ccu_cmp_slow_sync_en"; | |
3823 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.ccu_div_ph"; | |
3824 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.ccu_serdes_dtm"; | |
3825 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.ccu_slow_cmp_sync_en"; | |
3826 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.clk_ext"; | |
3827 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.cluster_arst_l"; | |
3828 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.cluster_div_en"; | |
3829 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.cmp_slow_sync_en"; | |
3830 | input l2clk PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.l2clk"; | |
3831 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.pce_ov"; | |
3832 | input por_ PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.por_"; | |
3833 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.rst_por_"; | |
3834 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.rst_wmr_"; | |
3835 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.rst_wmr_protect"; | |
3836 | input scan_en PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.scan_en"; | |
3837 | input scan_in PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.scan_in"; | |
3838 | input scan_out PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.scan_out"; | |
3839 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.slow_cmp_sync_en"; | |
3840 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.tcu_aclk"; | |
3841 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.tcu_atpg_mode"; | |
3842 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.tcu_bclk"; | |
3843 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.tcu_clk_stop"; | |
3844 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.tcu_div_bypass"; | |
3845 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.tcu_pce_ov"; | |
3846 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.tcu_wr_inhibit"; | |
3847 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.wmr_"; | |
3848 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.wmr_protect"; | |
3849 | } | |
3850 | ||
3851 | interface clkgen_spc0_cmp_l2clk_if { | |
3852 | input l2clk CLOCK verilog_node "`CPU.spc0.clk_spc.l2clk"; // Vera interface clock | |
3853 | ||
3854 | input aclk PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.aclk"; | |
3855 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.aclk_wmr"; | |
3856 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.array_wr_inhibit"; | |
3857 | input bclk PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.bclk"; | |
3858 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.cmp_slow_sync_en"; | |
3859 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.pce_ov"; | |
3860 | input por_ PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.por_"; | |
3861 | input scan_out PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.scan_out"; | |
3862 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.slow_cmp_sync_en"; | |
3863 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.wmr_"; | |
3864 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.wmr_protect"; | |
3865 | } | |
3866 | ||
3867 | #endif | |
3868 | ||
3869 | //----- VERA interfaces for clkgen_spc1_cmp ----- | |
3870 | ||
3871 | #ifndef RTL_NO_SPC1 | |
3872 | ||
3873 | interface clkgen_spc1_cmp_gclk_if { | |
3874 | input gclk CLOCK verilog_node "`CPU.spc1.clk_spc.gclk"; // Vera interface clock | |
3875 | ||
3876 | input aclk PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.aclk"; | |
3877 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.aclk_wmr"; | |
3878 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.array_wr_inhibit"; | |
3879 | input bclk PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.bclk"; | |
3880 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.ccu_cmp_slow_sync_en"; | |
3881 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.ccu_div_ph"; | |
3882 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.ccu_serdes_dtm"; | |
3883 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.ccu_slow_cmp_sync_en"; | |
3884 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.clk_ext"; | |
3885 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.cluster_arst_l"; | |
3886 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.cluster_div_en"; | |
3887 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.cmp_slow_sync_en"; | |
3888 | input l2clk PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.l2clk"; | |
3889 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.pce_ov"; | |
3890 | input por_ PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.por_"; | |
3891 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.rst_por_"; | |
3892 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.rst_wmr_"; | |
3893 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.rst_wmr_protect"; | |
3894 | input scan_en PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.scan_en"; | |
3895 | input scan_in PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.scan_in"; | |
3896 | input scan_out PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.scan_out"; | |
3897 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.slow_cmp_sync_en"; | |
3898 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.tcu_aclk"; | |
3899 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.tcu_atpg_mode"; | |
3900 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.tcu_bclk"; | |
3901 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.tcu_clk_stop"; | |
3902 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.tcu_div_bypass"; | |
3903 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.tcu_pce_ov"; | |
3904 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.tcu_wr_inhibit"; | |
3905 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.wmr_"; | |
3906 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.wmr_protect"; | |
3907 | } | |
3908 | ||
3909 | interface clkgen_spc1_cmp_l2clk_if { | |
3910 | input l2clk CLOCK verilog_node "`CPU.spc1.clk_spc.l2clk"; // Vera interface clock | |
3911 | ||
3912 | input aclk PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.aclk"; | |
3913 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.aclk_wmr"; | |
3914 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.array_wr_inhibit"; | |
3915 | input bclk PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.bclk"; | |
3916 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.cmp_slow_sync_en"; | |
3917 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.pce_ov"; | |
3918 | input por_ PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.por_"; | |
3919 | input scan_out PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.scan_out"; | |
3920 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.slow_cmp_sync_en"; | |
3921 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.wmr_"; | |
3922 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.wmr_protect"; | |
3923 | } | |
3924 | ||
3925 | #endif | |
3926 | ||
3927 | //----- VERA interfaces for clkgen_spc2_cmp ----- | |
3928 | ||
3929 | #ifndef RTL_NO_SPC2 | |
3930 | ||
3931 | interface clkgen_spc2_cmp_gclk_if { | |
3932 | input gclk CLOCK verilog_node "`CPU.spc2.clk_spc.gclk"; // Vera interface clock | |
3933 | ||
3934 | input aclk PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.aclk"; | |
3935 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.aclk_wmr"; | |
3936 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.array_wr_inhibit"; | |
3937 | input bclk PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.bclk"; | |
3938 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.ccu_cmp_slow_sync_en"; | |
3939 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.ccu_div_ph"; | |
3940 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.ccu_serdes_dtm"; | |
3941 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.ccu_slow_cmp_sync_en"; | |
3942 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.clk_ext"; | |
3943 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.cluster_arst_l"; | |
3944 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.cluster_div_en"; | |
3945 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.cmp_slow_sync_en"; | |
3946 | input l2clk PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.l2clk"; | |
3947 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.pce_ov"; | |
3948 | input por_ PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.por_"; | |
3949 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.rst_por_"; | |
3950 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.rst_wmr_"; | |
3951 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.rst_wmr_protect"; | |
3952 | input scan_en PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.scan_en"; | |
3953 | input scan_in PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.scan_in"; | |
3954 | input scan_out PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.scan_out"; | |
3955 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.slow_cmp_sync_en"; | |
3956 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.tcu_aclk"; | |
3957 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.tcu_atpg_mode"; | |
3958 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.tcu_bclk"; | |
3959 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.tcu_clk_stop"; | |
3960 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.tcu_div_bypass"; | |
3961 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.tcu_pce_ov"; | |
3962 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.tcu_wr_inhibit"; | |
3963 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.wmr_"; | |
3964 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.wmr_protect"; | |
3965 | } | |
3966 | ||
3967 | interface clkgen_spc2_cmp_l2clk_if { | |
3968 | input l2clk CLOCK verilog_node "`CPU.spc2.clk_spc.l2clk"; // Vera interface clock | |
3969 | ||
3970 | input aclk PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.aclk"; | |
3971 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.aclk_wmr"; | |
3972 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.array_wr_inhibit"; | |
3973 | input bclk PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.bclk"; | |
3974 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.cmp_slow_sync_en"; | |
3975 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.pce_ov"; | |
3976 | input por_ PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.por_"; | |
3977 | input scan_out PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.scan_out"; | |
3978 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.slow_cmp_sync_en"; | |
3979 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.wmr_"; | |
3980 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.wmr_protect"; | |
3981 | } | |
3982 | ||
3983 | #endif | |
3984 | ||
3985 | //----- VERA interfaces for clkgen_spc3_cmp ----- | |
3986 | ||
3987 | #ifndef RTL_NO_SPC3 | |
3988 | ||
3989 | interface clkgen_spc3_cmp_gclk_if { | |
3990 | input gclk CLOCK verilog_node "`CPU.spc3.clk_spc.gclk"; // Vera interface clock | |
3991 | ||
3992 | input aclk PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.aclk"; | |
3993 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.aclk_wmr"; | |
3994 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.array_wr_inhibit"; | |
3995 | input bclk PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.bclk"; | |
3996 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.ccu_cmp_slow_sync_en"; | |
3997 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.ccu_div_ph"; | |
3998 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.ccu_serdes_dtm"; | |
3999 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.ccu_slow_cmp_sync_en"; | |
4000 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.clk_ext"; | |
4001 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.cluster_arst_l"; | |
4002 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.cluster_div_en"; | |
4003 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.cmp_slow_sync_en"; | |
4004 | input l2clk PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.l2clk"; | |
4005 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.pce_ov"; | |
4006 | input por_ PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.por_"; | |
4007 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.rst_por_"; | |
4008 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.rst_wmr_"; | |
4009 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.rst_wmr_protect"; | |
4010 | input scan_en PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.scan_en"; | |
4011 | input scan_in PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.scan_in"; | |
4012 | input scan_out PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.scan_out"; | |
4013 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.slow_cmp_sync_en"; | |
4014 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.tcu_aclk"; | |
4015 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.tcu_atpg_mode"; | |
4016 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.tcu_bclk"; | |
4017 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.tcu_clk_stop"; | |
4018 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.tcu_div_bypass"; | |
4019 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.tcu_pce_ov"; | |
4020 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.tcu_wr_inhibit"; | |
4021 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.wmr_"; | |
4022 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.wmr_protect"; | |
4023 | } | |
4024 | ||
4025 | interface clkgen_spc3_cmp_l2clk_if { | |
4026 | input l2clk CLOCK verilog_node "`CPU.spc3.clk_spc.l2clk"; // Vera interface clock | |
4027 | ||
4028 | input aclk PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.aclk"; | |
4029 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.aclk_wmr"; | |
4030 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.array_wr_inhibit"; | |
4031 | input bclk PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.bclk"; | |
4032 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.cmp_slow_sync_en"; | |
4033 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.pce_ov"; | |
4034 | input por_ PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.por_"; | |
4035 | input scan_out PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.scan_out"; | |
4036 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.slow_cmp_sync_en"; | |
4037 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.wmr_"; | |
4038 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.wmr_protect"; | |
4039 | } | |
4040 | ||
4041 | #endif | |
4042 | ||
4043 | //----- VERA interfaces for clkgen_spc4_cmp ----- | |
4044 | ||
4045 | #ifndef RTL_NO_SPC4 | |
4046 | ||
4047 | interface clkgen_spc4_cmp_gclk_if { | |
4048 | input gclk CLOCK verilog_node "`CPU.spc4.clk_spc.gclk"; // Vera interface clock | |
4049 | ||
4050 | input aclk PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.aclk"; | |
4051 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.aclk_wmr"; | |
4052 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.array_wr_inhibit"; | |
4053 | input bclk PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.bclk"; | |
4054 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.ccu_cmp_slow_sync_en"; | |
4055 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.ccu_div_ph"; | |
4056 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.ccu_serdes_dtm"; | |
4057 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.ccu_slow_cmp_sync_en"; | |
4058 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.clk_ext"; | |
4059 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.cluster_arst_l"; | |
4060 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.cluster_div_en"; | |
4061 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.cmp_slow_sync_en"; | |
4062 | input l2clk PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.l2clk"; | |
4063 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.pce_ov"; | |
4064 | input por_ PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.por_"; | |
4065 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.rst_por_"; | |
4066 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.rst_wmr_"; | |
4067 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.rst_wmr_protect"; | |
4068 | input scan_en PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.scan_en"; | |
4069 | input scan_in PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.scan_in"; | |
4070 | input scan_out PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.scan_out"; | |
4071 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.slow_cmp_sync_en"; | |
4072 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.tcu_aclk"; | |
4073 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.tcu_atpg_mode"; | |
4074 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.tcu_bclk"; | |
4075 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.tcu_clk_stop"; | |
4076 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.tcu_div_bypass"; | |
4077 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.tcu_pce_ov"; | |
4078 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.tcu_wr_inhibit"; | |
4079 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.wmr_"; | |
4080 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.wmr_protect"; | |
4081 | } | |
4082 | ||
4083 | interface clkgen_spc4_cmp_l2clk_if { | |
4084 | input l2clk CLOCK verilog_node "`CPU.spc4.clk_spc.l2clk"; // Vera interface clock | |
4085 | ||
4086 | input aclk PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.aclk"; | |
4087 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.aclk_wmr"; | |
4088 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.array_wr_inhibit"; | |
4089 | input bclk PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.bclk"; | |
4090 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.cmp_slow_sync_en"; | |
4091 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.pce_ov"; | |
4092 | input por_ PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.por_"; | |
4093 | input scan_out PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.scan_out"; | |
4094 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.slow_cmp_sync_en"; | |
4095 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.wmr_"; | |
4096 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.wmr_protect"; | |
4097 | } | |
4098 | ||
4099 | #endif | |
4100 | ||
4101 | //----- VERA interfaces for clkgen_spc5_cmp ----- | |
4102 | ||
4103 | #ifndef RTL_NO_SPC5 | |
4104 | ||
4105 | interface clkgen_spc5_cmp_gclk_if { | |
4106 | input gclk CLOCK verilog_node "`CPU.spc5.clk_spc.gclk"; // Vera interface clock | |
4107 | ||
4108 | input aclk PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.aclk"; | |
4109 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.aclk_wmr"; | |
4110 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.array_wr_inhibit"; | |
4111 | input bclk PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.bclk"; | |
4112 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.ccu_cmp_slow_sync_en"; | |
4113 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.ccu_div_ph"; | |
4114 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.ccu_serdes_dtm"; | |
4115 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.ccu_slow_cmp_sync_en"; | |
4116 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.clk_ext"; | |
4117 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.cluster_arst_l"; | |
4118 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.cluster_div_en"; | |
4119 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.cmp_slow_sync_en"; | |
4120 | input l2clk PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.l2clk"; | |
4121 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.pce_ov"; | |
4122 | input por_ PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.por_"; | |
4123 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.rst_por_"; | |
4124 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.rst_wmr_"; | |
4125 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.rst_wmr_protect"; | |
4126 | input scan_en PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.scan_en"; | |
4127 | input scan_in PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.scan_in"; | |
4128 | input scan_out PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.scan_out"; | |
4129 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.slow_cmp_sync_en"; | |
4130 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.tcu_aclk"; | |
4131 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.tcu_atpg_mode"; | |
4132 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.tcu_bclk"; | |
4133 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.tcu_clk_stop"; | |
4134 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.tcu_div_bypass"; | |
4135 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.tcu_pce_ov"; | |
4136 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.tcu_wr_inhibit"; | |
4137 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.wmr_"; | |
4138 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.wmr_protect"; | |
4139 | } | |
4140 | ||
4141 | interface clkgen_spc5_cmp_l2clk_if { | |
4142 | input l2clk CLOCK verilog_node "`CPU.spc5.clk_spc.l2clk"; // Vera interface clock | |
4143 | ||
4144 | input aclk PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.aclk"; | |
4145 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.aclk_wmr"; | |
4146 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.array_wr_inhibit"; | |
4147 | input bclk PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.bclk"; | |
4148 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.cmp_slow_sync_en"; | |
4149 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.pce_ov"; | |
4150 | input por_ PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.por_"; | |
4151 | input scan_out PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.scan_out"; | |
4152 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.slow_cmp_sync_en"; | |
4153 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.wmr_"; | |
4154 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.wmr_protect"; | |
4155 | } | |
4156 | ||
4157 | #endif | |
4158 | ||
4159 | //----- VERA interfaces for clkgen_spc6_cmp ----- | |
4160 | ||
4161 | #ifndef RTL_NO_SPC6 | |
4162 | ||
4163 | interface clkgen_spc6_cmp_gclk_if { | |
4164 | input gclk CLOCK verilog_node "`CPU.spc6.clk_spc.gclk"; // Vera interface clock | |
4165 | ||
4166 | input aclk PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.aclk"; | |
4167 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.aclk_wmr"; | |
4168 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.array_wr_inhibit"; | |
4169 | input bclk PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.bclk"; | |
4170 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.ccu_cmp_slow_sync_en"; | |
4171 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.ccu_div_ph"; | |
4172 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.ccu_serdes_dtm"; | |
4173 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.ccu_slow_cmp_sync_en"; | |
4174 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.clk_ext"; | |
4175 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.cluster_arst_l"; | |
4176 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.cluster_div_en"; | |
4177 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.cmp_slow_sync_en"; | |
4178 | input l2clk PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.l2clk"; | |
4179 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.pce_ov"; | |
4180 | input por_ PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.por_"; | |
4181 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.rst_por_"; | |
4182 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.rst_wmr_"; | |
4183 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.rst_wmr_protect"; | |
4184 | input scan_en PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.scan_en"; | |
4185 | input scan_in PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.scan_in"; | |
4186 | input scan_out PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.scan_out"; | |
4187 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.slow_cmp_sync_en"; | |
4188 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.tcu_aclk"; | |
4189 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.tcu_atpg_mode"; | |
4190 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.tcu_bclk"; | |
4191 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.tcu_clk_stop"; | |
4192 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.tcu_div_bypass"; | |
4193 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.tcu_pce_ov"; | |
4194 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.tcu_wr_inhibit"; | |
4195 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.wmr_"; | |
4196 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.wmr_protect"; | |
4197 | } | |
4198 | ||
4199 | interface clkgen_spc6_cmp_l2clk_if { | |
4200 | input l2clk CLOCK verilog_node "`CPU.spc6.clk_spc.l2clk"; // Vera interface clock | |
4201 | ||
4202 | input aclk PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.aclk"; | |
4203 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.aclk_wmr"; | |
4204 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.array_wr_inhibit"; | |
4205 | input bclk PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.bclk"; | |
4206 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.cmp_slow_sync_en"; | |
4207 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.pce_ov"; | |
4208 | input por_ PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.por_"; | |
4209 | input scan_out PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.scan_out"; | |
4210 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.slow_cmp_sync_en"; | |
4211 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.wmr_"; | |
4212 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.wmr_protect"; | |
4213 | } | |
4214 | ||
4215 | #endif | |
4216 | ||
4217 | //----- VERA interfaces for clkgen_spc7_cmp ----- | |
4218 | ||
4219 | #ifndef RTL_NO_SPC7 | |
4220 | ||
4221 | interface clkgen_spc7_cmp_gclk_if { | |
4222 | input gclk CLOCK verilog_node "`CPU.spc7.clk_spc.gclk"; // Vera interface clock | |
4223 | ||
4224 | input aclk PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.aclk"; | |
4225 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.aclk_wmr"; | |
4226 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.array_wr_inhibit"; | |
4227 | input bclk PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.bclk"; | |
4228 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.ccu_cmp_slow_sync_en"; | |
4229 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.ccu_div_ph"; | |
4230 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.ccu_serdes_dtm"; | |
4231 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.ccu_slow_cmp_sync_en"; | |
4232 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.clk_ext"; | |
4233 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.cluster_arst_l"; | |
4234 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.cluster_div_en"; | |
4235 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.cmp_slow_sync_en"; | |
4236 | input l2clk PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.l2clk"; | |
4237 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.pce_ov"; | |
4238 | input por_ PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.por_"; | |
4239 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.rst_por_"; | |
4240 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.rst_wmr_"; | |
4241 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.rst_wmr_protect"; | |
4242 | input scan_en PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.scan_en"; | |
4243 | input scan_in PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.scan_in"; | |
4244 | input scan_out PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.scan_out"; | |
4245 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.slow_cmp_sync_en"; | |
4246 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.tcu_aclk"; | |
4247 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.tcu_atpg_mode"; | |
4248 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.tcu_bclk"; | |
4249 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.tcu_clk_stop"; | |
4250 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.tcu_div_bypass"; | |
4251 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.tcu_pce_ov"; | |
4252 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.tcu_wr_inhibit"; | |
4253 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.wmr_"; | |
4254 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.wmr_protect"; | |
4255 | } | |
4256 | ||
4257 | interface clkgen_spc7_cmp_l2clk_if { | |
4258 | input l2clk CLOCK verilog_node "`CPU.spc7.clk_spc.l2clk"; // Vera interface clock | |
4259 | ||
4260 | input aclk PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.aclk"; | |
4261 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.aclk_wmr"; | |
4262 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.array_wr_inhibit"; | |
4263 | input bclk PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.bclk"; | |
4264 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.cmp_slow_sync_en"; | |
4265 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.pce_ov"; | |
4266 | input por_ PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.por_"; | |
4267 | input scan_out PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.scan_out"; | |
4268 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.slow_cmp_sync_en"; | |
4269 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.wmr_"; | |
4270 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.wmr_protect"; | |
4271 | } | |
4272 | ||
4273 | #endif | |
4274 | ||
4275 | #ifndef FC_NO_NIU_T2 | |
4276 | #ifndef NIU_SYSTEMC_T2 | |
4277 | //----- VERA interfaces for clkgen_tds_io ----- | |
4278 | ||
4279 | interface clkgen_tds_io_gclk_if { | |
4280 | input gclk CLOCK verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.gclk"; // Vera interface clock | |
4281 | ||
4282 | input aclk PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.aclk"; | |
4283 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.aclk_wmr"; | |
4284 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.array_wr_inhibit"; | |
4285 | input bclk PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.bclk"; | |
4286 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.ccu_cmp_slow_sync_en"; | |
4287 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.ccu_div_ph"; | |
4288 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.ccu_serdes_dtm"; | |
4289 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.ccu_slow_cmp_sync_en"; | |
4290 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.clk_ext"; | |
4291 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.cluster_arst_l"; | |
4292 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.cluster_div_en"; | |
4293 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.cmp_slow_sync_en"; | |
4294 | input l2clk PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.l2clk"; | |
4295 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.pce_ov"; | |
4296 | input por_ PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.por_"; | |
4297 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.rst_por_"; | |
4298 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.rst_wmr_"; | |
4299 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.rst_wmr_protect"; | |
4300 | input scan_en PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.scan_en"; | |
4301 | input scan_in PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.scan_in"; | |
4302 | input scan_out PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.scan_out"; | |
4303 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.slow_cmp_sync_en"; | |
4304 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.tcu_aclk"; | |
4305 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.tcu_atpg_mode"; | |
4306 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.tcu_bclk"; | |
4307 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.tcu_clk_stop"; | |
4308 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.tcu_div_bypass"; | |
4309 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.tcu_pce_ov"; | |
4310 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.tcu_wr_inhibit"; | |
4311 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.wmr_"; | |
4312 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.wmr_protect"; | |
4313 | } | |
4314 | ||
4315 | interface clkgen_tds_io_l2clk_if { | |
4316 | input l2clk CLOCK verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.l2clk"; // Vera interface clock | |
4317 | ||
4318 | input aclk PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.aclk"; | |
4319 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.aclk_wmr"; | |
4320 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.array_wr_inhibit"; | |
4321 | input bclk PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.bclk"; | |
4322 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.cmp_slow_sync_en"; | |
4323 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.pce_ov"; | |
4324 | input por_ PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.por_"; | |
4325 | input scan_out PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.scan_out"; | |
4326 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.slow_cmp_sync_en"; | |
4327 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.wmr_"; | |
4328 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.wmr_protect"; | |
4329 | } | |
4330 | ||
4331 | //----- VERA interfaces for clkgen_tds_io2x ----- | |
4332 | ||
4333 | interface clkgen_tds_io2x_gclk_if { | |
4334 | input gclk CLOCK verilog_node "`CPU.tds.clkgen2x_tds.gclk"; // Vera interface clock | |
4335 | ||
4336 | input aclk PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.aclk"; | |
4337 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.aclk_wmr"; | |
4338 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.array_wr_inhibit"; | |
4339 | input bclk PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.bclk"; | |
4340 | input ccu_cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.ccu_cmp_slow_sync_en"; | |
4341 | input ccu_div_ph PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.ccu_div_ph"; | |
4342 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.ccu_serdes_dtm"; | |
4343 | input ccu_slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.ccu_slow_cmp_sync_en"; | |
4344 | input clk_ext PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.clk_ext"; | |
4345 | input cluster_arst_l PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.cluster_arst_l"; | |
4346 | input cluster_div_en PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.cluster_div_en"; | |
4347 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.cmp_slow_sync_en"; | |
4348 | input l2clk PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.l2clk"; | |
4349 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.pce_ov"; | |
4350 | input por_ PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.por_"; | |
4351 | input rst_por_ PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.rst_por_"; | |
4352 | input rst_wmr_ PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.rst_wmr_"; | |
4353 | input rst_wmr_protect PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.rst_wmr_protect"; | |
4354 | input scan_en PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.scan_en"; | |
4355 | input scan_in PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.scan_in"; | |
4356 | input scan_out PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.scan_out"; | |
4357 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.slow_cmp_sync_en"; | |
4358 | input tcu_aclk PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.tcu_aclk"; | |
4359 | input tcu_atpg_mode PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.tcu_atpg_mode"; | |
4360 | input tcu_bclk PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.tcu_bclk"; | |
4361 | input tcu_clk_stop PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.tcu_clk_stop"; | |
4362 | input tcu_div_bypass PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.tcu_div_bypass"; | |
4363 | input tcu_pce_ov PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.tcu_pce_ov"; | |
4364 | input tcu_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.tcu_wr_inhibit"; | |
4365 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.wmr_"; | |
4366 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.wmr_protect"; | |
4367 | } | |
4368 | ||
4369 | interface clkgen_tds_io2x_l2clk_if { | |
4370 | input l2clk CLOCK verilog_node "`CPU.tds.clkgen2x_tds.l2clk"; // Vera interface clock | |
4371 | ||
4372 | input aclk PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.aclk"; | |
4373 | input aclk_wmr PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.aclk_wmr"; | |
4374 | input array_wr_inhibit PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.array_wr_inhibit"; | |
4375 | input bclk PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.bclk"; | |
4376 | input cmp_slow_sync_en PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.cmp_slow_sync_en"; | |
4377 | input pce_ov PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.pce_ov"; | |
4378 | input por_ PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.por_"; | |
4379 | input scan_out PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.scan_out"; | |
4380 | input slow_cmp_sync_en PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.slow_cmp_sync_en"; | |
4381 | input wmr_ PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.wmr_"; | |
4382 | input wmr_protect PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.wmr_protect"; | |
4383 | } | |
4384 | #endif | |
4385 | #endif | |
4386 | ||
4387 | #endif // #ifdef FC_BENCH | |
4388 | #endif // #ifndef INC_CLUSTER_HDR_IF_VRI |