projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: ncu_defines.vri | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | #ifndef INC_NCU_DEFINES_VRI | |
| 36 | #define INC_NCU_DEFINES_VRI | |
| 37 | ||
| 38 | //------------------ Address Space (MSB 8-bits of Physical Address) --------------------- | |
| 39 | #define NCU_PA 8'h80 | |
| 40 | #define NIU_PA 8'h81 | |
| 41 | // RESERVED 8'h82 | |
| 42 | #define CCU_PA 8'h83 // RNG+CCU | |
| 43 | #define MCU_PA 8'h84 | |
| 44 | // RESERVED 8'h85 | |
| 45 | // RESERVED 8'h86 | |
| 46 | // RESERVED 8'h87 | |
| 47 | #define DMU_PA 8'h88 | |
| 48 | #define RST_PA 8'h89 | |
| 49 | #define ASI_PA 8'h90 // CPU Shared Registers | |
| 50 | #define SSI_PA 8'hff // Boot ROM | |
| 51 | ||
| 52 | //------------------ NCU Access Field --------------------- | |
| 53 | #define NCU_CSR 16'h0000 | |
| 54 | #define NCU_ASI_CMP 16'h0104 // Multi-core access via ASI | |
| 55 | #define NCU_ASI_INT 16'h01cc // Interrupt access via ASI | |
| 56 | #define NCU_ASI_RST 16'h0000 | |
| 57 | #define NCU_ASI_CCU 16'h0000 | |
| 58 | ||
| 59 | //------------------ NCU ASI registers (from NCU) --------------------- | |
| 60 | #define NCU_ASI_CORE_AVAILABLE 16'h0000 | |
| 61 | #define NCU_ASI_CORE_ENABLE_STATUS 16'h0010 // CMP spec calls this ASI_CORE_ENABLED | |
| 62 | #define NCU_ASI_CORE_ENABLE 16'h0020 | |
| 63 | #define NCU_ASI_XIR_STEERING 16'h0030 | |
| 64 | #define NCU_ASI_CORE_RUNNING_RW 16'h0050 | |
| 65 | #define NCU_ASI_CORE_RUNNING_STATUS 16'h0058 | |
| 66 | #define NCU_ASI_CORE_RUNNING_W1S 16'h0060 | |
| 67 | #define NCU_ASI_CORE_RUNNING_W1C 16'h0068 | |
| 68 | #define NCU_ASI_INT_VEC_DISP 16'h0800 // Design intends to support interrupt via TAP | |
| 69 | ||
| 70 | //------------------ Local NCU CSR (from NCU) --------------------- | |
| 71 | #define NCU_CSR_INT_MAN 16'h0000 | |
| 72 | #define NCU_CSR_MONDO_INT_VEC 16'h0a00 | |
| 73 | #define NCU_CSR_SER_NUM 16'h1000 | |
| 74 | #define NCU_CSR_EFU_STAT 16'h1008 | |
| 75 | #define NCU_CSR_CORE_AVAIL 16'h1010 | |
| 76 | #define NCU_CSR_BANK_AVAIL 16'h1018 | |
| 77 | #define NCU_CSR_BANK_ENABLE 16'h1020 | |
| 78 | #define NCU_CSR_BANK_ENABLE_STATUS 16'h1028 | |
| 79 | #define NCU_CSR_L2_IDX_HASH_EN 16'h1030 | |
| 80 | #define NCU_CSR_L2_IDX_HASH_EN_STATUS 16'h1038 | |
| 81 | ||
| 82 | //------------------ NCU Addresses --------------------- | |
| 83 | #define NCU_INT_MAN_REG {NCU_PA,NCU_CSR,NCU_CSR_INT_MAN} | |
| 84 | #define NCU_MONDO_INT_VEC_REG {NCU_PA,NCU_CSR,NCU_CSR_MONDO_INT_VEC} | |
| 85 | #define NCU_SER_NUM_REG {NCU_PA,NCU_CSR,NCU_CSR_SER_NUM} | |
| 86 | #define NCU_EFU_STAT_REG {NCU_PA,NCU_CSR,NCU_CSR_EFU_STAT} | |
| 87 | #define NCU_CORE_AVAIL_REG {NCU_PA,NCU_CSR,NCU_CSR_CORE_AVAIL} | |
| 88 | #define NCU_BANK_AVAIL_REG {NCU_PA,NCU_CSR,NCU_CSR_BANK_AVAIL} | |
| 89 | #define NCU_BANK_ENABLE_REG {NCU_PA,NCU_CSR,NCU_CSR_BANK_ENABLE} | |
| 90 | #define NCU_BANK_ENABLE_STATUS_REG {NCU_PA,NCU_CSR,NCU_CSR_BANK_ENABLE_STATUS} | |
| 91 | #define NCU_L2_IDX_HASH_EN_REG {NCU_PA,NCU_CSR,NCU_CSR_L2_IDX_HASH_EN} | |
| 92 | #define NCU_L2_IDX_HASH_EN_STATUS_REG {NCU_PA,NCU_CSR,NCU_CSR_L2_IDX_HASH_EN_STATUS} | |
| 93 | #define NCU_ASI_CORE_AVAILABLE_REG {ASI_PA,NCU_ASI_CMP,NCU_ASI_CORE_AVAILABLE} | |
| 94 | #define NCU_ASI_CORE_ENABLE_STATUS_REG {ASI_PA,NCU_ASI_CMP,NCU_ASI_CORE_ENABLE_STATUS} | |
| 95 | #define NCU_ASI_CORE_ENABLE_REG {ASI_PA,NCU_ASI_CMP,NCU_ASI_CORE_ENABLE} | |
| 96 | #define NCU_ASI_XIR_STEERING_REG {ASI_PA,NCU_ASI_CMP,NCU_ASI_XIR_STEERING} | |
| 97 | #define NCU_ASI_CORE_RUNNING_RW_REG {ASI_PA,NCU_ASI_CMP,NCU_ASI_CORE_RUNNING_RW} | |
| 98 | #define NCU_ASI_CORE_RUNNING_STATUS_REG {ASI_PA,NCU_ASI_CMP,NCU_ASI_CORE_RUNNING_STATUS} | |
| 99 | #define NCU_ASI_CORE_RUNNING_W1S_REG {ASI_PA,NCU_ASI_CMP,NCU_ASI_CORE_RUNNING_W1S} | |
| 100 | #define NCU_ASI_CORE_RUNNING_W1C_REG {ASI_PA,NCU_ASI_CMP,NCU_ASI_CORE_RUNNING_W1C} | |
| 101 | #define NCU_ASI_INT_VEC_DISP_REG {ASI_PA,NCU_ASI_INT,NCU_ASI_INT_VEC_DISP} | |
| 102 | ||
| 103 | #endif INC_NCU_DEFINES_VRI |