projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: rst_defines.vri | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | #ifndef INC_RST_DEFINES_VRI | |
| 36 | #define INC_RST_DEFINES_VRI | |
| 37 | ||
| 38 | #include "ncu_defines.vri" | |
| 39 | ||
| 40 | //------------------ RST ASI Registers --------------------- | |
| 41 | #define RST_ASI_RESET_GEN 16'h0808 | |
| 42 | #define RST_ASI_RESET_STAT 16'h0810 | |
| 43 | #define RST_ASI_RESET_SOURCE 16'h0818 // N2 PRM 08/11/2004 | |
| 44 | #define RST_ASI_RESET_SSYS 16'h0838 | |
| 45 | #define RST_ASI_LOCK_TIME 16'h0870 | |
| 46 | #define RST_ASI_PROP_TIME 16'h0880 // Added as per changed RST spec 1.06 | |
| 47 | #define RST_ASI_NIU_TIME 16'h0890 | |
| 48 | #define RST_ASI_CCU_TIME 16'h0860 | |
| 49 | #define RST_ASI_RESET_FEE 16'h0820 // Added as per changed RST spec 1.14 | |
| 50 | ||
| 51 | //------------------ RST Addresses --------------------- | |
| 52 | #define RST_ASI_RESET_GEN_REG {RST_PA,NCU_ASI_RST,RST_ASI_RESET_GEN} | |
| 53 | #define RST_ASI_RESET_STAT_REG {RST_PA,NCU_ASI_RST,RST_ASI_RESET_STAT} | |
| 54 | #define RST_ASI_RESET_SOURCE_REG {RST_PA,NCU_ASI_RST,RST_ASI_RESET_SOURCE} | |
| 55 | #define RST_ASI_RESET_SSYS_REG {RST_PA,NCU_ASI_RST,RST_ASI_RESET_SSYS} | |
| 56 | #define RST_ASI_LOCK_TIME_REG {RST_PA,NCU_ASI_RST,RST_ASI_LOCK_TIME} | |
| 57 | #define RST_ASI_NIU_TIME_REG {RST_PA,NCU_ASI_RST,RST_ASI_NIU_TIME} | |
| 58 | #define RST_ASI_CCU_TIME_REG {RST_PA,NCU_ASI_RST,RST_ASI_CCU_TIME} | |
| 59 | #define RST_ASI_PROP_TIME_REG {RST_PA,NCU_ASI_RST,RST_ASI_PROP_TIME} // Added as per changed RST spec 1.06 | |
| 60 | #define RST_ASI_RESET_FEE_REG {RST_PA,NCU_ASI_RST,RST_ASI_RESET_FEE} // Added as per changed RST spec 1.14 | |
| 61 | ||
| 62 | //------------------ Deterministic reset wait times --------------------- | |
| 63 | #define RST_LOCK_INITIAL 16'd5120 // Test files use this (RST spec v0.9) | |
| 64 | #define RST_LOCK_COLD 0 | |
| 65 | #define RST_LOCK_WARM 1 | |
| 66 | #define RST_LOCK_ATTRIB_COUNT 2 | |
| 67 | #define RST_LOCK_POR_TCU 0 // Allow scan enable to reach destination | |
| 68 | #define RST_LOCK_BIST_TCU 1 | |
| 69 | #define RST_LOCK_BIST_RST 2 // Allow scan enable to reach destination | |
| 70 | #define RST_LOCK_ATTRIB_FIELD_COUNT 3 | |
| 71 | #define RST_LOCK { { 16, 1, 1 }, { 1 , 1 , 1 } } | |
| 72 | // Cold Warm | |
| 73 | // Reset lock warm, the POR 07/22 is to make these all the same | |
| 74 | // Reset lock cold, the POR 07/22 is to make these all the same | |
| 75 | ||
| 76 | //------------------ Knob and testbench wait times --------------------- | |
| 77 | // @@UPDATE@@ Need to update for N2 | |
| 78 | #define PLL_RST_CNT_NORM 128 | |
| 79 | #define PLL_RST_CNT_FAST 32 | |
| 80 | #define PLL_RST_NS_NORM 500 | |
| 81 | #define PLL_LCK_CNT_NORM 31488 | |
| 82 | #define PLL_LCK_CNT_FAST 256 | |
| 83 | #define PLL_LCK_NS_NORM 25000 | |
| 84 | #define EFC_READ_CNT_NORM 8000 | |
| 85 | #define EFC_READ_CNT_FAST 200 | |
| 86 | #define EFC_READ_NS_NORM 40000 | |
| 87 | #define TRST_SETUP_CMP_CYCLES 16 | |
| 88 | #define PLL_RST_NS_FAST (PLL_RST_NS_NORM / (PLL_RST_CNT_NORM / PLL_RST_CNT_FAST) ) | |
| 89 | #define PLL_LCK_NS_FAST (PLL_LCK_NS_NORM / (PLL_LCK_CNT_NORM / PLL_LCK_CNT_FAST) ) | |
| 90 | #define EFC_READ_NS_FAST (EFC_READ_NS_NORM / (EFC_READ_CNT_NORM / EFC_READ_CNT_FAST)) | |
| 91 | ||
| 92 | #define NORM_PLL_RST_R_CNT 128 | |
| 93 | #define FAST_PLL_RST_R_CNT 32 | |
| 94 | #define NORM_PLL_LCK_R_CNT 31488 | |
| 95 | #define FAST_PLL_LCK_R_CNT 256 | |
| 96 | #define NORM_PLL_BYP_R_CNT 16 | |
| 97 | #define FAST_PLL_BYP_R_CNT 16 | |
| 98 | #define NORM_PLL_LCK_SEQ_R_CNT 32000 | |
| 99 | #define NORM_PLL_BYP_SEQ_R_CNT 256 | |
| 100 | #define NORM_WRM_RST_R_CNT 2000 | |
| 101 | #define FAST_WRM_RST_R_CNT 128 | |
| 102 | #define NORM_TST_RST_R_CNT 256 | |
| 103 | #define FAST_TST_RST_R_CNT 64 | |
| 104 | #define NORM_DRM_RST_J_CNT 1600 | |
| 105 | #define FAST_DRM_RST_J_CNT 100 | |
| 106 | #define CKEN_C_CNT 4000 | |
| 107 | #define NORM_PLL_RST_LCK_R_CNT (NORM_PLL_RST_R_CNT+NORM_PLL_LCK_R_CNT) | |
| 108 | #define FAST_PLL_RST_LCK_R_CNT (FAST_PLL_RST_R_CNT+FAST_PLL_LCK_R_CNT) | |
| 109 | #define NORM_PLL_RST_BYP_R_CNT (NORM_PLL_RST_R_CNT+NORM_PLL_BYP_R_CNT) | |
| 110 | #define FAST_PLL_RST_BYP_R_CNT (FAST_PLL_RST_R_CNT+FAST_PLL_BYP_R_CNT) | |
| 111 | #define FAST_PLL_LCK_SEQ_R_CNT (NORM_PLL_LCK_SEQ_R_CNT-NORM_PLL_RST_LCK_R_CNT+FAST_PLL_RST_LCK_R_CNT ) | |
| 112 | #define FAST_PLL_BYP_SEQ_R_CNT (NORM_PLL_BYP_SEQ_R_CNT-NORM_PLL_RST_BYP_R_CNT+FAST_PLL_RST_BYP_R_CNT) | |
| 113 | ||
| 114 | #ifdef TCU_SAT | |
| 115 | #define TEST_RST_SEQUENCE_TIME 36000 // Used for timeout calculation | |
| 116 | #else | |
| 117 | #define TEST_RST_SEQUENCE_TIME 36000000 // Used for timeout calculation for FC_SCAN bench | |
| 118 | #endif //#ifdef TCU_SAT | |
| 119 | ||
| 120 | //------------------ Reset state machine --------------------- | |
| 121 | #define FLUSH_POR_1 12'h001 | |
| 122 | #define DEASSERT_SE_1 12'h002 | |
| 123 | #define DEASSERT_SE_PROP_1 12'h004 | |
| 124 | #define DEASSERT_CLOCK_STOP 12'h008 | |
| 125 | #define EFU_RUN_1 12'h010 | |
| 126 | #define REASSERT_CLOCK_STOP_1 12'h020 | |
| 127 | #define BISI_RUN_1 12'h040 | |
| 128 | #define FLUSH_POR_2 12'h080 | |
| 129 | #define DEASSERT_SE_PROP_2 12'h100 | |
| 130 | #define EFU_RUN_2 12'h200 | |
| 131 | #define REASSERT_CLOCK_STOP_2 12'h400 | |
| 132 | #define POR_UNPARK_THREAD 12'h800 | |
| 133 | ||
| 134 | // N1 #define PLL_SM_WAIT_POR 0 | |
| 135 | // N1 #define PLL_SM_RST_PLL 1 | |
| 136 | // N1 #define PLL_SM_WAIT_PLL_LCK 2 | |
| 137 | // N1 #define PLL_SM_PLL_LCK 3 | |
| 138 | // N1 #define CTL_SM_WAIT_LCK 0 | |
| 139 | // N1 #define CTL_SM_STR_CLK 1 | |
| 140 | // N1 #define CTL_SM_EN_CLK 2 | |
| 141 | // N1 #define CTL_SM_WAIT_J_RST 3 | |
| 142 | // N1 #define CTL_SM_DE_DLLRST 4 | |
| 143 | // N1 #define CTL_SM_DE_GRST 5 | |
| 144 | // N1 #define CTL_SM_EFC_RD 6 | |
| 145 | // N1 #define CTL_SM_WAIT_BISTDN 7 | |
| 146 | // N1 #define CTL_SM_IDLE 8 | |
| 147 | // N1 #define CTL_SM_A_GRST 9 | |
| 148 | // N1 #define CTL_SM_A_DGRST 10 | |
| 149 | // N1 #define CTL_SM_DIS_CLK 11 | |
| 150 | // N1 #define CTL_SM_CHNG_FRQ 12 | |
| 151 | // N1 #define CTL_SM_WAIT_RST 13 | |
| 152 | ||
| 153 | ||
| 154 | //------------------ Reset Source Register --------------------- | |
| 155 | // Modified the bit structure as per RST spec 1.06 | |
| 156 | // --------------------------------------------------------- - - - - - - - | |
| 157 | // 666655555555554444444444333333333322222222221111111111000 0 0 0 0 0 0 0 | |
| 158 | // 321098765432109876543210987654321098765432109876543210987 6 5 4 3 2 1 0 | |
| 159 | // --------------------------------------------------------- - - - - - - - | |
| 160 | #define RST_ASI_RESET_SOURCE_MASK 64'b000000000000000000000000000000000000000000000000_1_1_1_1_1_1_1_1_1_1_1_1_1_0_1_1 | |
| 161 | #define RST_ASI_RESET_SOURCE_DEF 64'b000000000000000000000000000000000000000000000000_0_0_0_0_0_0_0_0_0_0_0_0_1_0_0_0 | |
| 162 | ||
| 163 | //------------------ Reset Generate Register ------------------- | |
| 164 | // Modified the bit structure as per RST spec 1.06 | |
| 165 | // ------------------------------------------------------------- - - - | |
| 166 | // 6666555555555544444444443333333333222222222211111111110000000 0 0 0 | |
| 167 | // 3210987654321098765432109876543210987654321098765432109876543 2 1 0 | |
| 168 | // ------------------------------------------------------------- - - - | |
| 169 | #define RST_ASI_RESET_GEN_MASK 64'b000000000000000000000000000000000000000000000000000000000000_1_1_1_1 | |
| 170 | #define RST_ASI_RESET_GEN_DEF 64'b000000000000000000000000000000000000000000000000000000000000_0_0_0_0 | |
| 171 | ||
| 172 | //------------------ Reset Status Register --------------------- | |
| 173 | // Modified the bit structure as per RST spec 1.06 | |
| 174 | // ---------------------------------------------------- - - - ----- - - - - | |
| 175 | // 6666555555555544444444443333333333222222222211111111 1 1 0 00000 0 0 0 0 | |
| 176 | // 3210987654321098765432109876543210987654321098765432 1 0 9 87654 3 2 1 0 | |
| 177 | // ---------------------------------------------------- - - - ----- - - - - | |
| 178 | #define RST_ASI_RESET_STAT_MASK 64'b0000000000000000000000000000000000000000000000000000_1_1_1_00000_1_1_1_0 | |
| 179 | #define RST_ASI_RESET_STAT_DEF 64'b0000000000000000000000000000000000000000000000000000_0_0_0_00000_0_0_0_0 | |
| 180 | ||
| 181 | //------------------ Reset fatal error enable register ------------------- | |
| 182 | // Modified the bit structure as per RST spec 1.14 | |
| 183 | // ------------------------------------------------------------- - - - | |
| 184 | // 6666555555555544444444443333333333222222222211111111110000000 0 0 0 | |
| 185 | // 3210987654321098765432109876543210987654321098765432109876543 2 1 0 | |
| 186 | // ------------------------------------------------------------- - - - | |
| 187 | #define RST_ASI_RESET_FEE_MASK 64'b000000000000000000000000000000000000000000000000_1_1_1_1_1_1_1_1_0_0_0_0_0_0_0_0 | |
| 188 | #define RST_ASI_RESET_FEE_DEF 64'b000000000000000000000000000000000000000000000000_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0 | |
| 189 | ||
| 190 | ||
| 191 | ||
| 192 | #define RST_ASI_RESET_STAT_FREQ_S 11 | |
| 193 | #define RST_ASI_RESET_STAT_POR_S 10 | |
| 194 | #define RST_ASI_RESET_STAT_WMR_S 9 | |
| 195 | #define RST_ASI_RESET_STAT_FREQ 3 | |
| 196 | #define RST_ASI_RESET_STAT_POR 2 | |
| 197 | #define RST_ASI_RESET_STAT_WMR 1 | |
| 198 | ||
| 199 | ||
| 200 | //------------------ Reset Subsystem Register --------------------- | |
| 201 | // Modified the bit structure as per RST spec 1.06 | |
| 202 | // -------------------------------------------------------------- - - | |
| 203 | // 66665555555555444444444433333333332222222222111111111100000000 0 0 | |
| 204 | // 32109876543210987654321098765432109876543210987654321098765432 1 0 | |
| 205 | // -------------------------------------------------------------- - - | |
| 206 | #define RST_ASI_RESET_SSYS_MASK 64'b0000000000000000000000000000000000000000000000000000000000_1_0_0_0_1_1 | |
| 207 | #define RST_ASI_RESET_SSYS_DEF 64'b0000000000000000000000000000000000000000000000000000000000_0_0_0_0_0_0 | |
| 208 | ||
| 209 | #define RST_ASI_PROP_TIME_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111 | |
| 210 | #define RST_ASI_PROP_TIME_DEF 64'b000000000000000000000000000000000000000000000000000000000000_1_0_1_0 | |
| 211 | ||
| 212 | #define RST_ASI_LOCK_TIME_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111 | |
| 213 | #define RST_ASI_LOCK_TIME_DEF 64'b000000000000000000000000000000000000000000000000000000000000_1_0_1_0 | |
| 214 | ||
| 215 | #define RST_ASI_NIU_TIME_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111 | |
| 216 | #define RST_ASI_NIU_TIME_DEF 64'b000000000000000000000000000000000000000000000000000000000000_1_0_1_0 | |
| 217 | ||
| 218 | #define RST_ASI_CCU_TIME_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111 | |
| 219 | #define RST_ASI_CCU_TIME_DEF 64'b0000000000000000000000000000000000000000000000000000000000_1_0_0_0_0_0 | |
| 220 | ||
| 221 | #endif INC_RST_DEFINES_VRI | |
| 222 |