projects / OpenSPARC-T2-DV / blame
| Commit | Line | Data |
|---|---|---|
| 86530b38 AT |
1 | // -*- vera -*- |
| 2 | ||
| 3 | #ifndef INC_TCU_IF_VRI | |
| 4 | #define INC_TCU_IF_VRI | |
| 5 | ||
| 6 | #include "top_defines.vrh" | |
| 7 | ||
| 8 | interface jtag { | |
| 9 | input TCK CLOCK verilog_node "`TOP.tck"; | |
| 10 | input TDO INPUT_EDGE INPUT_SKEW verilog_node "`TOP.TDO"; | |
| 11 | output TEST_MODE OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.TEST_MODE"; | |
| 12 | output TDI OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.TDI"; | |
| 13 | output TMS OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.TMS"; | |
| 14 | output TRST_L OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.TRST_L"; | |
| 15 | } | |
| 16 | ||
| 17 | interface bscan { | |
| 18 | input TCK CLOCK verilog_node "`TOP.tck" ; | |
| 19 | input bs_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.bs_scan_en" ; | |
| 20 | input bs_clk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.bs_clk" ; | |
| 21 | input bs_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.bs_aclk" ; | |
| 22 | input bs_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.bs_bclk" ; | |
| 23 | input bs_uclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.bs_uclk" ; | |
| 24 | } | |
| 25 | ||
| 26 | interface mbist { | |
| 27 | input TCK CLOCK verilog_node "`TOP.tck"; | |
| 28 | input [65:0] mbist_bypass INPUT_EDGE INPUT_SKEW verilog_node "`TCU.mbist_bypass"; | |
| 29 | input mbist_parallel INPUT_EDGE INPUT_SKEW verilog_node "`TCU.mbist_parallel"; | |
| 30 | input mbist_diag INPUT_EDGE INPUT_SKEW verilog_node "`TCU.mbist_diag"; | |
| 31 | input mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.mbist_start"; // @@UPDATE@@ | |
| 32 | input tcu_spc0_mb_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc0_mb_scan_en"; | |
| 33 | input tcu_spc1_mb_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc1_mb_scan_en"; | |
| 34 | input tcu_spc2_mb_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc2_mb_scan_en"; | |
| 35 | input tcu_spc3_mb_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc3_mb_scan_en"; | |
| 36 | input tcu_spc4_mb_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc4_mb_scan_en"; | |
| 37 | input tcu_spc5_mb_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc5_mb_scan_en"; | |
| 38 | input tcu_spc6_mb_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc6_mb_scan_en"; | |
| 39 | input tcu_spc7_mb_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc7_mb_scan_en"; | |
| 40 | input [23:0] tcu_spc_mb_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc_mb_start"; | |
| 41 | input tcu_mbist_bisi_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mbist_bisi_en"; | |
| 42 | output [65:0] mb_tcu_done OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.mb_tcu_done"; | |
| 43 | output [65:0] mb_tcu_fail OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.mb_tcu_fail"; | |
| 44 | } | |
| 45 | ||
| 46 | interface scan { | |
| 47 | input TCK CLOCK verilog_node "`TOP.tck"; // Using pos/neg edge for AB clock | |
| 48 | input tcu_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_scan_en"; | |
| 49 | input tcu_srdes_scancfg INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_srdes_scancfg"; | |
| 50 | input tcu_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_aclk"; // For scan flush check | |
| 51 | input tcu_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_bclk"; // For scan flush check | |
| 52 | input tcu_scan_cclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_scan_cclk"; | |
| 53 | input tcu_pllbypass INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_pllbypass"; | |
| 54 | input tcu_pce_ov INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_pce_ov"; | |
| 55 | input [31:0] SCAN_OUT INPUT_EDGE INPUT_SKEW verilog_node "`TOP.SCAN_OUT"; | |
| 56 | input [2:0] tcu_spc0_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc0_scan_out"; | |
| 57 | input [2:0] tcu_spc1_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc1_scan_out"; | |
| 58 | input [2:0] tcu_spc2_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc2_scan_out"; | |
| 59 | input [2:0] tcu_spc3_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc3_scan_out"; | |
| 60 | input [2:0] tcu_spc4_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc4_scan_out"; | |
| 61 | input [2:0] tcu_spc5_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc5_scan_out"; | |
| 62 | input [2:0] tcu_spc6_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc6_scan_out"; | |
| 63 | input [2:0] tcu_spc7_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc7_scan_out"; | |
| 64 | input tcu_soc0_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc0_scan_out"; | |
| 65 | input tcu_soc1_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc1_scan_out"; | |
| 66 | input tcu_soc2_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc2_scan_out"; | |
| 67 | input tcu_soc3_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc3_scan_out"; | |
| 68 | input tcu_soc4_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc4_scan_out"; | |
| 69 | input tcu_soc5_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc5_scan_out"; | |
| 70 | input tcu_soc6_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc6_scan_out"; | |
| 71 | input tcu_srdes_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_srdes_scan_out"; | |
| 72 | input tcu_se_scancollar_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_se_scancollar_in"; | |
| 73 | input tcu_se_scancollar_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_se_scancollar_out"; | |
| 74 | input tcu_array_wr_inhibit INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_array_wr_inhibit"; | |
| 75 | input tcu_array_bypass INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_array_bypass"; | |
| 76 | input tcu_dectest INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_dectest"; | |
| 77 | input tcu_muxtest INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_muxtest"; | |
| 78 | ||
| 79 | output AC_TEST_MODE OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.AC_TEST_MODE"; | |
| 80 | output SCAN_EN OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.SCAN_EN"; | |
| 81 | output [31:0] SCAN_IN OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.SCAN_IN"; | |
| 82 | output SRDES_SCANCFG OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.SRDES_SCANCFG"; | |
| 83 | output [2:0] spc0_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.spc0_tcu_scan_in"; | |
| 84 | output [2:0] spc1_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.spc1_tcu_scan_in"; | |
| 85 | output [2:0] spc2_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.spc2_tcu_scan_in"; | |
| 86 | output [2:0] spc3_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.spc3_tcu_scan_in"; | |
| 87 | output [2:0] spc4_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.spc4_tcu_scan_in"; | |
| 88 | output [2:0] spc5_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.spc5_tcu_scan_in"; | |
| 89 | output [2:0] spc6_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.spc6_tcu_scan_in"; | |
| 90 | output [2:0] spc7_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.spc7_tcu_scan_in"; | |
| 91 | output soc0_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.soc0_tcu_scan_in"; | |
| 92 | output soc1_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.soc1_tcu_scan_in"; | |
| 93 | output soc2_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.soc2_tcu_scan_in"; | |
| 94 | output soc3_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.soc3_tcu_scan_in"; | |
| 95 | output soc4_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.soc4_tcu_scan_in"; | |
| 96 | output soc5_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.soc5_tcu_scan_in"; | |
| 97 | output soc6_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.soc6_tcu_scan_in"; | |
| 98 | output srdes_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.srdes_tcu_scan_in"; | |
| 99 | ||
| 100 | } | |
| 101 | ||
| 102 | interface efuse { | |
| 103 | input TCK CLOCK verilog_node "`TOP.tck"; | |
| 104 | input [6:0] tcu_efu_rowaddr INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_rowaddr"; | |
| 105 | input [4:0] tcu_efu_coladdr INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_coladdr"; | |
| 106 | input tcu_efu_read_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_read_en"; | |
| 107 | input [2:0] tcu_efu_read_mode INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_read_mode"; | |
| 108 | input tcu_efu_read_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_read_start"; | |
| 109 | input tcu_efu_fuse_bypass INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_fuse_bypass"; | |
| 110 | input tcu_efu_dest_sample INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_dest_sample"; | |
| 111 | input tcu_efu_updatedr INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_updatedr"; | |
| 112 | input tcu_efu_shiftdr INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_shiftdr"; | |
| 113 | input tcu_efu_capturedr INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_capturedr"; | |
| 114 | } | |
| 115 | ||
| 116 | interface tcu_siu { | |
| 117 | input CLK CLOCK verilog_node "`TOP.top_l2clk"; | |
| 118 | input tcu_sii_data INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_sii_data"; | |
| 119 | input tcu_sii_vld INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_sii_vld"; | |
| 120 | output sio_tcu_data OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.sio_tcu_data"; | |
| 121 | output sio_tcu_vld OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.sio_tcu_vld"; | |
| 122 | } | |
| 123 | ||
| 124 | interface clk_stop { | |
| 125 | input CLK CLOCK verilog_node "`TOP.top_l2clk"; | |
| 126 | input tcu_spc0_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc0_clk_stop"; | |
| 127 | input tcu_spc1_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc1_clk_stop"; | |
| 128 | input tcu_spc2_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc2_clk_stop"; | |
| 129 | input tcu_spc3_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc3_clk_stop"; | |
| 130 | input tcu_spc4_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc4_clk_stop"; | |
| 131 | input tcu_spc5_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc5_clk_stop"; | |
| 132 | input tcu_spc6_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc6_clk_stop"; | |
| 133 | input tcu_spc7_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc7_clk_stop"; | |
| 134 | input tcu_soc0cmp_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc0cmp_clk_stop"; | |
| 135 | input tcu_soc1cmp_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc1cmp_clk_stop"; | |
| 136 | input tcu_soc2cmp_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc2cmp_clk_stop"; | |
| 137 | input tcu_soc3cmp_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc3cmp_clk_stop"; | |
| 138 | input tcu_soc4cmp_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc4cmp_clk_stop"; | |
| 139 | input tcu_soc5ddr_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc5ddr_clk_stop"; | |
| 140 | input tcu_soc6io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc6io_clk_stop"; | |
| 141 | input tcu_soc7pc_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc7pc_clk_stop"; | |
| 142 | input tcu_soc8en_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc8en_clk_stop"; | |
| 143 | input tcu_spc0_mb_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc0_mb_clk_stop"; | |
| 144 | input tcu_spc1_mb_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc1_mb_clk_stop"; | |
| 145 | input tcu_spc2_mb_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc2_mb_clk_stop"; | |
| 146 | input tcu_spc3_mb_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc3_mb_clk_stop"; | |
| 147 | input tcu_spc4_mb_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc4_mb_clk_stop"; | |
| 148 | input tcu_spc5_mb_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc5_mb_clk_stop"; | |
| 149 | input tcu_spc6_mb_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc6_mb_clk_stop"; | |
| 150 | input tcu_spc7_mb_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc7_mb_clk_stop"; | |
| 151 | ||
| 152 | // @@UPDATE@@ Move these to the correct clock domain and interface | |
| 153 | input rst_tcu_flush_req INPUT_EDGE INPUT_SKEW verilog_node "`RST.rst_tcu_flush_req"; | |
| 154 | // output tcu_rst_flush_done OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.tcu_rst_flush_done"; // @@UPDATE@@ Remove when RST/TCU | |
| 155 | input tcu_rst_flush_done INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rst_flush_done"; | |
| 156 | // output rst_tcu_flush_req OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.rst_tcu_flush_req"; // @@UPDATE@@ Remove when RST/TCU | |
| 157 | } | |
| 158 | ||
| 159 | interface cmp_spc { | |
| 160 | input CLK CLOCK verilog_node "`TOP.top_iol2clk"; | |
| 161 | .for($b=0; $b<8; $b++) { | |
| 162 | input core_available_${b} INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc${b}_core_available" ; | |
| 163 | input core_enable_status_${b} INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc${b}_core_enable_status" ; | |
| 164 | input core_running_${b} INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc${b}_core_running" ; | |
| 165 | input core_running_status_${b} INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc${b}_ncu_core_running_status" ; | |
| 166 | .} | |
| 167 | output [21:0] tb_fusedata_init OUTPUT_EDGE OUTPUT_SKEW verilog_node "`MONTCU.tb_fusedata_init"; // Set core testbench core available | |
| 168 | } | |
| 169 | ||
| 170 | ||
| 171 | ||
| 172 | //// CLOCK is required in some global testbench files (ie: std_display_class.vr). | |
| 173 | //// Deleting this causes the simulation to hang in std_display_class on all dispmon calls with the MON_ERR parameter | |
| 174 | //// CLOCK below has no other purpose than this in the TCU testbench. | |
| 175 | verilog_node CLOCK "`TOP.tck"; | |
| 176 | #endif | |
| 177 |