Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / tcu / vera / include / ucb.if.vri

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ucb.if.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#ifndef INC_UCB_IF_VRI
#define INC_UCB_IF_VRI

#include "fc_top_defines.vri"

//
// For monitoring rd/wr of CCU CSRs
//
interface ccu_ucb_mon_if {
  input   clk                  CLOCK                  verilog_node "`NCU.iol2clk";

  //---request bus---       
  input   ncu_ccu_vld          PSAMPLE #-1  verilog_node "`NCU.ncu_ccu_vld" ;
  input   [3:0]  ncu_ccu_data  PSAMPLE #-1  verilog_node "`NCU.ncu_ccu_data" ;
  input   ccu_ncu_stall        PSAMPLE #-1  verilog_node "`NCU.ccu_ncu_stall" ;
   
   //---response bus--
  input   ccu_ncu_vld          PSAMPLE #-1  verilog_node "`NCU.ccu_ncu_vld" ;
  input   [3:0]  ccu_ncu_data  PSAMPLE #-1  verilog_node "`NCU.ccu_ncu_data" ;
  input   ncu_ccu_stall        PSAMPLE #-1  verilog_node "`NCU.ncu_ccu_stall" ;
}

//
// For monitoring rd/wr of DBG1 CSRs
//
interface dbg1_ucb_mon_if {
  input   clk                  CLOCK                  verilog_node "`NCU.iol2clk";

  //---request bus---       
  input   ncu_dbg1_vld          PSAMPLE #-1  verilog_node "`NCU.ncu_dbg1_vld" ;
  input   [3:0]  ncu_dbg1_data  PSAMPLE #-1  verilog_node "`NCU.ncu_dbg1_data" ;
  input   dbg1_ncu_stall        PSAMPLE #-1  verilog_node "`NCU.dbg1_ncu_stall" ;
   
   //---response bus--
  input   dbg1_ncu_vld          PSAMPLE #-1  verilog_node "`NCU.dbg1_ncu_vld" ;
  input   [3:0]  dbg1_ncu_data  PSAMPLE #-1  verilog_node "`NCU.dbg1_ncu_data" ;
  input   ncu_dbg1_stall        PSAMPLE #-1  verilog_node "`NCU.ncu_dbg1_stall" ;
}

//
// For monitoring rd/wr of RST's CSRs
//
interface rst_ucb_mon_if {
  input   clk                  CLOCK                  verilog_node "`NCU.iol2clk";

  //---request bus---
  input   ncu_rst_vld          PSAMPLE #-1  verilog_node "`NCU.ncu_rst_vld" ;
  input   [3:0]  ncu_rst_data  PSAMPLE #-1  verilog_node "`NCU.ncu_rst_data" ;
  input   rst_ncu_stall        PSAMPLE #-1  verilog_node "`NCU.rst_ncu_stall" ;

   //---response bus--
  input   rst_ncu_vld          PSAMPLE #-1  verilog_node "`NCU.rst_ncu_vld" ;
  input   [3:0]  rst_ncu_data  PSAMPLE #-1  verilog_node "`NCU.rst_ncu_data" ;
  input   ncu_rst_stall        PSAMPLE #-1  verilog_node "`NCU.ncu_rst_stall" ;
}

//
// For monitoring ucb rd/wr between NCU-TCU
//
interface tcu_ucb_mon_if {
  input   clk                  CLOCK                  verilog_node "`NCU.iol2clk";

  //---request bus---
  input   ncu_tcu_vld          PSAMPLE #-1  verilog_node "`NCU.ncu_tcu_vld" ;
  input   [7:0]  ncu_tcu_data  PSAMPLE #-1  verilog_node "`NCU.ncu_tcu_data" ;
  input   tcu_ncu_stall        PSAMPLE #-1  verilog_node "`NCU.tcu_ncu_stall" ;

   //---response bus--
  input   tcu_ncu_vld          PSAMPLE #-1  verilog_node "`NCU.tcu_ncu_vld" ;
  input   [7:0]  tcu_ncu_data  PSAMPLE #-1  verilog_node "`NCU.tcu_ncu_data" ;
  input   ncu_tcu_stall        PSAMPLE #-1  verilog_node "`NCU.ncu_tcu_stall" ;
}

#endif