verif/env/tcu/vera/include/ucb.if.vri

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: ucb.if.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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// the Free Software Foundation; version 2 of the License.
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
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// along with this program; if not, write to the Free Software
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// ========== Copyright Header End ============================================
#ifndef INC_UCB_IF_VRI
#define INC_UCB_IF_VRI

#include "fc_top_defines.vri"

//
// For monitoring rd/wr of CCU CSRs
//
interface ccu_ucb_mon_if {
  input   clk                  CLOCK                  verilog_node "`NCU.iol2clk";

  //---request bus---
  input   ncu_ccu_vld          PSAMPLE #-1  verilog_node "`NCU.ncu_ccu_vld" ;
  input   [3:0]  ncu_ccu_data  PSAMPLE #-1  verilog_node "`NCU.ncu_ccu_data" ;
  input   ccu_ncu_stall        PSAMPLE #-1  verilog_node "`NCU.ccu_ncu_stall" ;

   //---response bus--
  input   ccu_ncu_vld          PSAMPLE #-1  verilog_node "`NCU.ccu_ncu_vld" ;
  input   [3:0]  ccu_ncu_data  PSAMPLE #-1  verilog_node "`NCU.ccu_ncu_data" ;
  input   ncu_ccu_stall        PSAMPLE #-1  verilog_node "`NCU.ncu_ccu_stall" ;
}

//
// For monitoring rd/wr of DBG1 CSRs
//
interface dbg1_ucb_mon_if {
  input   clk                  CLOCK                  verilog_node "`NCU.iol2clk";

  //---request bus---
  input   ncu_dbg1_vld          PSAMPLE #-1  verilog_node "`NCU.ncu_dbg1_vld" ;
  input   [3:0]  ncu_dbg1_data  PSAMPLE #-1  verilog_node "`NCU.ncu_dbg1_data" ;
  input   dbg1_ncu_stall        PSAMPLE #-1  verilog_node "`NCU.dbg1_ncu_stall" ;

   //---response bus--
  input   dbg1_ncu_vld          PSAMPLE #-1  verilog_node "`NCU.dbg1_ncu_vld" ;
  input   [3:0]  dbg1_ncu_data  PSAMPLE #-1  verilog_node "`NCU.dbg1_ncu_data" ;
  input   ncu_dbg1_stall        PSAMPLE #-1  verilog_node "`NCU.ncu_dbg1_stall" ;
}

//
// For monitoring rd/wr of RST's CSRs
//
interface rst_ucb_mon_if {
  input   clk                  CLOCK                  verilog_node "`NCU.iol2clk";

  //---request bus---
  input   ncu_rst_vld          PSAMPLE #-1  verilog_node "`NCU.ncu_rst_vld" ;
  input   [3:0]  ncu_rst_data  PSAMPLE #-1  verilog_node "`NCU.ncu_rst_data" ;
  input   rst_ncu_stall        PSAMPLE #-1  verilog_node "`NCU.rst_ncu_stall" ;

   //---response bus--
  input   rst_ncu_vld          PSAMPLE #-1  verilog_node "`NCU.rst_ncu_vld" ;
  input   [3:0]  rst_ncu_data  PSAMPLE #-1  verilog_node "`NCU.rst_ncu_data" ;
  input   ncu_rst_stall        PSAMPLE #-1  verilog_node "`NCU.ncu_rst_stall" ;
}

//
// For monitoring ucb rd/wr between NCU-TCU
//
interface tcu_ucb_mon_if {
  input   clk                  CLOCK                  verilog_node "`NCU.iol2clk";

  //---request bus---
  input   ncu_tcu_vld          PSAMPLE #-1  verilog_node "`NCU.ncu_tcu_vld" ;
  input   [7:0]  ncu_tcu_data  PSAMPLE #-1  verilog_node "`NCU.ncu_tcu_data" ;
  input   tcu_ncu_stall        PSAMPLE #-1  verilog_node "`NCU.tcu_ncu_stall" ;

   //---response bus--
  input   tcu_ncu_vld          PSAMPLE #-1  verilog_node "`NCU.tcu_ncu_vld" ;
  input   [7:0]  tcu_ncu_data  PSAMPLE #-1  verilog_node "`NCU.tcu_ncu_data" ;
  input   ncu_tcu_stall        PSAMPLE #-1  verilog_node "`NCU.ncu_tcu_stall" ;
}

#endif