[OpenSPARC-T2-DV] / verif / model / verilog / mem / dram / fbdimm_DIMMx4.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fbdimm_DIMMx4.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`timescale 1ps/1ps

module fbdimm_DIMMx4 (CK, bCK, CKE, bCS, bRAS, bCAS, bWE, 
                      BA, Addr, DQ, CB, DQS, bDQS, DM_RDQS,
                      bRDQS, ODT, term, CS_SEL, l0state);

   parameter regdel=500; // ps
   
`ifdef DRAM_SAT 
   parameter addr_bits=15,
`else
   parameter addr_bits=17,
`endif

`ifdef DRAM_BANK_BITS2
   bank_bits=2,
`else
   bank_bits=3,
`endif

   data_bits=64,
   dqs_bits=9;

   input    			CK,bCK;   		// Clock Signals
   input [17:0] 		CKE;      		// Clock Enable
   input [17:0] 		bCS;      		// Rank/Chip Selects
   input [17:0] 		bRAS, bCAS, bWE;	// Command Inputs
   input [(bank_bits-1):0] 	BA;			// Address Inputs (Bank sel)
   input [(addr_bits-1):0] 	Addr;			// Address Inputs
   inout [(data_bits-1):0] 	DQ;			// Data Bus
   inout [7:0] 		   	CB; 		   
   inout [(dqs_bits-1):0]       DQS, bDQS;		// Data Strobe (bidir)
   inout [(dqs_bits-1):0]       DM_RDQS, bRDQS;		// Data Mask
   input [17:0] 		ODT;			// On Die Termination
   output [17:0] 		term;
   input [7:0] 			CS_SEL;
   input			l0state;

   supply0 		   	vss; 		   
   supply1 		   	vdd;

`ifdef X4_REGISTER

   reg [17:0] 		   ODT_int;
   reg [17:0] 		   CKE_int, bCS_int;
   reg [17:0]		   bRAS_int, bCAS_int, bWE_int;
   reg [(bank_bits-1):0]   BA_int;
   reg [(addr_bits-1):0]   Addr_int;

   always @(posedge CK)
   begin
      CKE_int 	  <= #regdel CKE;
      bCS_int 	  <= #regdel bCS;
      bRAS_int 	  <= #regdel bRAS;
      bCAS_int 	  <= #regdel bCAS;
      bWE_int 	  <= #regdel bWE;
      BA_int 	  <= #regdel BA;
      Addr_int 	  <= #regdel Addr;
      ODT_int 	  <= #regdel ODT;
   end // always @ (posedge CK)
`else
   wire [17:0] 		   ODT_int;
   wire [17:0] 		   CKE_int, bCS_int;
   wire [17:0]		   bRAS_int, bCAS_int, bWE_int;
   wire [(bank_bits-1):0]   BA_int;
   wire [(addr_bits-1):0]   Addr_int;
   assign CKE_int = CKE;
   assign bCS_int 	  =  bCS;
   assign bRAS_int 	  =  bRAS;
   assign bCAS_int 	  =  bCAS;
   assign bWE_int 	  =  bWE;
   assign BA_int 	  =  BA;
   assign Addr_int 	  =  Addr;
   assign ODT_int 	  =  ODT;
`endif
   

   dimm U00 ( .clk (CK),
              .cs  (bCS_int[0]),
              .ras (bRAS_int[0]),
              .cas (bCAS_int[0]),
              .we  (bWE_int[0]),
              .ba  (BA_int),
              .addr (Addr_int),
              .cs_sel (CS_SEL),
              .dataq (DQ[3:0]),
              .dqs (DQS[0]));

   dimm U02 ( .clk (CK),
              .cs  (bCS_int[1]),
              .ras (bRAS_int[1]),
              .cas (bCAS_int[1]),
              .we  (bWE_int[1]),
              .ba  (BA_int),
              .addr (Addr_int),
              .cs_sel (CS_SEL),
              .dataq (DQ[11:8]),
              .dqs (DQS[1]));

   dimm U05 ( .clk (CK),
              .cs  (bCS_int[2]),
              .ras (bRAS_int[2]),
              .cas (bCAS_int[2]),
              .we  (bWE_int[2]),
              .ba  (BA_int),
              .addr (Addr_int),
              .cs_sel (CS_SEL),
              .dataq (DQ[19:16]),
              .dqs (DQS[0]));

   dimm U07 ( .clk (CK),
              .cs  (bCS_int[3]),
              .ras (bRAS_int[3]),
              .cas (bCAS_int[3]),
              .we  (bWE_int[3]),
              .ba  (BA_int),
              .addr (Addr_int),
              .cs_sel (CS_SEL),
              .dataq (DQ[27:24]),
              .dqs (DQS[0]));

   dimm U09 ( .clk (CK),
              .cs  (bCS_int[4]),
              .ras (bRAS_int[4]),
              .cas (bCAS_int[4]),
              .we  (bWE_int[4]),
              .ba  (BA_int),
              .addr (Addr_int),
              .cs_sel (CS_SEL),
              .dataq (DQ[35:32]),
              .dqs (DQS[0]));


   dimm U11 ( .clk (CK),
              .cs  (bCS_int[5]),
              .ras (bRAS_int[5]),
              .cas (bCAS_int[5]),
              .we  (bWE_int[5]),
              .ba  (BA_int),
              .addr (Addr_int),
              .cs_sel (CS_SEL),
              .dataq (DQ[43:40]),
              .dqs (DQS[0]));

   dimm U14 ( .clk (CK),
              .cs  (bCS_int[6]),
              .ras (bRAS_int[6]),
              .cas (bCAS_int[6]),
              .we  (bWE_int[6]),
              .ba  (BA_int),
              .addr (Addr_int),
              .cs_sel (CS_SEL),
              .dataq (DQ[51:48]),
              .dqs (DQS[0]));

   dimm U16 ( .clk (CK),
              .cs  (bCS_int[7]),
              .ras (bRAS_int[7]),
              .cas (bCAS_int[7]),
              .we  (bWE_int[7]),
              .ba  (BA_int),
              .addr (Addr_int),
              .cs_sel (CS_SEL),
              .dataq (DQ[59:56]),
              .dqs (DQS[0]));

   dimm U04 ( .clk (CK),
              .cs  (bCS_int[8]),
              .ras (bRAS_int[8]),
              .cas (bCAS_int[8]),
              .we  (bWE_int[8]),
              .ba  (BA_int),
              .addr (Addr_int),
              .cs_sel (CS_SEL),
              .dataq (CB[3:0]),
              .dqs (DQS[0]));

   dimm U01 ( .clk (CK),
              .cs  (bCS_int[9]),
              .ras (bRAS_int[9]),
              .cas (bCAS_int[9]),
              .we  (bWE_int[9]),
              .ba  (BA_int),
              .addr (Addr_int),
              .cs_sel (CS_SEL),
              .dataq (DQ[7:4]),
              .dqs (DQS[0]));

   dimm U03 ( .clk (CK),
              .cs  (bCS_int[10]),
              .ras (bRAS_int[10]),
              .cas (bCAS_int[10]),
              .we  (bWE_int[10]),
              .ba  (BA_int),
              .addr (Addr_int),
              .cs_sel (CS_SEL),
              .dataq (DQ[15:12]),
              .dqs (DQS[0]));

   dimm U06 ( .clk (CK),
              .cs  (bCS_int[11]),
              .ras (bRAS_int[11]),
              .cas (bCAS_int[11]),
              .we  (bWE_int[11]),
              .ba  (BA_int),
              .addr (Addr_int),
              .cs_sel (CS_SEL),
              .dataq (DQ[23:20]),
              .dqs (DQS[0]));

   dimm U08 ( .clk (CK),
              .cs  (bCS_int[12]),
              .ras (bRAS_int[12]),
              .cas (bCAS_int[12]),
              .we  (bWE_int[12]),
              .ba  (BA_int),
              .addr (Addr_int),
              .cs_sel (CS_SEL),
              .dataq (DQ[31:28]),
              .dqs (DQS[0]));

   dimm U10 ( .clk (CK),
              .cs  (bCS_int[13]),
              .ras (bRAS_int[13]),
              .cas (bCAS_int[13]),
              .we  (bWE_int[13]),
              .ba  (BA_int),
              .addr (Addr_int),
              .cs_sel (CS_SEL),
              .dataq (DQ[39:36]),
              .dqs (DQS[0]));

   dimm U12 ( .clk (CK),
              .cs  (bCS_int[14]),
              .ras (bRAS_int[14]),
              .cas (bCAS_int[14]),
              .we  (bWE_int[14]),
              .ba  (BA_int),
              .addr (Addr_int),
              .cs_sel (CS_SEL),
              .dataq (DQ[47:44]),
              .dqs (DQS[0]));

   dimm U15 ( .clk (CK),
              .cs  (bCS_int[15]),
              .ras (bRAS_int[15]),
              .cas (bCAS_int[15]),
              .we  (bWE_int[15]),
              .ba  (BA_int),
              .addr (Addr_int),
              .cs_sel (CS_SEL),
              .dataq (DQ[55:52]),
              .dqs (DQS[0]));

   dimm U17 ( .clk (CK),
              .cs  (bCS_int[16]),
              .ras (bRAS_int[16]),
              .cas (bCAS_int[16]),
              .we  (bWE_int[16]),
              .ba  (BA_int),
              .addr (Addr_int),
              .cs_sel (CS_SEL),
              .dataq (DQ[63:60]),
              .dqs (DQS[0]));

   dimm U13 ( .clk (CK),
              .cs  (bCS_int[17]),
              .ras (bRAS_int[17]),
              .cas (bCAS_int[17]),
              .we  (bWE_int[17]),
              .ba  (BA_int),
              .addr (Addr_int),
              .cs_sel (CS_SEL),
              .dataq (CB[7:4]),
              .dqs (DQS[0]));


endmodule
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: fbdimm_DIMMx4.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	`timescale 1ps/1ps
	36
	37	module fbdimm_DIMMx4 (CK, bCK, CKE, bCS, bRAS, bCAS, bWE,
	38	BA, Addr, DQ, CB, DQS, bDQS, DM_RDQS,
	39	bRDQS, ODT, term, CS_SEL, l0state);
	40
	41	parameter regdel=500; // ps
	42
	43	`ifdef DRAM_SAT
	44	parameter addr_bits=15,
	45	`else
	46	parameter addr_bits=17,
	47	`endif
	48
	49	`ifdef DRAM_BANK_BITS2
	50	bank_bits=2,
	51	`else
	52	bank_bits=3,
	53	`endif
	54
	55	data_bits=64,
	56	dqs_bits=9;
	57
	58	input CK,bCK; // Clock Signals
	59	input [17:0] CKE; // Clock Enable
	60	input [17:0] bCS; // Rank/Chip Selects
	61	input [17:0] bRAS, bCAS, bWE; // Command Inputs
	62	input [(bank_bits-1):0] BA; // Address Inputs (Bank sel)
	63	input [(addr_bits-1):0] Addr; // Address Inputs
	64	inout [(data_bits-1):0] DQ; // Data Bus
65	inout [7:0] CB;
66	inout [(dqs_bits-1):0] DQS, bDQS; // Data Strobe (bidir)
67	inout [(dqs_bits-1):0] DM_RDQS, bRDQS; // Data Mask
68	input [17:0] ODT; // On Die Termination
69	output [17:0] term;
70	input [7:0] CS_SEL;
71	input l0state;
72
73	supply0 vss;
74	supply1 vdd;
75
76	`ifdef X4_REGISTER
77
78	reg [17:0] ODT_int;
79	reg [17:0] CKE_int, bCS_int;
80	reg [17:0] bRAS_int, bCAS_int, bWE_int;
81	reg [(bank_bits-1):0] BA_int;
82	reg [(addr_bits-1):0] Addr_int;
83
84	always @(posedge CK)
85	begin
86	CKE_int <= #regdel CKE;
87	bCS_int <= #regdel bCS;
88	bRAS_int <= #regdel bRAS;
89	bCAS_int <= #regdel bCAS;
90	bWE_int <= #regdel bWE;
91	BA_int <= #regdel BA;
92	Addr_int <= #regdel Addr;
93	ODT_int <= #regdel ODT;
94	end // always @ (posedge CK)
95	`else
96	wire [17:0] ODT_int;
97	wire [17:0] CKE_int, bCS_int;
98	wire [17:0] bRAS_int, bCAS_int, bWE_int;
99	wire [(bank_bits-1):0] BA_int;
100	wire [(addr_bits-1):0] Addr_int;
101	assign CKE_int = CKE;
102	assign bCS_int = bCS;
103	assign bRAS_int = bRAS;
104	assign bCAS_int = bCAS;
105	assign bWE_int = bWE;
106	assign BA_int = BA;
107	assign Addr_int = Addr;
108	assign ODT_int = ODT;
109	`endif
110
111
112	dimm U00 ( .clk (CK),
113	.cs (bCS_int[0]),
114	.ras (bRAS_int[0]),
115	.cas (bCAS_int[0]),
116	.we (bWE_int[0]),
117	.ba (BA_int),
118	.addr (Addr_int),
119	.cs_sel (CS_SEL),
120	.dataq (DQ[3:0]),
121	.dqs (DQS[0]));
122
123	dimm U02 ( .clk (CK),
124	.cs (bCS_int[1]),
125	.ras (bRAS_int[1]),
126	.cas (bCAS_int[1]),
127	.we (bWE_int[1]),
128	.ba (BA_int),
129	.addr (Addr_int),
130	.cs_sel (CS_SEL),
131	.dataq (DQ[11:8]),
132	.dqs (DQS[1]));
133
134	dimm U05 ( .clk (CK),
135	.cs (bCS_int[2]),
136	.ras (bRAS_int[2]),
137	.cas (bCAS_int[2]),
138	.we (bWE_int[2]),
139	.ba (BA_int),
140	.addr (Addr_int),
141	.cs_sel (CS_SEL),
142	.dataq (DQ[19:16]),
143	.dqs (DQS[0]));
144
145	dimm U07 ( .clk (CK),
146	.cs (bCS_int[3]),
147	.ras (bRAS_int[3]),
148	.cas (bCAS_int[3]),
149	.we (bWE_int[3]),
150	.ba (BA_int),
151	.addr (Addr_int),
152	.cs_sel (CS_SEL),
153	.dataq (DQ[27:24]),
154	.dqs (DQS[0]));
155
156	dimm U09 ( .clk (CK),
157	.cs (bCS_int[4]),
158	.ras (bRAS_int[4]),
159	.cas (bCAS_int[4]),
160	.we (bWE_int[4]),
161	.ba (BA_int),
162	.addr (Addr_int),
163	.cs_sel (CS_SEL),
164	.dataq (DQ[35:32]),
165	.dqs (DQS[0]));
166
167
168	dimm U11 ( .clk (CK),
169	.cs (bCS_int[5]),
170	.ras (bRAS_int[5]),
171	.cas (bCAS_int[5]),
172	.we (bWE_int[5]),
173	.ba (BA_int),
174	.addr (Addr_int),
175	.cs_sel (CS_SEL),
176	.dataq (DQ[43:40]),
177	.dqs (DQS[0]));
178
179	dimm U14 ( .clk (CK),
180	.cs (bCS_int[6]),
181	.ras (bRAS_int[6]),
182	.cas (bCAS_int[6]),
183	.we (bWE_int[6]),
184	.ba (BA_int),
185	.addr (Addr_int),
186	.cs_sel (CS_SEL),
187	.dataq (DQ[51:48]),
188	.dqs (DQS[0]));
189
190	dimm U16 ( .clk (CK),
191	.cs (bCS_int[7]),
192	.ras (bRAS_int[7]),
193	.cas (bCAS_int[7]),
194	.we (bWE_int[7]),
195	.ba (BA_int),
196	.addr (Addr_int),
197	.cs_sel (CS_SEL),
198	.dataq (DQ[59:56]),
199	.dqs (DQS[0]));
200
201	dimm U04 ( .clk (CK),
202	.cs (bCS_int[8]),
203	.ras (bRAS_int[8]),
204	.cas (bCAS_int[8]),
205	.we (bWE_int[8]),
206	.ba (BA_int),
207	.addr (Addr_int),
208	.cs_sel (CS_SEL),
209	.dataq (CB[3:0]),
210	.dqs (DQS[0]));
211
212	dimm U01 ( .clk (CK),
213	.cs (bCS_int[9]),
214	.ras (bRAS_int[9]),
215	.cas (bCAS_int[9]),
216	.we (bWE_int[9]),
217	.ba (BA_int),
218	.addr (Addr_int),
219	.cs_sel (CS_SEL),
220	.dataq (DQ[7:4]),
221	.dqs (DQS[0]));
222
223	dimm U03 ( .clk (CK),
224	.cs (bCS_int[10]),
225	.ras (bRAS_int[10]),
226	.cas (bCAS_int[10]),
227	.we (bWE_int[10]),
228	.ba (BA_int),
229	.addr (Addr_int),
230	.cs_sel (CS_SEL),
231	.dataq (DQ[15:12]),
232	.dqs (DQS[0]));
233
234	dimm U06 ( .clk (CK),
235	.cs (bCS_int[11]),
236	.ras (bRAS_int[11]),
237	.cas (bCAS_int[11]),
238	.we (bWE_int[11]),
239	.ba (BA_int),
240	.addr (Addr_int),
241	.cs_sel (CS_SEL),
242	.dataq (DQ[23:20]),
243	.dqs (DQS[0]));
244
245	dimm U08 ( .clk (CK),
246	.cs (bCS_int[12]),
247	.ras (bRAS_int[12]),
248	.cas (bCAS_int[12]),
249	.we (bWE_int[12]),
250	.ba (BA_int),
251	.addr (Addr_int),
252	.cs_sel (CS_SEL),
253	.dataq (DQ[31:28]),
254	.dqs (DQS[0]));
255
256	dimm U10 ( .clk (CK),
257	.cs (bCS_int[13]),
258	.ras (bRAS_int[13]),
259	.cas (bCAS_int[13]),
260	.we (bWE_int[13]),
261	.ba (BA_int),
262	.addr (Addr_int),
263	.cs_sel (CS_SEL),
264	.dataq (DQ[39:36]),
265	.dqs (DQS[0]));
266
267	dimm U12 ( .clk (CK),
268	.cs (bCS_int[14]),
269	.ras (bRAS_int[14]),
270	.cas (bCAS_int[14]),
271	.we (bWE_int[14]),
272	.ba (BA_int),
273	.addr (Addr_int),
274	.cs_sel (CS_SEL),
275	.dataq (DQ[47:44]),
276	.dqs (DQS[0]));
277
278	dimm U15 ( .clk (CK),
279	.cs (bCS_int[15]),
280	.ras (bRAS_int[15]),
281	.cas (bCAS_int[15]),
282	.we (bWE_int[15]),
283	.ba (BA_int),
284	.addr (Addr_int),
285	.cs_sel (CS_SEL),
286	.dataq (DQ[55:52]),
287	.dqs (DQS[0]));
288
289	dimm U17 ( .clk (CK),
290	.cs (bCS_int[16]),
291	.ras (bRAS_int[16]),
292	.cas (bCAS_int[16]),
293	.we (bWE_int[16]),
294	.ba (BA_int),
295	.addr (Addr_int),
296	.cs_sel (CS_SEL),
297	.dataq (DQ[63:60]),
298	.dqs (DQS[0]));
299
300	dimm U13 ( .clk (CK),
301	.cs (bCS_int[17]),
302	.ras (bRAS_int[17]),
303	.cas (bCAS_int[17]),
304	.we (bWE_int[17]),
305	.ba (BA_int),
306	.addr (Addr_int),
307	.cs_sel (CS_SEL),
308	.dataq (CB[7:4]),
309	.dqs (DQS[0]));
310
311
312
313	endmodule