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// OpenSPARC T2 Processor File: fbdimm_DIMMx4.v
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module fbdimm_DIMMx4 (CK, bCK, CKE, bCS, bRAS, bCAS, bWE,
BA, Addr, DQ, CB, DQS, bDQS, DM_RDQS,
bRDQS, ODT, term, CS_SEL, l0state);
parameter regdel=500; // ps
input CK,bCK; // Clock Signals
input [17:0] CKE; // Clock Enable
input [17:0] bCS; // Rank/Chip Selects
input [17:0] bRAS, bCAS, bWE; // Command Inputs
input [(bank_bits-1):0] BA; // Address Inputs (Bank sel)
input [(addr_bits-1):0] Addr; // Address Inputs
inout [(data_bits-1):0] DQ; // Data Bus
inout [(dqs_bits-1):0] DQS, bDQS; // Data Strobe (bidir)
inout [(dqs_bits-1):0] DM_RDQS, bRDQS; // Data Mask
input [17:0] ODT; // On Die Termination
reg [17:0] CKE_int, bCS_int;
reg [17:0] bRAS_int, bCAS_int, bWE_int;
reg [(bank_bits-1):0] BA_int;
reg [(addr_bits-1):0] Addr_int;
bRAS_int <= #regdel bRAS;
bCAS_int <= #regdel bCAS;
Addr_int <= #regdel Addr;
end // always @ (posedge CK)
wire [17:0] CKE_int, bCS_int;
wire [17:0] bRAS_int, bCAS_int, bWE_int;
wire [(bank_bits-1):0] BA_int;
wire [(addr_bits-1):0] Addr_int;