Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / model / verilog / mem / fbdimm / library / fifo / rptr_empty.v

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// OpenSPARC T2 Processor File: rptr_empty.v
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module rptr_empty (rempty,raddr,rptr,rwptr2,rinc,rclk,rrst_n);
parameter ADDRSIZE=6;

output                rempty;
output [ADDRSIZE-1:0] raddr;
output [ADDRSIZE:0]   rptr;
input  [ADDRSIZE:0]   rwptr2;
input                 rinc,rclk,rrst_n;
reg   [ADDRSIZE:0]    rptr,rbin,rgnext,rbnext;
reg                     rempty,raddrmsb;

// Gray style pointer

always @(posedge rclk or negedge rrst_n)
 if ( !rrst_n) begin
    rptr <=0;
    raddrmsb <= 0;
  end
 else begin
   rptr <= rgnext;
   raddrmsb <= rgnext[ADDRSIZE]^rgnext[ADDRSIZE-1];
 end

always @(rptr or rinc or rempty ) begin: Gray_inc
  integer i;
  for (i=0; i <= ADDRSIZE; i=i+1)
    rbin[i] = ^(rptr>>i);
  if (!rempty ) rbnext = rbin + rinc;
   else  rbnext = rbin;
  rgnext = (rbnext >> 1) ^ rbnext;
end

// memory read address pointer
assign raddr = { raddrmsb,rptr[ADDRSIZE-2:0]};

// fifo empty on reset or when next rptr == synced wptr

always @(posedge rclk or negedge rrst_n)
  if (!rrst_n ) rempty <= 1'b1;
  else          rempty <= (rgnext == rwptr2);
endmodule