design/sys/iop/dmu/rtl/dmu_mmu_qcb_qgc.v

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//
// OpenSPARC T2 Processor File: dmu_mmu_qcb_qgc.v
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module dmu_mmu_qcb_qgc
  (
   clk,                         // clock
   rst_l,                       // reset
   enq,                         // enqueue
   deq,                         // dequeue
   ld,                          // load
   ds,                          // data select
   vld                          // valid bits
   );

// ----------------------------------------------------------------------------
// Parameters
// ----------------------------------------------------------------------------
  parameter     QD = 4;         // queue depth

// ----------------------------------------------------------------------------
// Ports
// ----------------------------------------------------------------------------
  input                 clk;
  input                 rst_l;

  input                 enq;
  input                 deq;

  output [QD-1:0]       ld;
  output [QD-2:0]       ds;
  output [QD-1:0]       vld;

// ----------------------------------------------------------------------------
// Variables
// ----------------------------------------------------------------------------
  reg  [QD-1:0]         ld;
  reg  [QD-2:0]         ds;
  reg  [QD-1:0]         vld, nxt_vld;

  integer i;

// ----------------------------------------------------------------------------
// Zero In Checkers
// ----------------------------------------------------------------------------

  // 0in fifo -enq enq -deq deq -depth QD

// ----------------------------------------------------------------------------
// Combinational
// ----------------------------------------------------------------------------
  always @ (rst_l or enq or deq or vld) begin
    case ({enq, deq})
      2'b00 : ld = ~{ QD { rst_l } };
      2'b01 : ld =  vld;
      2'b10 : ld = ~vld;
      2'b11 : ld =  vld;
    endcase
  end

  always @ (vld) begin
    for (i = 0; i < QD - 1; i = i + 1) ds[i] = vld[i+1];
  end

  always @ (enq or deq or vld) begin
    case ({enq, deq})
      2'b00 : nxt_vld = vld;
      2'b01 : nxt_vld = { 1'b0, vld[QD-1:1] };
      2'b10 : nxt_vld = { vld[QD-2:0], 1'b1 };
      2'b11 : nxt_vld = vld;
    endcase
  end

// ----------------------------------------------------------------------------
// Sequential
// ----------------------------------------------------------------------------
  always @ (posedge clk) begin
    if (!rst_l) begin
      vld <= 0;
    end
    else begin
      vld <= nxt_vld;
    end
  end

endmodule // dmu_mmu_qcb_qgc