verif/env/common/vera/classes/siu_ncu_mondo.if.vrh

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//
// OpenSPARC T2 Processor File: siu_ncu_mondo.if.vrh
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#ifndef INC__SIU_NCU_MONDO_IF_VRH
#define INC__SIU_NCU_MONDO_IF_VRH

///////////////////////////////////////////////////////////////////////////
#include "top_defines.vrh"


///////////// mondo ncu and ssi/dmu interface //////////////////////
interface mondo_ncu_if
{
  input           iol2clk                 CLOCK                 verilog_node "`CPU.ncu.iol2clk";
  input           sii_ncu_req             PSAMPLE   INPUT_SKEW  verilog_node "`CPU.ncu.sii_ncu_req";
  input  [31:0]   sii_ncu_data            PSAMPLE   INPUT_SKEW  verilog_node "`CPU.ncu.sii_ncu_data";
  input           ncu_sii_gnt             PSAMPLE   INPUT_SKEW  verilog_node "`CPU.ncu.ncu_sii_gnt";
  input           ncu_dmu_mondo_ack       PSAMPLE   INPUT_SKEW  verilog_node "`CPU.ncu.ncu_dmu_mondo_ack";
  input           ncu_dmu_mondo_nack      PSAMPLE   INPUT_SKEW  verilog_node "`CPU.ncu.ncu_dmu_mondo_nack";
  input  [5:0]    ncu_dmu_mondo_id        PSAMPLE   INPUT_SKEW  verilog_node "`CPU.ncu.ncu_dmu_mondo_id";
}

#endif