// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: niu.flist
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
// cdmspp_flist created Mon Nov 28 21:28:51 PST 2005
+incdir+../../../design/sys/iop/niu/rtl
+incdir+../../../design/sys/iop/niu/rtl
+incdir+../../../design/sys/iop/niu/rtl
+incdir+../../../design/sys/iop/niu/rtl
+incdir+../../../design/sys/iop/niu/rtl
+incdir+../../../design/sys/iop/niu/rtl
+incdir+../../../design/sys/iop/niu/rtl
+incdir+../../../design/sys/iop/niu/rtl
+incdir+../../../design/sys/iop/niu/rtl
+incdir+../../../design/sys/iop/niu/rtl
+incdir+../../../design/sys/iop/niu/rtl
+incdir+../../../design/sys/iop/niu/rtl
+incdir+../../../design/sys/iop/niu/rtl
+incdir+../../../design/sys/iop/niu/rtl
+incdir+../../../design/sys/iop/niu/rtl
+incdir+../../../verif/env/niu/verilog
-v ../../../libs/clk/n2_clk_clstr_hdr_cust_l/n2_clk_clstr_hdr_cust/rtl/n2_clk_clstr_hdr_cust.v
../../../libs/clk/rtl/clkgen_mac_io.v
../../../libs/clk/n2_clk_pgrid_cust_l/n2_clk_mac_io_cust/rtl/n2_clk_mac_io_cust.v
../../../libs/clk/rtl/clkgen_rdp_io.v
../../../libs/clk/rtl/clkgen_rdp_io2x.v
../../../libs/clk/n2_clk_pgrid_cust_l/n2_clk_rdp_io2x_cust/rtl/n2_clk_rdp_io2x_cust.v
../../../libs/clk/n2_clk_pgrid_cust_l/n2_clk_rdp_io_cust/rtl/n2_clk_rdp_io_cust.v
../../../libs/clk/rtl/clkgen_rtx_io.v
../../../libs/clk/rtl/clkgen_rtx_io2x.v
../../../libs/clk/n2_clk_pgrid_cust_l/n2_clk_rtx_io2x_cust/rtl/n2_clk_rtx_io2x_cust.v
../../../libs/clk/n2_clk_pgrid_cust_l/n2_clk_rtx_io_cust/rtl/n2_clk_rtx_io_cust.v
../../../libs/clk/rtl/clkgen_tds_io.v
../../../libs/clk/rtl/clkgen_tds_io2x.v
../../../libs/clk/n2_clk_pgrid_cust_l/n2_clk_tds_io2x_cust/rtl/n2_clk_tds_io2x_cust.v
../../../libs/clk/n2_clk_pgrid_cust_l/n2_clk_tds_io_cust/rtl/n2_clk_tds_io_cust.v
-v ../../../design/sys/iop/niu/rtl/mac_dummy_dft.v
-v ../../../design/sys/iop/niu/rtl/niu_zcp_macros.v
-v ../../../design/sys/iop/niu/rtl/niu_pio_macros.v
-y ../../../design/sys/iop/niu/rtl
-y ../../../design/sys/iop/niu/rtl
-v ../../../libs/n2sram/compiler/physical/n2_com_dp_128x42s_cust_l/n2_com_dp_128x42s_cust/rtl/n2_com_dp_128x42s_cust.v
-v ../../../libs/n2sram/compiler/physical/n2_com_dp_32x148s_cust_l/n2_com_dp_32x148s_cust/rtl/n2_com_dp_32x148s_cust.v
-v ../../../libs/n2sram/compiler/physical/n2_com_dp_64x148s_cust_l/n2_com_dp_64x148s_cust/rtl/n2_com_dp_64x148s_cust.v
-v ../../../libs/n2sram/cams/n2_niu_tc_128x200s_cust_l/n2_niu_tc_128x200s_cust/rtl/n2_niu_tc_128x200s_cust.v
-v ../../../libs/n2sram/dp/n2_niu_dp_1024x152s_cust_l/n2_niu_dp_1024x152s_cust/rtl/n2_niu_dp_1024x152s_cust.v
-v ../../../libs/n2sram/dp/n2_niu_dp_256x152s_cust_l/n2_niu_dp_256x152s_cust/rtl/n2_niu_dp_256x152s_cust.v
-v ../../../libs/n2sram/dp/n2_niu_dp_512x152s_cust_l/n2_niu_dp_512x152s_cust/rtl/n2_niu_dp_512x152s_cust.v
-v ../../../libs/n2sram/sp/n2_niu_sp_4096x9s_cust_l/n2_niu_sp_4096x9s_cust/rtl/n2_niu_sp_4096x9s_cust.v
// niu_gen_cdmspp_flist excludes ../../../verif/model/verilog/niu/sparse_mem_model/niu_mem_tasks.v
// niu_gen_cdmspp_flist excludes ../../../design/sys/iop/niu/rtl/timescale.v
../../../design/sys/iop/niu/rtl/niu_cam_128x200.v
../../../design/sys/iop/niu/rtl/niu.h
// niu_gen_cdmspp_flist excludes ../../../design/sys/iop/niu/rtl/niu_cpu.v
// niu_gen_cdmspp_flist excludes ../../../design/common/rtl/debug.v
// niu_gen_cdmspp_flist excludes ../../../design/sys/iop/niu/rtl/debug.v
../../../design/sys/iop/niu/rtl/niu_txc_reg_defines.h
../../../design/sys/iop/niu/rtl/txc_defines.h
../../../design/sys/iop/niu/rtl/niu_txc_dataFetch.v
../../../design/sys/iop/niu/rtl/niu_txc_portRequest.v
../../../design/sys/iop/niu/rtl/niu_txc_drr_arbiter.v
../../../design/sys/iop/niu/rtl/niu_txc_drr_engine.v
../../../design/sys/iop/niu/rtl/niu_txc_drr_context.v
../../../design/sys/iop/niu/rtl/niu_txc_mac_transfer.v
../../../design/sys/iop/niu/rtl/niu_txc_packetAssy.v
../../../design/sys/iop/niu/rtl/niu_txc_reAligner.v
../../../design/sys/iop/niu/rtl/niu_txc_packetEngine.v
../../../design/sys/iop/niu/rtl/niu_txc_dmaRegisters.v
../../../design/sys/iop/niu/rtl/niu_txc_portRegisters.v
../../../design/sys/iop/niu/rtl/niu_txc_RegisterControl.v
../../../design/sys/iop/niu/rtl/niu_txc_ControlRegs.v
../../../design/sys/iop/niu/rtl/niu_txc_Reset.v
../../../design/sys/iop/niu/rtl/niu_txc_debug.v
../../../design/sys/iop/niu/rtl/niu_txc_ecc_correct.v
../../../design/sys/iop/niu/rtl/niu_txc_ecc_syndrome.v
../../../design/sys/iop/niu/rtl/niu_txc_ecc_generate.v
../../../design/sys/iop/niu/rtl/niu_txc_ecc_engine.v
../../../design/sys/iop/niu/rtl/niu_txc_tdmc_context.v
../../../design/sys/iop/niu/rtl/niu_txc_tdmc_error.v
../../../design/sys/iop/niu/rtl/niu_txc_tdmc_ifc.v
../../../design/sys/iop/niu/rtl/niu_txc_meta_resp_ifc.v
../../../design/sys/iop/niu/rtl/niu_txc_mac_ifc.v
../../../design/sys/iop/niu/rtl/niu_txc.v
../../../design/sys/iop/niu/rtl/niu_ipp_sum_lib.h
../../../design/sys/iop/niu/rtl/niu_ipp.h
../../../design/sys/iop/niu/rtl/niu_zcp.h
../../../design/sys/iop/niu/rtl/fflp.h
../../../design/sys/iop/niu/rtl/niu_rxc.v
../../../design/sys/iop/niu/rtl/niu_ipp_top.v
../../../design/sys/iop/niu/rtl/niu_ipp_sum_lib.v
../../../design/sys/iop/niu/rtl/niu_ipp_sum_ctrl.v
../../../design/sys/iop/niu/rtl/niu_ipp_sum_data.v
../../../design/sys/iop/niu/rtl/niu_ipp_sum_unit.v
../../../design/sys/iop/niu/rtl/niu_ipp_lib.v
../../../design/sys/iop/niu/rtl/niu_ipp_load.v
../../../design/sys/iop/niu/rtl/niu_ipp_unload_dat.v
../../../design/sys/iop/niu/rtl/niu_ipp_hdr_fifo.v
../../../design/sys/iop/niu/rtl/niu_ipp_pkt_dsc.v
../../../design/sys/iop/niu/rtl/niu_ipp_ffl_arbiter.v
../../../design/sys/iop/niu/rtl/niu_ipp_slv.v
../../../design/sys/iop/niu/rtl/niu_ipp_dat_fifo_1ke.v
../../../design/sys/iop/niu/rtl/niu_ipp_unload_ctl_1ke.v
../../../design/sys/iop/niu/rtl/niu_ipp_1ke.v
../../../design/sys/iop/niu/rtl/niu_ipp_dmc_checker.v
../../../design/sys/iop/niu/rtl/niu_zcp.v
../../../design/sys/iop/niu/rtl/niu_zcp_fflp_intf.v
../../../design/sys/iop/niu/rtl/niu_zcp_ififo_sm.v
../../../design/sys/iop/niu/rtl/niu_zcp_ififo.v
../../../design/sys/iop/niu/rtl/niu_zcp_cfifo8KB.v
../../../design/sys/iop/niu/rtl/niu_zcp_tt.v
../../../design/sys/iop/niu/rtl/niu_zcp_tt_sm.v
../../../design/sys/iop/niu/rtl/niu_zcp_slv.v
../../../design/sys/iop/niu/rtl/niu_zcp_ram_access_sm.v
../../../design/sys/iop/niu/rtl/niu_zcp_handle_decoder.v
../../../design/sys/iop/niu/rtl/niu_zcp_debug.v
../../../design/sys/iop/niu/rtl/fflp.v
../../../design/sys/iop/niu/rtl/fflp_hdr_fifo.v
../../../design/sys/iop/niu/rtl/fflp_flow_fifo.v
../../../design/sys/iop/niu/rtl/fflp_hdr_dp.v
../../../design/sys/iop/niu/rtl/fflp_hdr_cntl.v
../../../design/sys/iop/niu/rtl/fflp_hdr.v
../../../design/sys/iop/niu/rtl/fflp_cam_sched.v
../../../design/sys/iop/niu/rtl/fflp_cam_srch_sm.v
../../../design/sys/iop/niu/rtl/fflp_cam_srch.v
../../../design/sys/iop/niu/rtl/fflp_ram_cntl.v
../../../design/sys/iop/niu/rtl/fflp_CRC32_D64.v
../../../design/sys/iop/niu/rtl/fflp_CRC16_D64.v
../../../design/sys/iop/niu/rtl/fflp_hash_func.v
../../../design/sys/iop/niu/rtl/fflp_fwd_mstr.v
../../../design/sys/iop/niu/rtl/fflp_cam_ram.v
../../../design/sys/iop/niu/rtl/fflp_fcram_arb.v
../../../design/sys/iop/niu/rtl/fflp_fcram_fwd_arb.v
../../../design/sys/iop/niu/rtl/fflp_fcram_sched.v
../../../design/sys/iop/niu/rtl/fflp_fcram_cntl_sm.v
../../../design/sys/iop/niu/rtl/fflp_fcram_cntl.v
../../../design/sys/iop/niu/rtl/fflp_merge_func.v
../../../design/sys/iop/niu/rtl/fflp_fcram_top.v
../../../design/sys/iop/niu/rtl/fflp_pio_if.v
../../../design/sys/iop/niu/rtl/fflp_sync2sys_clk.v
../../../design/sys/iop/niu/rtl/fflp_sync2fc_clk.v
../../../design/sys/iop/niu/rtl/niu_tcam.v
../../../design/sys/iop/niu/rtl/niu_pio.h
../../../design/sys/iop/niu/rtl/niu_pio.v
../../../design/sys/iop/niu/rtl/niu_pio_accepted_sm.v
../../../design/sys/iop/niu/rtl/niu_pio_fifo16d.v
../../../design/sys/iop/niu/rtl/niu_rw_ctl.v
../../../design/sys/iop/niu/rtl/niu_pio_regs.v
../../../design/sys/iop/niu/rtl/niu_pio_slv_decoder.v
../../../design/sys/iop/niu/rtl/niu_pio_fzc_slv_decoder.v
../../../design/sys/iop/niu/rtl/niu_pio_vdmc_decoder.v
../../../design/sys/iop/niu/rtl/niu_pio_ldgim_decoder.v
../../../design/sys/iop/niu/rtl/niu_pio_ldsv_decoder.v
../../../design/sys/iop/niu/rtl/niu_pio_imask0_decoder.v
../../../design/sys/iop/niu/rtl/niu_pio_imask1_decoder.v
../../../design/sys/iop/niu/rtl/niu_pio_decoder_6to64.v
../../../design/sys/iop/niu/rtl/niu_pio_rw_sm.v
../../../design/sys/iop/niu/rtl/niu_pio_ic.v
../../../design/sys/iop/niu/rtl/niu_pio_ldgn2group.v
../../../design/sys/iop/niu/rtl/niu_pio_scheduler64.v
../../../design/sys/iop/niu/rtl/niu_pio_ig_sm.v
../../../design/sys/iop/niu/rtl/niu_req_mux.v
../../../design/sys/iop/niu/rtl/niu_daisy_chain.v
../../../design/sys/iop/niu/rtl/niu_gnt_encoder.v
../../../design/sys/iop/niu/rtl/niu_pio_debug.v
../../../design/sys/iop/niu/rtl/niu_pio_virt_decode.v
../../../design/sys/iop/niu/rtl/niu_pio_ucb.v
../../../design/sys/iop/niu/rtl/niu_pio_ucb_in32.v
../../../design/sys/iop/niu/rtl/niu_pio_ucb_out32.v
../../../design/sys/iop/niu/rtl/xmac.h
../../../design/sys/iop/niu/rtl/pcs_define.h
../../../design/sys/iop/niu/rtl/mif.h
// niu_gen_cdmspp_flist excludes ../../../design/sys/iop/niu/rtl/mac.v
../../../design/sys/iop/mac/rtl/mac.v
-v ../../../design/sys/iop/niu/rtl/lib.v
../../../design/sys/iop/niu/rtl/mac_core.v
../../../design/sys/iop/niu/rtl/mac_2ports.v
../../../design/sys/iop/niu/rtl/sphy_dpath2.v
../../../design/sys/iop/niu/rtl/mac_reset_hdr.v
../../../design/sys/iop/niu/rtl/clkgen_mac.v
../../../design/sys/iop/niu/rtl/esr_ctl2.v
../../../design/sys/iop/niu/rtl/esr_bscan.v
../../../design/sys/iop/niu/rtl/phy_clock_2ports.v
../../../design/sys/iop/niu/rtl/mac_pio_intf.v
../../../design/sys/iop/niu/rtl/mac_clk_driver.v
../../../design/sys/iop/niu/rtl/xmac_2pcs_core.v
../../../design/sys/iop/niu/rtl/phy_dpath.v
../../../design/sys/iop/niu/rtl/n2_rxd_alatch.v
../../../design/sys/iop/niu/rtl/n2_txd_blatch.v
../../../design/sys/iop/niu/rtl/mif.v
../../../design/sys/iop/niu/rtl/mif_control_sm.v
../../../design/sys/iop/niu/rtl/mif_exec_sm.v
../../../design/sys/iop/niu/rtl/hedwig.v
../../../design/sys/iop/niu/rtl/xmac_2pcs_clk_mux.v
../../../design/sys/iop/niu/rtl/lfs.v
../../../design/sys/iop/niu/rtl/lfs_sm.v
../../../design/sys/iop/niu/rtl/address_decoder.v
../../../design/sys/iop/niu/rtl/xrlm_sm.v
../../../design/sys/iop/niu/rtl/rx_xdecap.v
../../../design/sys/iop/niu/rtl/xmac_fcs.v
../../../design/sys/iop/niu/rtl/crc_gen_xmii.v
../../../design/sys/iop/niu/rtl/rx_xmac.v
../../../design/sys/iop/niu/rtl/rx_xgmii_intf.v
../../../design/sys/iop/niu/rtl/sop_sm.v
../../../design/sys/iop/niu/rtl/rxfifo_load.v
../../../design/sys/iop/niu/rtl/srfifo_load.v
../../../design/sys/iop/niu/rtl/rxfifo_unload.v
../../../design/sys/iop/niu/rtl/xmac_slv.v
../../../design/sys/iop/niu/rtl/xmac_sync.v
../../../design/sys/iop/niu/rtl/xdeferral.v
../../../design/sys/iop/niu/rtl/xtlm_sm.v
../../../design/sys/iop/niu/rtl/txfifo_unload.v
../../../design/sys/iop/niu/rtl/txfifo_load.v
../../../design/sys/iop/niu/rtl/tx_xmac.v
../../../design/sys/iop/niu/rtl/tx_byte_counter.v
../../../design/sys/iop/niu/rtl/ipg_checker.v
../../../design/sys/iop/niu/rtl/tx_mii_gmii.v
../../../design/sys/iop/niu/rtl/rx_mii_gmii.v
../../../design/sys/iop/niu/rtl/mgrlm_sm.v
../../../design/sys/iop/niu/rtl/xmac.v
../../../design/sys/iop/niu/rtl/xpcs_define.v
../../../design/sys/iop/niu/rtl/xpcs.v
../../../design/sys/iop/niu/rtl/xpcs_dbg.v
../../../design/sys/iop/niu/rtl/xpcs_xgmii_dpath.v
../../../design/sys/iop/niu/rtl/xpcs_SYNC_CELL.v
../../../design/sys/iop/niu/rtl/xpcs_dpath.v
../../../design/sys/iop/niu/rtl/xpcs_pio.v
../../../design/sys/iop/niu/rtl/xpcs_sync.v
../../../design/sys/iop/niu/rtl/xpcs_rx.v
../../../design/sys/iop/niu/rtl/xpcs_tx_del.v
../../../design/sys/iop/niu/rtl/xpcs_tx_randomizer.v
../../../design/sys/iop/niu/rtl/xpcs_tx.v
../../../design/sys/iop/niu/rtl/xpcs_DEL05.v
../../../design/sys/iop/niu/rtl/xpcs_txio.v
../../../design/sys/iop/niu/rtl/xpcs_txio_pcs.v
../../../design/sys/iop/niu/rtl/xpcs_rxio.v
../../../design/sys/iop/niu/rtl/xpcs_rxio_ebuffer.v
../../../design/sys/iop/niu/rtl/xpcs_rxio_ebuffer_sm.v
../../../design/sys/iop/niu/rtl/xpcs_rxio_sync.v
../../../design/sys/iop/niu/rtl/xpcs_rxio_sync_decoder.v
../../../design/sys/iop/niu/rtl/xpcs_rxio_sync_deskew_fifo.v
../../../design/sys/iop/niu/rtl/xpcs_rxio_sync_fifo_ptr.v
../../../design/sys/iop/niu/rtl/xpcs_rxio_sync_sm.v
../../../design/sys/iop/niu/rtl/pcs.v
../../../design/sys/iop/niu/rtl/pcs_decoder.v
../../../design/sys/iop/niu/rtl/pcs_encoder.v
../../../design/sys/iop/niu/rtl/pcs_lfsr.v
../../../design/sys/iop/niu/rtl/pcs_link_config.v
../../../design/sys/iop/niu/rtl/pcs_rx_ctrl.v
../../../design/sys/iop/niu/rtl/pcs_rx_disparity.v
../../../design/sys/iop/niu/rtl/pcs_rx_dpath.v
../../../design/sys/iop/niu/rtl/pcs_sequence_detect.v
../../../design/sys/iop/niu/rtl/pcs_slave.v
../../../design/sys/iop/niu/rtl/pcs_tx_ctrl.v
../../../design/sys/iop/niu/rtl/pcs_tx_disparity.v
../../../design/sys/iop/niu/rtl/pcs_tx_dpath.v
-v ../../../design/sys/iop/niu/rtl/niu_mb0.v
-v ../../../design/sys/iop/niu/rtl/niu_mb1.v
-v ../../../design/sys/iop/niu/rtl/niu_mb2.v
-v ../../../design/sys/iop/niu/rtl/niu_mb3.v
-v ../../../design/sys/iop/niu/rtl/niu_mb4.v
-v ../../../design/sys/iop/niu/rtl/niu_mb5.v
-v ../../../design/sys/iop/niu/rtl/niu_mb6.v
-v ../../../design/sys/iop/niu/rtl/niu_mb7.v
../../../design/sys/iop/niu/rtl/niu_smx_define.h
../../../design/sys/iop/niu/rtl/niu_smx.v
../../../design/sys/iop/niu/rtl/niu_smx_ff_ctrl.v
../../../design/sys/iop/niu/rtl/niu_smx_ff_regfl.v
../../../design/sys/iop/niu/rtl/niu_smx_rdreq_dmc.v
../../../design/sys/iop/niu/rtl/niu_smx_regfl.v
../../../design/sys/iop/niu/rtl/niu_smx_req_ff.v
../../../design/sys/iop/niu/rtl/niu_smx_req_sii.v
../../../design/sys/iop/niu/rtl/niu_smx_req_sii_cr.v
../../../design/sys/iop/niu/rtl/niu_smx_resp_dmc.v
../../../design/sys/iop/niu/rtl/niu_smx_resp_ff.v
../../../design/sys/iop/niu/rtl/niu_smx_resp_rcvfile.v
../../../design/sys/iop/niu/rtl/niu_smx_resp_sio.v
../../../design/sys/iop/niu/rtl/niu_smx_sm_req_cmdreq.v
../../../design/sys/iop/niu/rtl/niu_smx_sm_req_datareq.v
../../../design/sys/iop/niu/rtl/niu_smx_sm_req_dv.v
../../../design/sys/iop/niu/rtl/niu_smx_sm_req_siiarb.v
../../../design/sys/iop/niu/rtl/niu_smx_sm_req_siireq.v
../../../design/sys/iop/niu/rtl/niu_smx_sm_resp_cmdlaunch.v
../../../design/sys/iop/niu/rtl/niu_smx_sm_resp_cmdproc.v
../../../design/sys/iop/niu/rtl/niu_smx_sm_resp_dv.v
../../../design/sys/iop/niu/rtl/niu_smx_wreq_dmc.v
../../../design/sys/iop/niu/rtl/niu_smx_xtb.v
../../../design/sys/iop/niu/rtl/niu_smx_ecc16_genpar.v
../../../design/sys/iop/niu/rtl/niu_smx_ecc16_corr.v
../../../design/sys/iop/niu/rtl/niu_smx_gen_siudp.v
../../../design/sys/iop/niu/rtl/niu_smx_regflag.v
../../../design/sys/iop/niu/rtl/niu_smx_status.v
../../../design/sys/iop/niu/rtl/niu_smx_timer.v
../../../design/sys/iop/niu/rtl/niu_smx_timeout_hdlr.v
../../../design/sys/iop/niu/rtl/niu_smx_stall_hdlr.v
../../../design/sys/iop/niu/rtl/niu_smx_arb_2c.v
../../../design/sys/iop/niu/rtl/niu_smx_decode.v
../../../design/sys/iop/niu/rtl/niu_smx_ff_ram32x144.v
../../../design/sys/iop/niu/rtl/niu_smx_pio.v
../../../design/sys/iop/niu/rtl/niu_rdmc.h
../../../design/sys/iop/niu/rtl/niu_rdmc_pio_if.v
../../../design/sys/iop/niu/rtl/niu_rdmc_encode_32.v
../../../design/sys/iop/niu/rtl/niu_rdmc_pri_encode_32.v
../../../design/sys/iop/niu/rtl/niu_rdmc_barrel_shl_32.v
../../../design/sys/iop/niu/rtl/niu_rdmc_cache_acc_ctrl.v
../../../design/sys/iop/niu/rtl/niu_rdmc_desp_acc_ctrl.v
../../../design/sys/iop/niu/rtl/niu_rdmc_shadow_ram_ctrl.v
../../../design/sys/iop/niu/rtl/niu_rdmc_rcr_acc_ctrl.v
../../../design/sys/iop/niu/rtl/niu_rdmc_rr_arbiter.v
../../../design/sys/iop/niu/rtl/niu_rdmc_wr_dp_sm.v
../../../design/sys/iop/niu/rtl/niu_rdmc_wr_sched.v
../../../design/sys/iop/niu/rtl/niu_rdmc_wr_dp.v
../../../design/sys/iop/niu/rtl/niu_rdmc_dp_master.v
../../../design/sys/iop/niu/rtl/niu_rdmc_buf_manager.v
../../../design/sys/iop/niu/rtl/niu_rdmc_fetch_desp_sm.v
../../../design/sys/iop/niu/rtl/niu_rdmc_chnl_pio_if.v
../../../design/sys/iop/niu/rtl/niu_rdmc_rcr_manager.v
../../../design/sys/iop/niu/rtl/niu_rdmc_chnl_master.v
../../../design/sys/iop/niu/rtl/niu_rdmc_clk_buf.v
../../../design/sys/iop/niu/rtl/niu_rdmc.v
../../../design/sys/iop/niu/rtl/niu_dmc_reg_defines.h
../../../design/sys/iop/niu/rtl/niu_tdmc.v
../../../design/sys/iop/niu/rtl/niu_dmc_txcif.v
../../../design/sys/iop/niu/rtl/niu_dmc_dmaarb.v
../../../design/sys/iop/niu/rtl/niu_dmc_txpios.v
../../../design/sys/iop/niu/rtl/niu_dmc_cache_dataFetch.v
../../../design/sys/iop/niu/rtl/niu_tdmc_cachewrite.v
../../../design/sys/iop/niu/rtl/niu_tdmc_cacheread.v
../../../design/sys/iop/niu/rtl/niu_tdmc_addrcalc.v
../../../design/sys/iop/niu/rtl/niu_tdmc_cachefetch.v
../../../design/sys/iop/niu/rtl/niu_tdmc_dmacontext.v
../../../design/sys/iop/niu/rtl/niu_tdmc_mbox.v
../../../design/sys/iop/niu/rtl/niu_tdmc_sendmbox.v
../../../design/sys/iop/niu/rtl/niu_tdmc_mbox_context.v
../../../design/sys/iop/niu/rtl/niu_tdmc_cacheparity.v
../../../design/sys/iop/niu/rtl/niu_tdmc_reset.v
../../../design/sys/iop/niu/rtl/niu_tdmc_debug.v
../../../design/sys/iop/niu/rtl/niu_dmc_txcache.v
../../../design/sys/iop/niu/rtl/niu_tdmc_dmaregs.v
../../../design/sys/iop/niu/rtl/niu_tdmc_piodecodes.v
../../../design/sys/iop/niu/rtl/niu_meta_arb_define.h
../../../design/sys/iop/niu/rtl/niu_meta_rd_tagfifo.v
../../../design/sys/iop/niu/rtl/niu_meta_wr_tagfifo.v
../../../design/sys/iop/niu/rtl/niu_rd_meta_arb.v
../../../design/sys/iop/niu/rtl/niu_wr_meta_arb.v
../../../design/sys/iop/niu/rtl/niu_meta_arb_reset.v
../../../design/sys/iop/niu/rtl/niu_meta_arb_syncfifo.v
../../../design/sys/iop/niu/rtl/niu_meta_arb_dbg.v
../../../design/sys/iop/niu/rtl/niu_meta_arb.v
../../../design/sys/iop/rtx/rtl/rtx.v
../../../design/sys/iop/rtx/rtl/clkgen_rtx.v
../../../design/sys/iop/rtx/rtl/rtx_dmo_mux.v
-v ../../../design/sys/iop/rtx/rtl/rtx_n2_efuhdr1a_p0_ctl.v
-v ../../../design/sys/iop/rtx/rtl/rtx_n2_efuhdr1a_p1_ctl.v
-v ../../../design/sys/iop/rtx/rtl/rtx_n2_efuhdr1b_p0_ctl.v
-v ../../../design/sys/iop/rtx/rtl/rtx_n2_efuhdr1b_p1_ctl.v
-v ../../../design/sys/iop/rtx/rtl/rtx_n2_efuhdr3_p0_ctl.v
-v ../../../design/sys/iop/rtx/rtl/rtx_n2_efuhdr3_p1_ctl.v
-v ../../../design/sys/iop/rtx/rtl/rtx_n2_efuhdr6_ctl.v
-v ../../../design/sys/iop/rtx/rtl/rtx_n2_efuhdr7_p0_ctl.v
-v ../../../design/sys/iop/rtx/rtl/rtx_n2_efuhdr7_p1_ctl.v
-v ../../../design/sys/iop/rdp/rtl/rdp_n2_efuhdr4a_ctl.v
-v ../../../design/sys/iop/rdp/rtl/rdp_n2_efuhdr4b_ctl.v
-v ../../../design/sys/iop/tds/rtl/tds_n2_efuhdr2_ctl.v
../../../design/sys/iop/rdp/rtl/rdp.v
../../../design/sys/iop/rdp/rtl/rdp_clkgen_rdp_io.v
../../../design/sys/iop/rdp/rtl/rdp_clkgen_rdp_io2x.v
../../../design/sys/iop/rdp/rtl/rdp_dmoreg.v
../../../design/sys/iop/tds/rtl/tds.v
../../../design/sys/iop/tds/rtl/tds_l2l1clk_io.v
../../../design/sys/iop/tds/rtl/dmo_regs.v
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/vera/include/neptune_defines.vri
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/vera/include/niu_seeding.vri
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/vera/include/niu_verilog_tasks.vri
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/vera/include/niu_plusArgMacros.vri
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/vera/top/vera_top.vr
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/vera/top/cosim_tasks.vr
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/verilog/neptune_defines.h
// niu_gen_cdmspp_flist excludes ../../../verif/env/common/vera/niu_randoms/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/common/vera/niu_gen_pio/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/common/vera/niu_coverage/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/common/vera/niu_intr/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/common/vera/niu_gen_error/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/common/pli/niu_pli/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/common/vera/niu_ippktgen/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/common/vera/niu_ippktgen/C/wrapper/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/common/vera/niu_ippktgen/C/libnet/include/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/common/vera/niu_ippktgen/C/libnet/src/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/dmc_sat/vera/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/mac_sat/vera/lib/niu_mac_checker/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/rxc_sat/vera/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/rxc_sat/vera/fflp/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/rxc_sat/vera/rxdma/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/rxc_sat/vera/pktconfig/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/rxc_sat/vera/drivers/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/rxc_sat/vera/checkers/dmc_rxc_checker/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/rxc_sat/vera/checkers/mem_checker/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/rxc_sat/vera/checkers/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/rxc_sat/vera/monitor/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/txc_sat/vera/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/vera/dmc_utils/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/vera/niu_tokens/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/vera/ncu_drv/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/vera/niu_pio/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/vera/niu_utils/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/vera/smx_drv/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/model/verilog/niu/sparse_mem_model/pli/src/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/vera/Makefile
// niu_gen_cdmspp_flist excludes ../../../verif/env/niu/verilog/n2_niu_tb_top.v
// niu_gen_cdmspp_flist excludes ../../../verif/model/verilog/niu/niu_enet_models/enet_models.v
// niu_gen_cdmspp_flist excludes ../../../verif/model/verilog/niu/niu_enet_models/enet_models.vp
// niu_gen_cdmspp_flist excludes ../../../verif/model/verilog/niu/niu_enet_models/enet_models_wdsds.v
// niu_gen_cdmspp_flist excludes ../../../verif/model/verilog/niu/niu_enet_models/enet_models_wdsds.vp
// niu_gen_cdmspp_flist excludes ../../../verif/model/verilog/niu/niu_enet_models/serdes_dummy1.v
// niu_gen_cdmspp_flist excludes ../../../verif/model/verilog/niu/niu_enet_models/serdes_dummy.v
// niu_gen_cdmspp_flist excludes ../../../verif/model/verilog/niu/niu_enet_models/phy_clock_doubler_env.v
// niu_gen_cdmspp_flist excludes ../../../verif/model/verilog/niu/niu_enet_models/port_clk.v
// niu_gen_cdmspp_flist excludes ../../../verif/model/verilog/niu/niu_enet_models/rgmii_mux.v
// niu_gen_cdmspp_flist excludes ../../../verif/model/verilog/niu/niu_enet_models/unh_checker.v
// niu_gen_cdmspp_flist excludes ../../../verif/model/verilog/niu/niu_enet_models/xaui_decode.v
// niu_gen_cdmspp_flist excludes ../../../verif/model/verilog/niu/niu_enet_models/xgmii_if.v
// niu_gen_cdmspp_flist excludes ../../../verif/model/verilog/niu/niu_enet_models/xgmii_rx_decoder.v
// niu_gen_cdmspp_flist excludes ../../../verif/model/verilog/niu/niu_enet_models/xgmii_tx_encoder.v
// niu_gen_cdmspp_flist excludes ../../../verif/model/verilog/niu/niu_enet_models/xgmii_tx_encoder_top.v
// niu_gen_cdmspp_flist excludes ../../../verif/model/verilog/niu/niu_enet_models/bw_calc.v
projects / OpenSPARC-T2-DV / blob