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* OpenSPARC T2 Processor File: n2_err_l2_LTC_2bnk_cecc_trap.s
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* ========== Copyright Header End ============================================
#define MAIN_PAGE_HV_ALSO
#define L2_ENTRY_PA 0xa400000000
#define TEST_DATA1 0x5555555555555555
#define L2_ENTRY_PA0 0x2020000008
#define L2_ES_W1C_VALUE 0xc03ffff800000000
! Boot code does not provide TLB translation for IO address space
ldxa [%g0] ASI_LSU_CONTROL, %l0
stxa %l0, [%g0] ASI_LSU_CONTROL
setx L2_ES_W1C_VALUE, %l0, %l1
set_L2_Directly_Mapped_Mode:
setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register
setx TEST_DATA1, %l0, %g5
set 0xaa80f100, %g2 ! bits [16:8] select index in 4 bank mode
setx 0xa40003c400,%l0,%g5 ! bits [17:9] select index in 4 bank mode
! Flip one bits to inject error
reading_back_0: !Load to L2 again to get the LTC logged in ESR
set 0xaaa0f100, %g2 ! bits [16:8] selects index in 4 bank mode
load_toprev_index_no_LTC:
set 0xaa80f100, %g2 ! bits [16:8] select index in 4 bank mode
set 0xaa80f100, %g2 ! bits [16:8] select index in 4 bank mode
! Check if a Corrected ECC Trap happened
mov TT_Corrected_ECC, %l0
/*******************************************************
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