verif/env/common/coverage/dmu/sio_dmu_sample.vrhpal

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// OpenSPARC T2 Processor File: sio_dmu_sample.vrhpal
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#inc "dmu_cov_inc.pal";

// sio_dmu_this_cmd is ignored by DSN, any hdr_vld indicates dma rd return
// hdr_vld is covered by the other sio egress VCO's

// DMCTag[15] = 0 for DMA/Int (DI) = 1 for DMA Tablewalk (TW)
sample dmu_siu_intf_eHdr_Cmd_cov (dmu_id_out[15])
{
  state DI (1'b0);
  state TW (1'b1);
  cov_weight = 0;
}

sample dmu_siu_intf_eHdr_UE_cov (sio_dmu_rd_return_ue)
{
  m_state UE (0:1);
  cov_weight = 0;
}

sample dmu_siu_intf_eHdr_DE_cov (sio_dmu_rd_return_de)
{
  m_state DE (0:1);
  cov_weight = 0;
}

// make sure all bits of the dmc tag field are toggled.
// Exclude bit [15] because that determines DI or TW
sample dmu_siu_intf_eHdr_DMCtag_cov (dmu_id_out[14:0])
{
. &toggle(15);
  cov_weight = 0;
}

sample dmu_siu_intf_eHdr_CtagECC_cov (sio_dmu_rd_return_ctagecc)
{
. &toggle(6);
  cov_weight = 0;
}

cross dmu_siu_intf_eHdr_Cmd_UE_cross (dmu_siu_intf_eHdr_Cmd_cov,
                                      dmu_siu_intf_eHdr_UE_cov);

cross dmu_siu_intf_eHdr_Cmd_DE_cross (dmu_siu_intf_eHdr_Cmd_cov,
                                      dmu_siu_intf_eHdr_DE_cov);

cross dmu_siu_intf_eHdr_Cmd_DMCtag_cross (dmu_siu_intf_eHdr_Cmd_cov,
                                          dmu_siu_intf_eHdr_DMCtag_cov);

cross dmu_siu_intf_eHdr_Cmd_CtagECC_cross (dmu_siu_intf_eHdr_Cmd_cov,
                                           dmu_siu_intf_eHdr_CtagECC_cov);