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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / legion / src / devices / mem_bus / libpiu / piu.h
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AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: piu.h
5* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
6* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
7*
8* The above named program is free software; you can redistribute it and/or
9* modify it under the terms of the GNU General Public
10* License version 2 as published by the Free Software Foundation.
11*
12* The above named program is distributed in the hope that it will be
13* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
14* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15* General Public License for more details.
16*
17* You should have received a copy of the GNU General Public
18* License along with this work; if not, write to the Free Software
19* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
20*
21* ========== Copyright Header End ============================================
22*/
23/*
24 * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
25 * Use is subject to license terms.
26 */
27
28#ifndef _PIU_H
29#define _PIU_H
30
31#pragma ident "@(#)piu.h 1.8 06/10/05 SMI"
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
37#include "niagara2_device.h"
38
39
40/*
41 * PCIE CSRs implemented by Niagara 2
42 */
43#define MAX_PCIE_REGX 1706
44#define NUM_PCIE_CSRS 146
45#define UND_PCIE_CSRS -1
46
47typedef enum PCIE_CSR pcie_csr_t;
48typedef struct PCIE_CSR_DESC pcie_csr_desc_t;
49
50
51enum PCIE_CSR {
52 PIU_Interrupt_Mapping_Registers,
53 PIU_Interrupt_Clear_Registers,
54 PIU_Interrupt_Retry_Timer_Register,
55 PIU_Interrupt_State_Status_Register_1,
56 PIU_Interrupt_State_Status_Register_2,
57 PIU_INTX_Status_Register,
58 PIU_INT_A_Clear_Register,
59 PIU_INT_B_Clear_Register,
60 PIU_INT_C_Clear_Register,
61 PIU_INT_D_Clear_Register,
62 PIU_Event_Queue_Base_Address_Register,
63 PIU_Event_Queue_Control_Set_Register,
64 PIU_Event_Queue_Control_Clear_Register,
65 PIU_Event_Queue_State_Register,
66 PIU_Event_Queue_Tail_Register,
67 PIU_Event_Queue_Head_Register,
68 PIU_MSI_Mapping_Register,
69 PIU_MSI_Clear_Registers,
70 PIU_Interrupt_Mondo_Data_0_Register,
71 PIU_Interrupt_Mondo_Data_1_Register,
72 PIU_ERR_COR_Mapping_Register,
73 PIU_ERR_NONFATAL_Mapping_Register,
74 PIU_ERR_FATAL_Mapping_Register,
75 PIU_PM_PME_Mapping_Register,
76 PIU_PME_To_ACK_Mapping_Register,
77 PIU_IMU_Error_Log_Enable_Register,
78 PIU_IMU_Interrupt_Enable_Register,
79 PIU_IMU_Interrupt_Status_Register,
80 PIU_IMU_Error_Status_Clear_Register,
81 PIU_IMU_Error_Status_Set_Register,
82 PIU_IMU_RDS_Error_Log_Register,
83 PIU_IMU_SCS_Error_Log_Register,
84 PIU_IMU_EQS_Error_Log_Register,
85 PIU_DMC_Core_and_Block_Interrupt_Enable_Register,
86 PIU_DMC_Core_and_Block_Error_Status_Register,
87 PIU_IMU_Performance_Counter_Select_Register,
88 PIU_IMU_Performance_Counter_Zero_Register,
89 PIU_IMU_Performance_Counter_One_Register,
90 PIU_MSI_32_bit_Address_Register,
91 PIU_MSI_64_bit_Address_Register,
92 PIU_Mem_64_PCIE_Offset_Register,
93 PIU_MMU_Control_and_Status_Register,
94 PIU_MMU_TSB_Control_Register,
95 PIU_MMU_TTE_Cache_Invalidate_Register,
96 PIU_MMU_Error_Log_Enable_Register,
97 PIU_MMU_Interrupt_Enable_Register,
98 PIU_MMU_Interrupt_Status_Register,
99 PIU_MMU_Error_Status_Clear_Register,
100 PIU_MMU_Error_Status_Set_Register,
101 PIU_MMU_Translation_Fault_Address_Register,
102 PIU_MMU_Translation_Fault_Status_Register,
103 PIU_MMU_Performance_Counter_Select_Register,
104 PIU_MMU_Performance_Counter_Zero_Register,
105 PIU_MMU_Performance_Counter_One_Register,
106 PIU_MMU_TTE_Cache_Virtual_Tag_Registers,
107 PIU_MMU_TTE_Cache_Physical_Tag_Registers,
108 PIU_MMU_TTE_Cache_Data_Registers,
109 PIU_MMU_DEV2IOTSB_Registers,
110 PIU_MMU_IOTSBDESC_Registers,
111 PIU_ILU_Error_Log_Enable_Register,
112 PIU_ILU_Interrupt_Enable_Register,
113 PIU_ILU_Interrupt_Status_Register,
114 PIU_ILU_Error_Status_Clear_Register,
115 PIU_ILU_Error_Status_Set_Register,
116 PIU_PEU_Core_and_Block_Interrupt_Enable_Register,
117 PIU_PEU_Core_and_Block_Interrupt_Status_Register,
118 PIU_ILU_Diagnostic_Register,
119 PIU_DMU_Debug_Select_Register_for_DMU_Debug_Bus_A,
120 PIU_DMU_Debug_Select_Register_for_DMU_Debug_Bus_B,
121 PIU_DMU_PCI_Express_Configuration_Register,
122 PIU_Packet_Scoreboard_DMA_Register_Set,
123 PIU_Packet_Scoreboard_PIO_Register_Set,
124 PIU_Transaction_Scoreboard_Register_Set,
125 PIU_Transaction_Scoreboard_Status_Register,
126 PIU_PEU_Control_Register,
127 PIU_PEU_Status_Register,
128 PIU_PEU_PME_Turn_Off_Generate_Register,
129 PIU_PEU_Ingress_Credits_Initial_Register,
130 PIU_PEU_Diagnostic_Register,
131 PIU_PEU_Egress_Credits_Consumed_Register,
132 PIU_PEU_Egress_Credit_Limit_Register,
133 PIU_PEU_Egress_Retry_Buffer_Register,
134 PIU_PEU_Ingress_Credits_Allocated_Register,
135 PIU_PEU_Ingress_Credits_Received_Register,
136 PIU_PEU_Other_Event_Log_Enable_Register,
137 PIU_PEU_Other_Event_Interrupt_Enable_Register,
138 PIU_PEU_Other_Event_Interrupt_Status_Register,
139 PIU_PEU_Other_Event_Status_Clear_Register,
140 PIU_PEU_Other_Event_Status_Set_Register,
141 PIU_PEU_Receive_Other_Event_Header1_Log_Register,
142 PIU_PEU_Receive_Other_Event_Header2_Log_Register,
143 PIU_PEU_Transmit_Other_Event_Header1_Log_Register,
144 PIU_PEU_Transmit_Other_Event_Header2_Log_Register,
145 PIU_PEU_Performance_Counter_Select_Register,
146 PIU_PEU_Performance_Counter_Zero_Register,
147 PIU_PEU_Performance_Counter_One_Register,
148 PIU_PEU_Performance_Counter_Two_Register,
149 PIU_PEU_Debug_Select_A_Register,
150 PIU_PEU_Debug_Select_B_Register,
151 PIU_PEU_Device_Capabilities_Register,
152 PIU_PEU_Device_Control_Register,
153 PIU_PEU_Device_Status_Register,
154 PIU_PEU_Link_Capabilities_Register,
155 PIU_PEU_Link_Control_Register,
156 PIU_PEU_Link_Status_Register,
157 PIU_PEU_Slot_Capabilities_Register,
158 PIU_PEU_Uncorrectable_Error_Log_Enable_Register,
159 PIU_PEU_Uncorrectable_Error_Interrupt_Enable_Register,
160 PIU_PEU_Uncorrectable_Error_Interrupt_Status_Register,
161 PIU_PEU_Uncorrectable_Error_Status_Clear_Register,
162 PIU_PEU_Uncorrectable_Error_Status_Set_Register,
163 PIU_PEU_Receive_Uncorrectable_Error_Header1_Log_Register,
164 PIU_PEU_Receive_Uncorrectable_Error_Header2_Log_Register,
165 PIU_PEU_Transmit_Uncorrectable_Error_Header1_Log_Register,
166 PIU_PEU_Transmit_Uncorrectable_Error_Header2_Log_Register,
167 PIU_PEU_Correctable_Error_Log_Enable_Register,
168 PIU_PEU_Correctable_Error_Interrupt_Enable_Register,
169 PIU_PEU_Correctable_Error_Interrupt_Status_Register,
170 PIU_PEU_Correctable_Error_Status_Clear_Register,
171 PIU_PEU_Correctable_Error_Status_Set_Register,
172 PIU_PEU_CXPL_SERDES_Revision_Register,
173 PIU_PEU_CXPL_AckNak_Latency_Threshold_Register,
174 PIU_PEU_CXPL_AckNak_Latency_Timer_Register,
175 PIU_PEU_CXPL_Replay_Timer_Threshold_Register,
176 PIU_PEU_CXPL_Replay_Timer_Register,
177 PIU_PEU_CXPL_Vendor_DLLP_Message_Register,
178 PIU_PEU_CXPL_LTSSM_Control_Register,
179 PIU_PEU_CXPL_DLL_Control_Register,
180 PIU_PEU_CXPL_MACL_PCS_Control_Register,
181 PIU_PEU_CXPL_MACL_Lane_Skew_Control_Register,
182 PIU_PEU_CXPL_MACL_Symbol_Number_Register,
183 PIU_PEU_CXPL_MACL_Symbol_Timer_Register,
184 PIU_PEU_CXPL_Core_Status_Register,
185 PIU_PEU_CXPL_Event_Error_Log_Enable_Register,
186 PIU_PEU_CXPL_Event_Error_Interrupt_Enable_Register,
187 PIU_PEU_CXPL_Event_Error_Interrupt_Status_Register,
188 PIU_PEU_CXPL_Event_Error_Status_Clear_Register,
189 PIU_PEU_CXPL_Event_Error_Set_Register,
190 PIU_PEU_Link_Bit_Error_Counter_I_Register,
191 PIU_PEU_Link_Bit_Error_Counter_II_Register,
192 PIU_PEU_SERDES_PLL_Control_Register,
193 PIU_PEU_SERDES_Receiver_Lane_Control_Register,
194 PIU_PEU_SERDES_Receiver_Lane_Status_Register,
195 PIU_PEU_SERDES_Transmitter_Control_Register,
196 PIU_PEU_SERDES_Transmitter_Status_Register,
197 PIU_PEU_SERDES_Test_Configuration_Register
198};
199
200/*
201 * CSR descrptor, used to specify each of the PCIE CSRs implemented
202 * by Niagara 2 PIU
203 */
204struct PCIE_CSR_DESC {
205 int offset;
206 int nwords;
207 int regx;
208 const char *name;
209};
210
211
212pcie_csr_desc_t pcie_csrs[NUM_PCIE_CSRS] = {
213 {0x6010a0, 44, 0, "PIU_Interrupt_Mapping_Registers"},
214 {0x6014a0, 44, 44, "PIU_Interrupt_Clear_Registers"},
215 {0x601a00, 1, 88, "PIU_Interrupt_Retry_Timer_Register"},
216 {0x601a10, 1, 89, "PIU_Interrupt_State_Status_Register_1"},
217 {0x601a18, 1, 90, "PIU_Interrupt_State_Status_Register_2"},
218 {0x60b000, 1, 91, "PIU_INTX_Status_Register"},
219 {0x60b008, 1, 92, "PIU_INT_A_Clear_Register"},
220 {0x60b010, 1, 93, "PIU_INT_B_Clear_Register"},
221 {0x60b018, 1, 94, "PIU_INT_C_Clear_Register"},
222 {0x60b020, 1, 95, "PIU_INT_D_Clear_Register"},
223 {0x610000, 1, 96, "PIU_Event_Queue_Base_Address_Register"},
224 {0x611000, 36, 97, "PIU_Event_Queue_Control_Set_Register"},
225 {0x611200, 36, 133, "PIU_Event_Queue_Control_Clear_Register"},
226 {0x611400, 36, 169, "PIU_Event_Queue_State_Register"},
227 {0x611600, 36, 205, "PIU_Event_Queue_Tail_Register"},
228 {0x611800, 36, 241, "PIU_Event_Queue_Head_Register"},
229 {0x620000, 256, 277, "PIU_MSI_Mapping_Register"},
230 {0x628000, 256, 533, "PIU_MSI_Clear_Registers"},
231 {0x62c000, 1, 789, "PIU_Interrupt_Mondo_Data_0_Register"},
232 {0x62c008, 1, 790, "PIU_Interrupt_Mondo_Data_1_Register"},
233 {0x630000, 1, 791, "PIU_ERR_COR_Mapping_Register"},
234 {0x630008, 1, 792, "PIU_ERR_NONFATAL_Mapping_Register"},
235 {0x630010, 1, 793, "PIU_ERR_FATAL_Mapping_Register"},
236 {0x630018, 1, 794, "PIU_PM_PME_Mapping_Register"},
237 {0x630020, 1, 795, "PIU_PME_To_ACK_Mapping_Register"},
238 {0x631000, 1, 796, "PIU_IMU_Error_Log_Enable_Register"},
239 {0x631008, 1, 797, "PIU_IMU_Interrupt_Enable_Register"},
240 {0x631010, 1, 798, "PIU_IMU_Interrupt_Status_Register"},
241 {0x631018, 1, 799, "PIU_IMU_Error_Status_Clear_Register"},
242 {0x631020, 1, 800, "PIU_IMU_Error_Status_Set_Register"},
243 {0x631028, 1, 801, "PIU_IMU_RDS_Error_Log_Register"},
244 {0x631030, 1, 802, "PIU_IMU_SCS_Error_Log_Register"},
245 {0x631038, 1, 803, "PIU_IMU_EQS_Error_Log_Register"},
246 {0x631800, 1, 804, "PIU_DMC_Core_and_Block_Interrupt_Enable_Register"},
247 {0x631808, 1, 805, "PIU_DMC_Core_and_Block_Error_Status_Register"},
248 {0x632000, 1, 806, "PIU_IMU_Performance_Counter_Select_Register"},
249 {0x632008, 1, 807, "PIU_IMU_Performance_Counter_Zero_Register"},
250 {0x632010, 1, 808, "PIU_IMU_Performance_Counter_One_Register"},
251 {0x634000, 1, 809, "PIU_MSI_32_bit_Address_Register"},
252 {0x634008, 1, 810, "PIU_MSI_64_bit_Address_Register"},
253 {0x634018, 1, 811, "PIU_Mem_64_PCIE_Offset_Register"},
254 {0x640000, 1, 812, "PIU_MMU_Control_and_Status_Register"},
255 {0x640008, 1, 813, "PIU_MMU_TSB_Control_Register"},
256 {0x640108, 1, 814, "PIU_MMU_TTE_Cache_Invalidate_Register"},
257 {0x641000, 1, 815, "PIU_MMU_Error_Log_Enable_Register"},
258 {0x641008, 1, 816, "PIU_MMU_Interrupt_Enable_Register"},
259 {0x641010, 1, 817, "PIU_MMU_Interrupt_Status_Register"},
260 {0x641018, 1, 818, "PIU_MMU_Error_Status_Clear_Register"},
261 {0x641020, 1, 819, "PIU_MMU_Error_Status_Set_Register"},
262 {0x641028, 1, 820, "PIU_MMU_Translation_Fault_Address_Register"},
263 {0x641030, 1, 821, "PIU_MMU_Translation_Fault_Status_Register"},
264 {0x642000, 1, 822, "PIU_MMU_Performance_Counter_Select_Register"},
265 {0x642008, 1, 823, "PIU_MMU_Performance_Counter_Zero_Register"},
266 {0x642010, 1, 824, "PIU_MMU_Performance_Counter_One_Register"},
267 {0x646000, 64, 825, "PIU_MMU_TTE_Cache_Virtual_Tag_Registers"},
268 {0x647000, 64, 889, "PIU_MMU_TTE_Cache_Physical_Tag_Registers"},
269 {0x648000, 512, 953, "PIU_MMU_TTE_Cache_Data_Registers"},
270 {0x649000, 16, 1465, "PIU_MMU_DEV2IOTSB_Registers"},
271 {0x649100, 32, 1481, "PIU_MMU_IOTSBDESC_Registers"},
272 {0x651000, 1, 1513, "PIU_ILU_Error_Log_Enable_Register"},
273 {0x651008, 1, 1514, "PIU_ILU_Interrupt_Enable_Register"},
274 {0x651010, 1, 1515, "PIU_ILU_Interrupt_Status_Register"},
275 {0x651018, 1, 1516, "PIU_ILU_Error_Status_Clear_Register"},
276 {0x651020, 1, 1517, "PIU_ILU_Error_Status_Set_Register"},
277 {0x651800, 1, 1518, "PIU_PEU_Core_and_Block_Interrupt_Enable_Register"},
278 {0x651808, 1, 1519, "PIU_PEU_Core_and_Block_Interrupt_Status_Register"},
279 {0x652000, 1, 1520, "PIU_ILU_Diagnostic_Register"},
280 {0x653000, 1, 1521, "PIU_DMU_Debug_Select_Register_for_DMU_Debug_Bus_A"},
281 {0x653008, 1, 1522, "PIU_DMU_Debug_Select_Register_for_DMU_Debug_Bus_B"},
282 {0x653100, 1, 1523, "PIU_DMU_PCI_Express_Configuration_Register"},
283 {0x660000, 32, 1524, "PIU_Packet_Scoreboard_DMA_Register_Set"},
284 {0x664000, 16, 1556, "PIU_Packet_Scoreboard_PIO_Register_Set"},
285 {0x670000, 32, 1572, "PIU_Transaction_Scoreboard_Register_Set"},
286 {0x670100, 1, 1604, "PIU_Transaction_Scoreboard_Status_Register"},
287 {0x680000, 1, 1605, "PIU_PEU_Control_Register"},
288 {0x680008, 1, 1606, "PIU_PEU_Status_Register"},
289 {0x680010, 1, 1607, "PIU_PEU_PME_Turn_Off_Generate_Register"},
290 {0x680018, 1, 1608, "PIU_PEU_Ingress_Credits_Initial_Register"},
291 {0x680100, 1, 1609, "PIU_PEU_Diagnostic_Register"},
292 {0x680200, 1, 1610, "PIU_PEU_Egress_Credits_Consumed_Register"},
293 {0x680208, 1, 1611, "PIU_PEU_Egress_Credit_Limit_Register"},
294 {0x680210, 1, 1612, "PIU_PEU_Egress_Retry_Buffer_Register"},
295 {0x680218, 1, 1613, "PIU_PEU_Ingress_Credits_Allocated_Register"},
296 {0x680220, 1, 1614, "PIU_PEU_Ingress_Credits_Received_Register"},
297 {0x681000, 1, 1615, "PIU_PEU_Other_Event_Log_Enable_Register"},
298 {0x681008, 1, 1616, "PIU_PEU_Other_Event_Interrupt_Enable_Register"},
299 {0x681010, 1, 1617, "PIU_PEU_Other_Event_Interrupt_Status_Register"},
300 {0x681018, 1, 1618, "PIU_PEU_Other_Event_Status_Clear_Register"},
301 {0x681020, 1, 1619, "PIU_PEU_Other_Event_Status_Set_Register"},
302 {0x681028, 1, 1620, "PIU_PEU_Receive_Other_Event_Header1_Log_Register"},
303 {0x681030, 1, 1621, "PIU_PEU_Receive_Other_Event_Header2_Log_Register"},
304 {0x681038, 1, 1622, "PIU_PEU_Transmit_Other_Event_Header1_Log_Register"},
305 {0x681040, 1, 1623, "PIU_PEU_Transmit_Other_Event_Header2_Log_Register"},
306 {0x682000, 1, 1624, "PIU_PEU_Performance_Counter_Select_Register"},
307 {0x682008, 1, 1625, "PIU_PEU_Performance_Counter_Zero_Register"},
308 {0x682010, 1, 1626, "PIU_PEU_Performance_Counter_One_Register"},
309 {0x682018, 1, 1627, "PIU_PEU_Performance_Counter_Two_Register"},
310 {0x683000, 1, 1628, "PIU_PEU_Debug_Select_A_Register"},
311 {0x683008, 1, 1629, "PIU_PEU_Debug_Select_B_Register"},
312 {0x690000, 1, 1630, "PIU_PEU_Device_Capabilities_Register"},
313 {0x690008, 1, 1631, "PIU_PEU_Device_Control_Register"},
314 {0x690010, 1, 1632, "PIU_PEU_Device_Status_Register"},
315 {0x690018, 1, 1633, "PIU_PEU_Link_Capabilities_Register"},
316 {0x690020, 1, 1634, "PIU_PEU_Link_Control_Register"},
317 {0x690028, 1, 1635, "PIU_PEU_Link_Status_Register"},
318 {0x690030, 1, 1636, "PIU_PEU_Slot_Capabilities_Register"},
319 {0x691000, 1, 1637, "PIU_PEU_Uncorrectable_Error_Log_Enable_Register"},
320 {0x691008, 1, 1638, "PIU_PEU_Uncorrectable_Error_Interrupt_Enable_Register"},
321 {0x691010, 1, 1639, "PIU_PEU_Uncorrectable_Error_Interrupt_Status_Register"},
322 {0x691018, 1, 1640, "PIU_PEU_Uncorrectable_Error_Status_Clear_Register"},
323 {0x691020, 1, 1641, "PIU_PEU_Uncorrectable_Error_Status_Set_Register"},
324 {0x691028, 1, 1642, "PIU_PEU_Receive_Uncorrectable_Error_Header1_Log_Register"},
325 {0x691030, 1, 1643, "PIU_PEU_Receive_Uncorrectable_Error_Header2_Log_Register"},
326 {0x691038, 1, 1644, "PIU_PEU_Transmit_Uncorrectable_Error_Header1_Log_Register"},
327 {0x691040, 1, 1645, "PIU_PEU_Transmit_Uncorrectable_Error_Header2_Log_Register"},
328 {0x6a1000, 1, 1646, "PIU_PEU_Correctable_Error_Log_Enable_Register"},
329 {0x6a1008, 1, 1647, "PIU_PEU_Correctable_Error_Interrupt_Enable_Register"},
330 {0x6a1010, 1, 1648, "PIU_PEU_Correctable_Error_Interrupt_Status_Register"},
331 {0x6a1018, 1, 1649, "PIU_PEU_Correctable_Error_Status_Clear_Register"},
332 {0x6a1020, 1, 1650, "PIU_PEU_Correctable_Error_Status_Set_Register"},
333 {0x6e2000, 1, 1651, "PIU_PEU_CXPL_SERDES_Revision_Register"},
334 {0x6e2008, 1, 1652, "PIU_PEU_CXPL_AckNak_Latency_Threshold_Register"},
335 {0x6e2010, 1, 1653, "PIU_PEU_CXPL_AckNak_Latency_Timer_Register"},
336 {0x6e2018, 1, 1654, "PIU_PEU_CXPL_Replay_Timer_Threshold_Register"},
337 {0x6e2020, 1, 1655, "PIU_PEU_CXPL_Replay_Timer_Register"},
338 {0x6e2040, 1, 1656, "PIU_PEU_CXPL_Vendor_DLLP_Message_Register"},
339 {0x6e2050, 1, 1657, "PIU_PEU_CXPL_LTSSM_Control_Register"},
340 {0x6e2058, 1, 1658, "PIU_PEU_CXPL_DLL_Control_Register"},
341 {0x6e2060, 1, 1659, "PIU_PEU_CXPL_MACL_PCS_Control_Register"},
342 {0x6e2068, 1, 1660, "PIU_PEU_CXPL_MACL_Lane_Skew_Control_Register"},
343 {0x6e2070, 1, 1661, "PIU_PEU_CXPL_MACL_Symbol_Number_Register"},
344 {0x6e2078, 1, 1662, "PIU_PEU_CXPL_MACL_Symbol_Timer_Register"},
345 {0x6e2100, 1, 1663, "PIU_PEU_CXPL_Core_Status_Register"},
346 {0x6e2108, 1, 1664, "PIU_PEU_CXPL_Event_Error_Log_Enable_Register"},
347 {0x6e2110, 1, 1665, "PIU_PEU_CXPL_Event_Error_Interrupt_Enable_Register"},
348 {0x6e2118, 1, 1666, "PIU_PEU_CXPL_Event_Error_Interrupt_Status_Register"},
349 {0x6e2120, 1, 1667, "PIU_PEU_CXPL_Event_Error_Status_Clear_Register"},
350 {0x6e2128, 1, 1668, "PIU_PEU_CXPL_Event_Error_Set_Register"},
351 {0x6e2130, 1, 1669, "PIU_PEU_Link_Bit_Error_Counter_I_Register"},
352 {0x6e2138, 1, 1670, "PIU_PEU_Link_Bit_Error_Counter_II_Register"},
353 {0x6e2200, 1, 1671, "PIU_PEU_SERDES_PLL_Control_Register"},
354 {0x6e2300, 8, 1672, "PIU_PEU_SERDES_Receiver_Lane_Control_Register"},
355 {0x6e2380, 8, 1680, "PIU_PEU_SERDES_Receiver_Lane_Status_Register"},
356 {0x6e2400, 8, 1688, "PIU_PEU_SERDES_Transmitter_Control_Register"},
357 {0x6e2480, 8, 1696, "PIU_PEU_SERDES_Transmitter_Status_Register"},
358 {0x6e2500, 2, 1704, "PIU_PEU_SERDES_Test_Configuration_Register"},
359};
360
361
362typedef struct {
363 uint64_t Interrupt_Mapping_Registers[44];
364 uint64_t Interrupt_Clear_Registers[44];
365 uint64_t Interrupt_Retry_Timer_Register;
366 uint64_t Interrupt_State_Status_Register_1;
367 uint64_t Interrupt_State_Status_Register_2;
368 uint64_t INTX_Status_Register;
369 uint64_t INT_A_Clear_Register;
370 uint64_t INT_B_Clear_Register;
371 uint64_t INT_C_Clear_Register;
372 uint64_t INT_D_Clear_Register;
373 uint64_t Event_Queue_Base_Address_Register;
374 uint64_t Event_Queue_Control_Set_Register[36];
375 uint64_t Event_Queue_Control_Clear_Register[36];
376 uint64_t Event_Queue_State_Register[36];
377 uint64_t Event_Queue_Tail_Register[36];
378 uint64_t Event_Queue_Head_Register[36];
379 uint64_t MSI_Mapping_Register[256];
380 uint64_t MSI_Clear_Registers[256];
381 uint64_t Interrupt_Mondo_Data_0_Register;
382 uint64_t Interrupt_Mondo_Data_1_Register;
383 uint64_t ERR_COR_Mapping_Register;
384 uint64_t ERR_NONFATAL_Mapping_Register;
385 uint64_t ERR_FATAL_Mapping_Register;
386 uint64_t PM_PME_Mapping_Register;
387 uint64_t PME_To_ACK_Mapping_Register;
388 uint64_t IMU_Error_Log_Enable_Register;
389 uint64_t IMU_Interrupt_Enable_Register;
390 uint64_t IMU_Interrupt_Status_Register;
391 uint64_t IMU_Error_Status_Clear_Register;
392 uint64_t IMU_Error_Status_Set_Register;
393 uint64_t IMU_RDS_Error_Log_Register;
394 uint64_t IMU_SCS_Error_Log_Register;
395 uint64_t IMU_EQS_Error_Log_Register;
396 uint64_t DMC_Core_and_Block_Interrupt_Enable_Register;
397 uint64_t DMC_Core_and_Block_Error_Status_Register;
398 uint64_t IMU_Performance_Counter_Select_Register;
399 uint64_t IMU_Performance_Counter_Zero_Register;
400 uint64_t IMU_Performance_Counter_One_Register;
401 uint64_t MSI_32_bit_Address_Register;
402 uint64_t MSI_64_bit_Address_Register;
403 uint64_t Mem_64_PCIE_Offset_Register;
404 uint64_t MMU_Control_and_Status_Register;
405 uint64_t MMU_TSB_Control_Register;
406 uint64_t MMU_TTE_Cache_Invalidate_Register;
407 uint64_t MMU_Error_Log_Enable_Register;
408 uint64_t MMU_Interrupt_Enable_Register;
409 uint64_t MMU_Interrupt_Status_Register;
410 uint64_t MMU_Error_Status_Clear_Register;
411 uint64_t MMU_Error_Status_Set_Register;
412 uint64_t MMU_Translation_Fault_Address_Register;
413 uint64_t MMU_Translation_Fault_Status_Register;
414 uint64_t MMU_Performance_Counter_Select_Register;
415 uint64_t MMU_Performance_Counter_Zero_Register;
416 uint64_t MMU_Performance_Counter_One_Register;
417 uint64_t MMU_TTE_Cache_Virtual_Tag_Registers[64];
418 uint64_t MMU_TTE_Cache_Physical_Tag_Registers[64];
419 uint64_t MMU_TTE_Cache_Data_Registers[512];
420 uint64_t MMU_DEV2IOTSB_Registers[16];
421 uint64_t MMU_IOTSBDESC_Registers[32];
422 uint64_t ILU_Error_Log_Enable_Register;
423 uint64_t ILU_Interrupt_Enable_Register;
424 uint64_t ILU_Interrupt_Status_Register;
425 uint64_t ILU_Error_Status_Clear_Register;
426 uint64_t ILU_Error_Status_Set_Register;
427 uint64_t PEU_Core_and_Block_Interrupt_Enable_Register;
428 uint64_t PEU_Core_and_Block_Interrupt_Status_Register;
429 uint64_t ILU_Diagnostic_Register;
430 uint64_t DMU_Debug_Select_Register_for_DMU_Debug_Bus_A;
431 uint64_t DMU_Debug_Select_Register_for_DMU_Debug_Bus_B;
432 uint64_t DMU_PCI_Express_Configuration_Register;
433 uint64_t Packet_Scoreboard_DMA_Register_Set[32];
434 uint64_t Packet_Scoreboard_PIO_Register_Set[16];
435 uint64_t Transaction_Scoreboard_Register_Set[32];
436 uint64_t Transaction_Scoreboard_Status_Register;
437 uint64_t PEU_Control_Register;
438 uint64_t PEU_Status_Register;
439 uint64_t PEU_PME_Turn_Off_Generate_Register;
440 uint64_t PEU_Ingress_Credits_Initial_Register;
441 uint64_t PEU_Diagnostic_Register;
442 uint64_t PEU_Egress_Credits_Consumed_Register;
443 uint64_t PEU_Egress_Credit_Limit_Register;
444 uint64_t PEU_Egress_Retry_Buffer_Register;
445 uint64_t PEU_Ingress_Credits_Allocated_Register;
446 uint64_t PEU_Ingress_Credits_Received_Register;
447 uint64_t PEU_Other_Event_Log_Enable_Register;
448 uint64_t PEU_Other_Event_Interrupt_Enable_Register;
449 uint64_t PEU_Other_Event_Interrupt_Status_Register;
450 uint64_t PEU_Other_Event_Status_Clear_Register;
451 uint64_t PEU_Other_Event_Status_Set_Register;
452 uint64_t PEU_Receive_Other_Event_Header1_Log_Register;
453 uint64_t PEU_Receive_Other_Event_Header2_Log_Register;
454 uint64_t PEU_Transmit_Other_Event_Header1_Log_Register;
455 uint64_t PEU_Transmit_Other_Event_Header2_Log_Register;
456 uint64_t PEU_Performance_Counter_Select_Register;
457 uint64_t PEU_Performance_Counter_Zero_Register;
458 uint64_t PEU_Performance_Counter_One_Register;
459 uint64_t PEU_Performance_Counter_Two_Register;
460 uint64_t PEU_Debug_Select_A_Register;
461 uint64_t PEU_Debug_Select_B_Register;
462 uint64_t PEU_Device_Capabilities_Register;
463 uint64_t PEU_Device_Control_Register;
464 uint64_t PEU_Device_Status_Register;
465 uint64_t PEU_Link_Capabilities_Register;
466 uint64_t PEU_Link_Control_Register;
467 uint64_t PEU_Link_Status_Register;
468 uint64_t PEU_Slot_Capabilities_Register;
469 uint64_t PEU_Uncorrectable_Error_Log_Enable_Register;
470 uint64_t PEU_Uncorrectable_Error_Interrupt_Enable_Register;
471 uint64_t PEU_Uncorrectable_Error_Interrupt_Status_Register;
472 uint64_t PEU_Uncorrectable_Error_Status_Clear_Register;
473 uint64_t PEU_Uncorrectable_Error_Status_Set_Register;
474 uint64_t PEU_Receive_Uncorrectable_Error_Header1_Log_Register;
475 uint64_t PEU_Receive_Uncorrectable_Error_Header2_Log_Register;
476 uint64_t PEU_Transmit_Uncorrectable_Error_Header1_Log_Register;
477 uint64_t PEU_Transmit_Uncorrectable_Error_Header2_Log_Register;
478 uint64_t PEU_Correctable_Error_Log_Enable_Register;
479 uint64_t PEU_Correctable_Error_Interrupt_Enable_Register;
480 uint64_t PEU_Correctable_Error_Interrupt_Status_Register;
481 uint64_t PEU_Correctable_Error_Status_Clear_Register;
482 uint64_t PEU_Correctable_Error_Status_Set_Register;
483 uint64_t PEU_CXPL_SERDES_Revision_Register;
484 uint64_t PEU_CXPL_AckNak_Latency_Threshold_Register;
485 uint64_t PEU_CXPL_AckNak_Latency_Timer_Register;
486 uint64_t PEU_CXPL_Replay_Timer_Threshold_Register;
487 uint64_t PEU_CXPL_Replay_Timer_Register;
488 uint64_t PEU_CXPL_Vendor_DLLP_Message_Register;
489 uint64_t PEU_CXPL_LTSSM_Control_Register;
490 uint64_t PEU_CXPL_DLL_Control_Register;
491 uint64_t PEU_CXPL_MACL_PCS_Control_Register;
492 uint64_t PEU_CXPL_MACL_Lane_Skew_Control_Register;
493 uint64_t PEU_CXPL_MACL_Symbol_Number_Register;
494 uint64_t PEU_CXPL_MACL_Symbol_Timer_Register;
495 uint64_t PEU_CXPL_Core_Status_Register;
496 uint64_t PEU_CXPL_Event_Error_Log_Enable_Register;
497 uint64_t PEU_CXPL_Event_Error_Interrupt_Enable_Register;
498 uint64_t PEU_CXPL_Event_Error_Interrupt_Status_Register;
499 uint64_t PEU_CXPL_Event_Error_Status_Clear_Register;
500 uint64_t PEU_CXPL_Event_Error_Set_Register;
501 uint64_t PEU_Link_Bit_Error_Counter_I_Register;
502 uint64_t PEU_Link_Bit_Error_Counter_II_Register;
503 uint64_t PEU_SERDES_PLL_Control_Register;
504 uint64_t PEU_SERDES_Receiver_Lane_Control_Register[8];
505 uint64_t PEU_SERDES_Receiver_Lane_Status_Register[8];
506 uint64_t PEU_SERDES_Transmitter_Control_Register[8];
507 uint64_t PEU_SERDES_Transmitter_Status_Register[8];
508 uint64_t PEU_SERDES_Test_Configuration_Register[2];
509} piu_csr_t;
510
511#define WRITE_PIU_CSR(_r, _v, _m) ((_r) = ((_v) & (_m)) | ((_r) & ~(_m)))
512
513/*
514 * Error macro to build lookup table for simulating PIU errors:
515 *
516 * <type, name, error bit, interrupt enable bit>
517 */
518#define PIU_ERR( _name, _i) _name, #_name, ((uint64_t)1<<_i), ((uint64_t)1<<_i)
519
520/*
521 * IMMU error
522 */
523#define IMU_ERROR_MAXNUM 64
524
525typedef enum {
526 RDS,
527 SCS,
528 EQS
529} imu_group_t;
530
531typedef enum imu_error_type {
532 IMU_NONE = -1,
533 MSI_NOT_EN_P = 0,
534 COR_MES_NOT_EN_P = 1,
535 NONFATAL_MES_NOT_EN_P = 2,
536 FATAL_MES_NOT_EN_P = 3,
537 PMPME_MES_NOT_EN_P = 4,
538 PMEACK_MES_NOT_EN_P = 5,
539 MSI_PAR_ERR_P = 6,
540 MSI_MAL_ERR_P = 7,
541 EQ_NOT_EN_P = 8,
542 EQ_OVER_P = 9,
543 MSI_NOT_EN_S = 32,
544 COR_MES_NOT_EN_S = 33,
545 NONFATAL_MES_NOT_EN_S = 34,
546 FATAL_MES_NOT_EN_S = 35,
547 PMPME_MES_NOT_EN_SEQ_OVER_S = 36,
548 PMEACK_MES_NOT_EN_S = 37,
549 MSI_PAR_ERR_S = 38,
550 MSI_MAL_ERR_S = 39,
551 EQ_NOT_EN_S = 40,
552 EQ_OVER_S = 41
553} imu_error_type_t;
554
555typedef struct imu_error_entry {
556 imu_error_type_t error_type;
557 char *error_name;
558 uint64_t error_code;
559 uint64_t intr_enable;
560} imu_error_entry_t;
561
562imu_error_entry_t imu_error_list[IMU_ERROR_MAXNUM];
563
564/*
565 * MMU error
566 */
567#define MMU_ERROR_MAXNUM 64
568
569typedef enum mmu_error_type {
570 MMU_NONE = -1,
571 BYP_ERR_P = 0,
572 BYP_OOR_P = 1,
573 SUN4V_INV_PG_SZ_P = 2,
574 SPARE1_P = 3,
575 TRN_ERR_P = 4,
576 TRN_OOR_P = 5,
577 TTE_INV_P = 6,
578 TTE_PRT_P = 7,
579 TTC_DPE_P = 8,
580 TTC_CAE_P = 9,
581 SPARE2_P = 10,
582 SPARE3_P = 11,
583 TBW_DME_P = 12,
584 TBW_UDE_P = 13,
585 TBW_ERR_P = 14,
586 TBW_DPE_P = 15,
587 IOTSBDESC_INV_P = 16,
588 IOTSBDESC_DPE_P = 17,
589 SUN4V_VA_OOR_P = 18,
590 SUN4V_VA_ADJ_UF_P = 19,
591 SUN4V_KEY_ERR_P = 20,
592 BYP_ERR_S = 32,
593 BYP_OOR_S = 33,
594 SUN4V_INV_PG_SZ_S = 34,
595 SPARE1_S = 35,
596 TRN_ERR_S = 36,
597 TRN_OOR_S = 37,
598 TTE_INV_S = 38,
599 TTE_PRT_S = 39,
600 TTC_DPE_S = 40,
601 TTC_CAE_S = 41,
602 SPARE2_S = 42,
603 SPARE3_S = 43,
604 TBW_DME_S = 44,
605 TBW_UDE_S = 45,
606 TBW_ERR_S = 46,
607 TBW_DPE_S = 47,
608 IOTSBDESC_INV_S = 48,
609 IOTSBDESC_DPE_S = 49,
610 SUN4V_VA_OOR_S = 50,
611 SUN4V_VA_ADJ_UF_S = 51,
612 SUN4V_KEY_ERR_S = 52
613} mmu_error_type_t;
614
615typedef struct mmu_error_entry {
616 mmu_error_type_t error_type;
617 char *error_name;
618 uint64_t error_code;
619 uint64_t intr_enable;
620} mmu_error_entry_t;
621
622mmu_error_entry_t mmu_error_list[MMU_ERROR_MAXNUM];
623
624/*
625 * PCIE interface unit (PIU) for Niagara 2
626 */
627#define MAX_PCIE_INO_NUM 64 /* max interrupt number */
628#define PCIE_IO_ADDR_MASK MASK64(27,0)
629#define PCIE_IOCON_ADDR_MASK MASK64(28,0)
630#define PCIE_MEM64_ADDR_MASK MASK64(35,0)
631
632struct PCIE_MODEL {
633 char *proc_type_namep; /* processor type name */
634 piu_csr_t csrs; /* PCIE CSRs */
635 uint8_t interrupt[MAX_PCIE_INO_NUM];
636 config_dev_t *config_devp; /* back pointer to device tree */
637 config_proc_t *config_procp; /* back pointer to processor */
638 pcie_dev_inst_t *pcie_devices_list_head; /* end device linked list */
639};
640
641
642/*
643 * Interrupt Mondo INO mapping info
644 */
645typedef enum {
646 INO_INTA = 20,
647 INO_INTB = 21,
648 INO_INTC = 22,
649 INO_INTD = 23,
650 INO_EQLO = 24,
651 INO_EQHI = 59,
652 INO_DMU = 62,
653 INO_PEU = 63
654} irq_ino_t;
655
656/*
657 * Interrupt Mondo State (see N2 PRM section 16.4.3.2 for Interrupt Clear Register)
658 */
659typedef enum {
660 IRQ_IDLE = 0,
661 IRQ_RECEIVED = 1,
662 IRQ_RESERVED = 2, /* not used */
663 IRQ_PENDING = 3
664} irq_state_t;
665
666#define IRQ_STATE_MASK 0x3LL
667
668/*
669 * Event Queue Interrupt State (INO 24 - 59)
670 */
671typedef enum {
672 EQ_IDLE = 1,
673 EQ_ACTIVE = 2,
674 EQ_ERROR = 4
675} eq_state_t;
676
677#define EQ_NUM_ENTRIES 128
678#define EQ_RECORD_SIZE 64
679
680/*
681 * Event Queue Record
682 */
683typedef struct eq_record {
684 /*
685 * bit fields for record[0]
686 */
687 uint32_t :1; /* reserved, bit 63 */
688 uint32_t fmt_type :7; /* bit 62:56 */
689 uint32_t length :10; /* bit 55:46 */
690 uint32_t addr_15_2 :14; /* bit 45:32, copy of msi/msi-x addr[15:2] */
691 uint32_t rid :16; /* bit 31:16, requester Id */
692 uint32_t data0 :16; /* bit 15:0, msi/msi-x data[15,0] */
693 /*
694 * bit fields for record[1]
695 */
696 uint32_t addr_hi :32; /* bit 63:32, copy of msi/msi-x addr[63:32] */
697 uint32_t addr_31_16 :16; /* bit 31:16, copy of msi/msi-x addr[31:16] */
698 uint32_t data1 :16; /* bit 15:0, msi-x data[31:16], not valid for msi */
699 /*
700 * the rest of the records
701 */
702 uint64_t record[6]; /* reserved */
703} eq_record_t;
704
705/*
706 * PCIE TLP Fmt[1:0] and Type[4:0] Field Encodings
707 */
708#define TLP_MRd_FMT_TYPE_IS32 0 /* 32-bit addressed memory read */
709#define TLP_MRd_FMT_TYPE_IS64 (0x1<<5) /* 64-bit addressed memory read */
710#define TLP_MWr_FMT_TYPE_IS32 (0x2<<5) /* 32-bit addressed memory write */
711#define TLP_MWr_FMT_TYPE_IS64 (0x3<<5) /* 64-bit addressed memory write */
712#define TLP_MSI_FMT_TYPE_IS32 ((0x2<<5) | (0x18)) /* 32-bit addressed MSI */
713#define TLP_MSI_FMT_TYPE_IS64 ((0x3<<5) | (0x18)) /* 64-bit addressed MSI */
714
715/*
716 * Macros, functions used for handling PCIE downbound transactions
717 */
718#define PCIE_BUS_NO_MASK MASK64(27,20)
719#define PCIE_DEV_NO_MASK MASK64(19,15)
720#define PCIE_FUN_NO_MASK MASK64(14,12)
721#define PCIE_REG_NO_MASK MASK64(11, 0)
722
723#define PCIE_BUS_NO_SHIFT 20
724#define PCIE_DEV_NO_SHIFT 15
725#define PCIE_FUN_NO_SHIFT 12
726
727
728piu_region_t piu_decode_region(simcpu_t *sp, pcie_model_t *piup, uint64_t pa, uint64_t *offset);
729bool_t piu_decode_cfgio(pcie_model_t *piup, uint64_t pa, uint64_t *offset);
730bool_t piu_decode_mem32(pcie_model_t *piup, uint64_t pa, uint64_t *offset);
731bool_t piu_decode_mem64(pcie_model_t *piup, uint64_t pa, uint64_t *offset);
732
733bool_t piu_csr_access(simcpu_t *sp, pcie_model_t *piup, maccess_t op, uint64_t offset, uint64_t *regp);
734bool_t piu_cfg_access(pcie_model_t *piup, maccess_t op, uint64_t ioaddr, uint32_t count, uint64_t *regp);
735bool_t piu_io_access(pcie_model_t *piup, maccess_t op, uint64_t ioaddr, uint32_t count, uint64_t *regp);
736bool_t piu_mem_access(pcie_model_t *piup, maccess_t op, uint64_t ioaddr, uint32_t count, uint64_t *regp,
737 pcie_space_t space_id);
738
739/*
740 * Macros, functions used for handling PCIE upbound transactions
741 */
742bool_t piu_dma_access(pcie_model_t *piup, tvaddr_t va, uint8_t *datap, int count, uint16_t req_id,
743 dev_access_t type, dev_mode_t mode);
744bool_t piu_assert_intx(pcie_model_t *piup, uint8_t pin, uint8_t dev_no);
745bool_t piu_deassert_intx(pcie_model_t *piup, uint8_t pin, uint8_t dev_no);
746
747bool_t piu_iommu(pcie_model_t *piup, tvaddr_t va, uint16_t req_id, dev_access_t type,
748 dev_mode_t mode, tpaddr_t *pa);
749bool_t piu_iommu_sun4u(pcie_model_t *piup, tvaddr_t va, uint16_t req_id, dev_access_t type,
750 dev_mode_t mode, tpaddr_t *pa);
751bool_t piu_iommu_sun4v(pcie_model_t *piup, tvaddr_t va, uint16_t req_id, dev_access_t type,
752 dev_mode_t mode, tpaddr_t *pa);
753bool_t piu_iommu_va2pa(uint64_t tte, int ps, tvaddr_t va, uint16_t req_id, dev_access_t type,
754 dev_mode_t mode, tpaddr_t *pa);
755
756void piu_set_irq_state(pcie_model_t *piup, uint8_t ino, irq_state_t new);
757int piu_get_irq_state(pcie_model_t *piup, uint8_t ino);
758void piu_set_intx_state(pcie_model_t *piup, uint8_t ino, irq_state_t new);
759int piu_get_intx_state(pcie_model_t *piup, uint8_t ino);
760void piu_mondo_interrupt(pcie_model_t *piup, uint8_t ino, irq_state_t new);
761bool_t piu_eq_write(pcie_model_t *piup, int eqnum, eq_record_t *record, uint16_t req_id);
762bool_t piu_msi_write(pcie_model_t *piup, uint64_t msi_addr, uint8_t *msi_datap, int count,
763 uint16_t req_id, dev_mode_t mode);
764
765/*
766 * piu error handling routines
767 */
768void piu_init_error_list();
769void piu_simulate_imu_error(pcie_model_t *piup, uint64_t error);
770void piu_simulate_mmu_error(pcie_model_t *piup, uint64_t error);
771void piu_raise_imu_error(pcie_model_t *piup, uint64_t error_code);
772void piu_raise_mmu_error(pcie_model_t *piup, uint64_t error_code);
773
774/*
775 * internal function prototypes
776 */
777void piu_register_pcie_device(pcie_model_t *piup, pcie_dev_inst_t *new);
778pcie_csr_t piu_offset2reg(uint64_t offset, int *regx);
779pcie_dev_inst_t *piu_find_pcie_dev(pcie_model_t *piup, void *dptr, pcie_space_t space);
780
781#ifdef __cplusplus
782}
783#endif
784
785#endif /* _PIU_H */
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.