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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / legion / src / devices / mem_bus / libpiu / piu.h
/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: piu.h
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _PIU_H
#define _PIU_H
#pragma ident "@(#)piu.h 1.8 06/10/05 SMI"
#ifdef __cplusplus
extern "C" {
#endif
#include "niagara2_device.h"
/*
* PCIE CSRs implemented by Niagara 2
*/
#define MAX_PCIE_REGX 1706
#define NUM_PCIE_CSRS 146
#define UND_PCIE_CSRS -1
typedef enum PCIE_CSR pcie_csr_t;
typedef struct PCIE_CSR_DESC pcie_csr_desc_t;
enum PCIE_CSR {
PIU_Interrupt_Mapping_Registers,
PIU_Interrupt_Clear_Registers,
PIU_Interrupt_Retry_Timer_Register,
PIU_Interrupt_State_Status_Register_1,
PIU_Interrupt_State_Status_Register_2,
PIU_INTX_Status_Register,
PIU_INT_A_Clear_Register,
PIU_INT_B_Clear_Register,
PIU_INT_C_Clear_Register,
PIU_INT_D_Clear_Register,
PIU_Event_Queue_Base_Address_Register,
PIU_Event_Queue_Control_Set_Register,
PIU_Event_Queue_Control_Clear_Register,
PIU_Event_Queue_State_Register,
PIU_Event_Queue_Tail_Register,
PIU_Event_Queue_Head_Register,
PIU_MSI_Mapping_Register,
PIU_MSI_Clear_Registers,
PIU_Interrupt_Mondo_Data_0_Register,
PIU_Interrupt_Mondo_Data_1_Register,
PIU_ERR_COR_Mapping_Register,
PIU_ERR_NONFATAL_Mapping_Register,
PIU_ERR_FATAL_Mapping_Register,
PIU_PM_PME_Mapping_Register,
PIU_PME_To_ACK_Mapping_Register,
PIU_IMU_Error_Log_Enable_Register,
PIU_IMU_Interrupt_Enable_Register,
PIU_IMU_Interrupt_Status_Register,
PIU_IMU_Error_Status_Clear_Register,
PIU_IMU_Error_Status_Set_Register,
PIU_IMU_RDS_Error_Log_Register,
PIU_IMU_SCS_Error_Log_Register,
PIU_IMU_EQS_Error_Log_Register,
PIU_DMC_Core_and_Block_Interrupt_Enable_Register,
PIU_DMC_Core_and_Block_Error_Status_Register,
PIU_IMU_Performance_Counter_Select_Register,
PIU_IMU_Performance_Counter_Zero_Register,
PIU_IMU_Performance_Counter_One_Register,
PIU_MSI_32_bit_Address_Register,
PIU_MSI_64_bit_Address_Register,
PIU_Mem_64_PCIE_Offset_Register,
PIU_MMU_Control_and_Status_Register,
PIU_MMU_TSB_Control_Register,
PIU_MMU_TTE_Cache_Invalidate_Register,
PIU_MMU_Error_Log_Enable_Register,
PIU_MMU_Interrupt_Enable_Register,
PIU_MMU_Interrupt_Status_Register,
PIU_MMU_Error_Status_Clear_Register,
PIU_MMU_Error_Status_Set_Register,
PIU_MMU_Translation_Fault_Address_Register,
PIU_MMU_Translation_Fault_Status_Register,
PIU_MMU_Performance_Counter_Select_Register,
PIU_MMU_Performance_Counter_Zero_Register,
PIU_MMU_Performance_Counter_One_Register,
PIU_MMU_TTE_Cache_Virtual_Tag_Registers,
PIU_MMU_TTE_Cache_Physical_Tag_Registers,
PIU_MMU_TTE_Cache_Data_Registers,
PIU_MMU_DEV2IOTSB_Registers,
PIU_MMU_IOTSBDESC_Registers,
PIU_ILU_Error_Log_Enable_Register,
PIU_ILU_Interrupt_Enable_Register,
PIU_ILU_Interrupt_Status_Register,
PIU_ILU_Error_Status_Clear_Register,
PIU_ILU_Error_Status_Set_Register,
PIU_PEU_Core_and_Block_Interrupt_Enable_Register,
PIU_PEU_Core_and_Block_Interrupt_Status_Register,
PIU_ILU_Diagnostic_Register,
PIU_DMU_Debug_Select_Register_for_DMU_Debug_Bus_A,
PIU_DMU_Debug_Select_Register_for_DMU_Debug_Bus_B,
PIU_DMU_PCI_Express_Configuration_Register,
PIU_Packet_Scoreboard_DMA_Register_Set,
PIU_Packet_Scoreboard_PIO_Register_Set,
PIU_Transaction_Scoreboard_Register_Set,
PIU_Transaction_Scoreboard_Status_Register,
PIU_PEU_Control_Register,
PIU_PEU_Status_Register,
PIU_PEU_PME_Turn_Off_Generate_Register,
PIU_PEU_Ingress_Credits_Initial_Register,
PIU_PEU_Diagnostic_Register,
PIU_PEU_Egress_Credits_Consumed_Register,
PIU_PEU_Egress_Credit_Limit_Register,
PIU_PEU_Egress_Retry_Buffer_Register,
PIU_PEU_Ingress_Credits_Allocated_Register,
PIU_PEU_Ingress_Credits_Received_Register,
PIU_PEU_Other_Event_Log_Enable_Register,
PIU_PEU_Other_Event_Interrupt_Enable_Register,
PIU_PEU_Other_Event_Interrupt_Status_Register,
PIU_PEU_Other_Event_Status_Clear_Register,
PIU_PEU_Other_Event_Status_Set_Register,
PIU_PEU_Receive_Other_Event_Header1_Log_Register,
PIU_PEU_Receive_Other_Event_Header2_Log_Register,
PIU_PEU_Transmit_Other_Event_Header1_Log_Register,
PIU_PEU_Transmit_Other_Event_Header2_Log_Register,
PIU_PEU_Performance_Counter_Select_Register,
PIU_PEU_Performance_Counter_Zero_Register,
PIU_PEU_Performance_Counter_One_Register,
PIU_PEU_Performance_Counter_Two_Register,
PIU_PEU_Debug_Select_A_Register,
PIU_PEU_Debug_Select_B_Register,
PIU_PEU_Device_Capabilities_Register,
PIU_PEU_Device_Control_Register,
PIU_PEU_Device_Status_Register,
PIU_PEU_Link_Capabilities_Register,
PIU_PEU_Link_Control_Register,
PIU_PEU_Link_Status_Register,
PIU_PEU_Slot_Capabilities_Register,
PIU_PEU_Uncorrectable_Error_Log_Enable_Register,
PIU_PEU_Uncorrectable_Error_Interrupt_Enable_Register,
PIU_PEU_Uncorrectable_Error_Interrupt_Status_Register,
PIU_PEU_Uncorrectable_Error_Status_Clear_Register,
PIU_PEU_Uncorrectable_Error_Status_Set_Register,
PIU_PEU_Receive_Uncorrectable_Error_Header1_Log_Register,
PIU_PEU_Receive_Uncorrectable_Error_Header2_Log_Register,
PIU_PEU_Transmit_Uncorrectable_Error_Header1_Log_Register,
PIU_PEU_Transmit_Uncorrectable_Error_Header2_Log_Register,
PIU_PEU_Correctable_Error_Log_Enable_Register,
PIU_PEU_Correctable_Error_Interrupt_Enable_Register,
PIU_PEU_Correctable_Error_Interrupt_Status_Register,
PIU_PEU_Correctable_Error_Status_Clear_Register,
PIU_PEU_Correctable_Error_Status_Set_Register,
PIU_PEU_CXPL_SERDES_Revision_Register,
PIU_PEU_CXPL_AckNak_Latency_Threshold_Register,
PIU_PEU_CXPL_AckNak_Latency_Timer_Register,
PIU_PEU_CXPL_Replay_Timer_Threshold_Register,
PIU_PEU_CXPL_Replay_Timer_Register,
PIU_PEU_CXPL_Vendor_DLLP_Message_Register,
PIU_PEU_CXPL_LTSSM_Control_Register,
PIU_PEU_CXPL_DLL_Control_Register,
PIU_PEU_CXPL_MACL_PCS_Control_Register,
PIU_PEU_CXPL_MACL_Lane_Skew_Control_Register,
PIU_PEU_CXPL_MACL_Symbol_Number_Register,
PIU_PEU_CXPL_MACL_Symbol_Timer_Register,
PIU_PEU_CXPL_Core_Status_Register,
PIU_PEU_CXPL_Event_Error_Log_Enable_Register,
PIU_PEU_CXPL_Event_Error_Interrupt_Enable_Register,
PIU_PEU_CXPL_Event_Error_Interrupt_Status_Register,
PIU_PEU_CXPL_Event_Error_Status_Clear_Register,
PIU_PEU_CXPL_Event_Error_Set_Register,
PIU_PEU_Link_Bit_Error_Counter_I_Register,
PIU_PEU_Link_Bit_Error_Counter_II_Register,
PIU_PEU_SERDES_PLL_Control_Register,
PIU_PEU_SERDES_Receiver_Lane_Control_Register,
PIU_PEU_SERDES_Receiver_Lane_Status_Register,
PIU_PEU_SERDES_Transmitter_Control_Register,
PIU_PEU_SERDES_Transmitter_Status_Register,
PIU_PEU_SERDES_Test_Configuration_Register
};
/*
* CSR descrptor, used to specify each of the PCIE CSRs implemented
* by Niagara 2 PIU
*/
struct PCIE_CSR_DESC {
int offset;
int nwords;
int regx;
const char *name;
};
pcie_csr_desc_t pcie_csrs[NUM_PCIE_CSRS] = {
{0x6010a0, 44, 0, "PIU_Interrupt_Mapping_Registers"},
{0x6014a0, 44, 44, "PIU_Interrupt_Clear_Registers"},
{0x601a00, 1, 88, "PIU_Interrupt_Retry_Timer_Register"},
{0x601a10, 1, 89, "PIU_Interrupt_State_Status_Register_1"},
{0x601a18, 1, 90, "PIU_Interrupt_State_Status_Register_2"},
{0x60b000, 1, 91, "PIU_INTX_Status_Register"},
{0x60b008, 1, 92, "PIU_INT_A_Clear_Register"},
{0x60b010, 1, 93, "PIU_INT_B_Clear_Register"},
{0x60b018, 1, 94, "PIU_INT_C_Clear_Register"},
{0x60b020, 1, 95, "PIU_INT_D_Clear_Register"},
{0x610000, 1, 96, "PIU_Event_Queue_Base_Address_Register"},
{0x611000, 36, 97, "PIU_Event_Queue_Control_Set_Register"},
{0x611200, 36, 133, "PIU_Event_Queue_Control_Clear_Register"},
{0x611400, 36, 169, "PIU_Event_Queue_State_Register"},
{0x611600, 36, 205, "PIU_Event_Queue_Tail_Register"},
{0x611800, 36, 241, "PIU_Event_Queue_Head_Register"},
{0x620000, 256, 277, "PIU_MSI_Mapping_Register"},
{0x628000, 256, 533, "PIU_MSI_Clear_Registers"},
{0x62c000, 1, 789, "PIU_Interrupt_Mondo_Data_0_Register"},
{0x62c008, 1, 790, "PIU_Interrupt_Mondo_Data_1_Register"},
{0x630000, 1, 791, "PIU_ERR_COR_Mapping_Register"},
{0x630008, 1, 792, "PIU_ERR_NONFATAL_Mapping_Register"},
{0x630010, 1, 793, "PIU_ERR_FATAL_Mapping_Register"},
{0x630018, 1, 794, "PIU_PM_PME_Mapping_Register"},
{0x630020, 1, 795, "PIU_PME_To_ACK_Mapping_Register"},
{0x631000, 1, 796, "PIU_IMU_Error_Log_Enable_Register"},
{0x631008, 1, 797, "PIU_IMU_Interrupt_Enable_Register"},
{0x631010, 1, 798, "PIU_IMU_Interrupt_Status_Register"},
{0x631018, 1, 799, "PIU_IMU_Error_Status_Clear_Register"},
{0x631020, 1, 800, "PIU_IMU_Error_Status_Set_Register"},
{0x631028, 1, 801, "PIU_IMU_RDS_Error_Log_Register"},
{0x631030, 1, 802, "PIU_IMU_SCS_Error_Log_Register"},
{0x631038, 1, 803, "PIU_IMU_EQS_Error_Log_Register"},
{0x631800, 1, 804, "PIU_DMC_Core_and_Block_Interrupt_Enable_Register"},
{0x631808, 1, 805, "PIU_DMC_Core_and_Block_Error_Status_Register"},
{0x632000, 1, 806, "PIU_IMU_Performance_Counter_Select_Register"},
{0x632008, 1, 807, "PIU_IMU_Performance_Counter_Zero_Register"},
{0x632010, 1, 808, "PIU_IMU_Performance_Counter_One_Register"},
{0x634000, 1, 809, "PIU_MSI_32_bit_Address_Register"},
{0x634008, 1, 810, "PIU_MSI_64_bit_Address_Register"},
{0x634018, 1, 811, "PIU_Mem_64_PCIE_Offset_Register"},
{0x640000, 1, 812, "PIU_MMU_Control_and_Status_Register"},
{0x640008, 1, 813, "PIU_MMU_TSB_Control_Register"},
{0x640108, 1, 814, "PIU_MMU_TTE_Cache_Invalidate_Register"},
{0x641000, 1, 815, "PIU_MMU_Error_Log_Enable_Register"},
{0x641008, 1, 816, "PIU_MMU_Interrupt_Enable_Register"},
{0x641010, 1, 817, "PIU_MMU_Interrupt_Status_Register"},
{0x641018, 1, 818, "PIU_MMU_Error_Status_Clear_Register"},
{0x641020, 1, 819, "PIU_MMU_Error_Status_Set_Register"},
{0x641028, 1, 820, "PIU_MMU_Translation_Fault_Address_Register"},
{0x641030, 1, 821, "PIU_MMU_Translation_Fault_Status_Register"},
{0x642000, 1, 822, "PIU_MMU_Performance_Counter_Select_Register"},
{0x642008, 1, 823, "PIU_MMU_Performance_Counter_Zero_Register"},
{0x642010, 1, 824, "PIU_MMU_Performance_Counter_One_Register"},
{0x646000, 64, 825, "PIU_MMU_TTE_Cache_Virtual_Tag_Registers"},
{0x647000, 64, 889, "PIU_MMU_TTE_Cache_Physical_Tag_Registers"},
{0x648000, 512, 953, "PIU_MMU_TTE_Cache_Data_Registers"},
{0x649000, 16, 1465, "PIU_MMU_DEV2IOTSB_Registers"},
{0x649100, 32, 1481, "PIU_MMU_IOTSBDESC_Registers"},
{0x651000, 1, 1513, "PIU_ILU_Error_Log_Enable_Register"},
{0x651008, 1, 1514, "PIU_ILU_Interrupt_Enable_Register"},
{0x651010, 1, 1515, "PIU_ILU_Interrupt_Status_Register"},
{0x651018, 1, 1516, "PIU_ILU_Error_Status_Clear_Register"},
{0x651020, 1, 1517, "PIU_ILU_Error_Status_Set_Register"},
{0x651800, 1, 1518, "PIU_PEU_Core_and_Block_Interrupt_Enable_Register"},
{0x651808, 1, 1519, "PIU_PEU_Core_and_Block_Interrupt_Status_Register"},
{0x652000, 1, 1520, "PIU_ILU_Diagnostic_Register"},
{0x653000, 1, 1521, "PIU_DMU_Debug_Select_Register_for_DMU_Debug_Bus_A"},
{0x653008, 1, 1522, "PIU_DMU_Debug_Select_Register_for_DMU_Debug_Bus_B"},
{0x653100, 1, 1523, "PIU_DMU_PCI_Express_Configuration_Register"},
{0x660000, 32, 1524, "PIU_Packet_Scoreboard_DMA_Register_Set"},
{0x664000, 16, 1556, "PIU_Packet_Scoreboard_PIO_Register_Set"},
{0x670000, 32, 1572, "PIU_Transaction_Scoreboard_Register_Set"},
{0x670100, 1, 1604, "PIU_Transaction_Scoreboard_Status_Register"},
{0x680000, 1, 1605, "PIU_PEU_Control_Register"},
{0x680008, 1, 1606, "PIU_PEU_Status_Register"},
{0x680010, 1, 1607, "PIU_PEU_PME_Turn_Off_Generate_Register"},
{0x680018, 1, 1608, "PIU_PEU_Ingress_Credits_Initial_Register"},
{0x680100, 1, 1609, "PIU_PEU_Diagnostic_Register"},
{0x680200, 1, 1610, "PIU_PEU_Egress_Credits_Consumed_Register"},
{0x680208, 1, 1611, "PIU_PEU_Egress_Credit_Limit_Register"},
{0x680210, 1, 1612, "PIU_PEU_Egress_Retry_Buffer_Register"},
{0x680218, 1, 1613, "PIU_PEU_Ingress_Credits_Allocated_Register"},
{0x680220, 1, 1614, "PIU_PEU_Ingress_Credits_Received_Register"},
{0x681000, 1, 1615, "PIU_PEU_Other_Event_Log_Enable_Register"},
{0x681008, 1, 1616, "PIU_PEU_Other_Event_Interrupt_Enable_Register"},
{0x681010, 1, 1617, "PIU_PEU_Other_Event_Interrupt_Status_Register"},
{0x681018, 1, 1618, "PIU_PEU_Other_Event_Status_Clear_Register"},
{0x681020, 1, 1619, "PIU_PEU_Other_Event_Status_Set_Register"},
{0x681028, 1, 1620, "PIU_PEU_Receive_Other_Event_Header1_Log_Register"},
{0x681030, 1, 1621, "PIU_PEU_Receive_Other_Event_Header2_Log_Register"},
{0x681038, 1, 1622, "PIU_PEU_Transmit_Other_Event_Header1_Log_Register"},
{0x681040, 1, 1623, "PIU_PEU_Transmit_Other_Event_Header2_Log_Register"},
{0x682000, 1, 1624, "PIU_PEU_Performance_Counter_Select_Register"},
{0x682008, 1, 1625, "PIU_PEU_Performance_Counter_Zero_Register"},
{0x682010, 1, 1626, "PIU_PEU_Performance_Counter_One_Register"},
{0x682018, 1, 1627, "PIU_PEU_Performance_Counter_Two_Register"},
{0x683000, 1, 1628, "PIU_PEU_Debug_Select_A_Register"},
{0x683008, 1, 1629, "PIU_PEU_Debug_Select_B_Register"},
{0x690000, 1, 1630, "PIU_PEU_Device_Capabilities_Register"},
{0x690008, 1, 1631, "PIU_PEU_Device_Control_Register"},
{0x690010, 1, 1632, "PIU_PEU_Device_Status_Register"},
{0x690018, 1, 1633, "PIU_PEU_Link_Capabilities_Register"},
{0x690020, 1, 1634, "PIU_PEU_Link_Control_Register"},
{0x690028, 1, 1635, "PIU_PEU_Link_Status_Register"},
{0x690030, 1, 1636, "PIU_PEU_Slot_Capabilities_Register"},
{0x691000, 1, 1637, "PIU_PEU_Uncorrectable_Error_Log_Enable_Register"},
{0x691008, 1, 1638, "PIU_PEU_Uncorrectable_Error_Interrupt_Enable_Register"},
{0x691010, 1, 1639, "PIU_PEU_Uncorrectable_Error_Interrupt_Status_Register"},
{0x691018, 1, 1640, "PIU_PEU_Uncorrectable_Error_Status_Clear_Register"},
{0x691020, 1, 1641, "PIU_PEU_Uncorrectable_Error_Status_Set_Register"},
{0x691028, 1, 1642, "PIU_PEU_Receive_Uncorrectable_Error_Header1_Log_Register"},
{0x691030, 1, 1643, "PIU_PEU_Receive_Uncorrectable_Error_Header2_Log_Register"},
{0x691038, 1, 1644, "PIU_PEU_Transmit_Uncorrectable_Error_Header1_Log_Register"},
{0x691040, 1, 1645, "PIU_PEU_Transmit_Uncorrectable_Error_Header2_Log_Register"},
{0x6a1000, 1, 1646, "PIU_PEU_Correctable_Error_Log_Enable_Register"},
{0x6a1008, 1, 1647, "PIU_PEU_Correctable_Error_Interrupt_Enable_Register"},
{0x6a1010, 1, 1648, "PIU_PEU_Correctable_Error_Interrupt_Status_Register"},
{0x6a1018, 1, 1649, "PIU_PEU_Correctable_Error_Status_Clear_Register"},
{0x6a1020, 1, 1650, "PIU_PEU_Correctable_Error_Status_Set_Register"},
{0x6e2000, 1, 1651, "PIU_PEU_CXPL_SERDES_Revision_Register"},
{0x6e2008, 1, 1652, "PIU_PEU_CXPL_AckNak_Latency_Threshold_Register"},
{0x6e2010, 1, 1653, "PIU_PEU_CXPL_AckNak_Latency_Timer_Register"},
{0x6e2018, 1, 1654, "PIU_PEU_CXPL_Replay_Timer_Threshold_Register"},
{0x6e2020, 1, 1655, "PIU_PEU_CXPL_Replay_Timer_Register"},
{0x6e2040, 1, 1656, "PIU_PEU_CXPL_Vendor_DLLP_Message_Register"},
{0x6e2050, 1, 1657, "PIU_PEU_CXPL_LTSSM_Control_Register"},
{0x6e2058, 1, 1658, "PIU_PEU_CXPL_DLL_Control_Register"},
{0x6e2060, 1, 1659, "PIU_PEU_CXPL_MACL_PCS_Control_Register"},
{0x6e2068, 1, 1660, "PIU_PEU_CXPL_MACL_Lane_Skew_Control_Register"},
{0x6e2070, 1, 1661, "PIU_PEU_CXPL_MACL_Symbol_Number_Register"},
{0x6e2078, 1, 1662, "PIU_PEU_CXPL_MACL_Symbol_Timer_Register"},
{0x6e2100, 1, 1663, "PIU_PEU_CXPL_Core_Status_Register"},
{0x6e2108, 1, 1664, "PIU_PEU_CXPL_Event_Error_Log_Enable_Register"},
{0x6e2110, 1, 1665, "PIU_PEU_CXPL_Event_Error_Interrupt_Enable_Register"},
{0x6e2118, 1, 1666, "PIU_PEU_CXPL_Event_Error_Interrupt_Status_Register"},
{0x6e2120, 1, 1667, "PIU_PEU_CXPL_Event_Error_Status_Clear_Register"},
{0x6e2128, 1, 1668, "PIU_PEU_CXPL_Event_Error_Set_Register"},
{0x6e2130, 1, 1669, "PIU_PEU_Link_Bit_Error_Counter_I_Register"},
{0x6e2138, 1, 1670, "PIU_PEU_Link_Bit_Error_Counter_II_Register"},
{0x6e2200, 1, 1671, "PIU_PEU_SERDES_PLL_Control_Register"},
{0x6e2300, 8, 1672, "PIU_PEU_SERDES_Receiver_Lane_Control_Register"},
{0x6e2380, 8, 1680, "PIU_PEU_SERDES_Receiver_Lane_Status_Register"},
{0x6e2400, 8, 1688, "PIU_PEU_SERDES_Transmitter_Control_Register"},
{0x6e2480, 8, 1696, "PIU_PEU_SERDES_Transmitter_Status_Register"},
{0x6e2500, 2, 1704, "PIU_PEU_SERDES_Test_Configuration_Register"},
};
typedef struct {
uint64_t Interrupt_Mapping_Registers[44];
uint64_t Interrupt_Clear_Registers[44];
uint64_t Interrupt_Retry_Timer_Register;
uint64_t Interrupt_State_Status_Register_1;
uint64_t Interrupt_State_Status_Register_2;
uint64_t INTX_Status_Register;
uint64_t INT_A_Clear_Register;
uint64_t INT_B_Clear_Register;
uint64_t INT_C_Clear_Register;
uint64_t INT_D_Clear_Register;
uint64_t Event_Queue_Base_Address_Register;
uint64_t Event_Queue_Control_Set_Register[36];
uint64_t Event_Queue_Control_Clear_Register[36];
uint64_t Event_Queue_State_Register[36];
uint64_t Event_Queue_Tail_Register[36];
uint64_t Event_Queue_Head_Register[36];
uint64_t MSI_Mapping_Register[256];
uint64_t MSI_Clear_Registers[256];
uint64_t Interrupt_Mondo_Data_0_Register;
uint64_t Interrupt_Mondo_Data_1_Register;
uint64_t ERR_COR_Mapping_Register;
uint64_t ERR_NONFATAL_Mapping_Register;
uint64_t ERR_FATAL_Mapping_Register;
uint64_t PM_PME_Mapping_Register;
uint64_t PME_To_ACK_Mapping_Register;
uint64_t IMU_Error_Log_Enable_Register;
uint64_t IMU_Interrupt_Enable_Register;
uint64_t IMU_Interrupt_Status_Register;
uint64_t IMU_Error_Status_Clear_Register;
uint64_t IMU_Error_Status_Set_Register;
uint64_t IMU_RDS_Error_Log_Register;
uint64_t IMU_SCS_Error_Log_Register;
uint64_t IMU_EQS_Error_Log_Register;
uint64_t DMC_Core_and_Block_Interrupt_Enable_Register;
uint64_t DMC_Core_and_Block_Error_Status_Register;
uint64_t IMU_Performance_Counter_Select_Register;
uint64_t IMU_Performance_Counter_Zero_Register;
uint64_t IMU_Performance_Counter_One_Register;
uint64_t MSI_32_bit_Address_Register;
uint64_t MSI_64_bit_Address_Register;
uint64_t Mem_64_PCIE_Offset_Register;
uint64_t MMU_Control_and_Status_Register;
uint64_t MMU_TSB_Control_Register;
uint64_t MMU_TTE_Cache_Invalidate_Register;
uint64_t MMU_Error_Log_Enable_Register;
uint64_t MMU_Interrupt_Enable_Register;
uint64_t MMU_Interrupt_Status_Register;
uint64_t MMU_Error_Status_Clear_Register;
uint64_t MMU_Error_Status_Set_Register;
uint64_t MMU_Translation_Fault_Address_Register;
uint64_t MMU_Translation_Fault_Status_Register;
uint64_t MMU_Performance_Counter_Select_Register;
uint64_t MMU_Performance_Counter_Zero_Register;
uint64_t MMU_Performance_Counter_One_Register;
uint64_t MMU_TTE_Cache_Virtual_Tag_Registers[64];
uint64_t MMU_TTE_Cache_Physical_Tag_Registers[64];
uint64_t MMU_TTE_Cache_Data_Registers[512];
uint64_t MMU_DEV2IOTSB_Registers[16];
uint64_t MMU_IOTSBDESC_Registers[32];
uint64_t ILU_Error_Log_Enable_Register;
uint64_t ILU_Interrupt_Enable_Register;
uint64_t ILU_Interrupt_Status_Register;
uint64_t ILU_Error_Status_Clear_Register;
uint64_t ILU_Error_Status_Set_Register;
uint64_t PEU_Core_and_Block_Interrupt_Enable_Register;
uint64_t PEU_Core_and_Block_Interrupt_Status_Register;
uint64_t ILU_Diagnostic_Register;
uint64_t DMU_Debug_Select_Register_for_DMU_Debug_Bus_A;
uint64_t DMU_Debug_Select_Register_for_DMU_Debug_Bus_B;
uint64_t DMU_PCI_Express_Configuration_Register;
uint64_t Packet_Scoreboard_DMA_Register_Set[32];
uint64_t Packet_Scoreboard_PIO_Register_Set[16];
uint64_t Transaction_Scoreboard_Register_Set[32];
uint64_t Transaction_Scoreboard_Status_Register;
uint64_t PEU_Control_Register;
uint64_t PEU_Status_Register;
uint64_t PEU_PME_Turn_Off_Generate_Register;
uint64_t PEU_Ingress_Credits_Initial_Register;
uint64_t PEU_Diagnostic_Register;
uint64_t PEU_Egress_Credits_Consumed_Register;
uint64_t PEU_Egress_Credit_Limit_Register;
uint64_t PEU_Egress_Retry_Buffer_Register;
uint64_t PEU_Ingress_Credits_Allocated_Register;
uint64_t PEU_Ingress_Credits_Received_Register;
uint64_t PEU_Other_Event_Log_Enable_Register;
uint64_t PEU_Other_Event_Interrupt_Enable_Register;
uint64_t PEU_Other_Event_Interrupt_Status_Register;
uint64_t PEU_Other_Event_Status_Clear_Register;
uint64_t PEU_Other_Event_Status_Set_Register;
uint64_t PEU_Receive_Other_Event_Header1_Log_Register;
uint64_t PEU_Receive_Other_Event_Header2_Log_Register;
uint64_t PEU_Transmit_Other_Event_Header1_Log_Register;
uint64_t PEU_Transmit_Other_Event_Header2_Log_Register;
uint64_t PEU_Performance_Counter_Select_Register;
uint64_t PEU_Performance_Counter_Zero_Register;
uint64_t PEU_Performance_Counter_One_Register;
uint64_t PEU_Performance_Counter_Two_Register;
uint64_t PEU_Debug_Select_A_Register;
uint64_t PEU_Debug_Select_B_Register;
uint64_t PEU_Device_Capabilities_Register;
uint64_t PEU_Device_Control_Register;
uint64_t PEU_Device_Status_Register;
uint64_t PEU_Link_Capabilities_Register;
uint64_t PEU_Link_Control_Register;
uint64_t PEU_Link_Status_Register;
uint64_t PEU_Slot_Capabilities_Register;
uint64_t PEU_Uncorrectable_Error_Log_Enable_Register;
uint64_t PEU_Uncorrectable_Error_Interrupt_Enable_Register;
uint64_t PEU_Uncorrectable_Error_Interrupt_Status_Register;
uint64_t PEU_Uncorrectable_Error_Status_Clear_Register;
uint64_t PEU_Uncorrectable_Error_Status_Set_Register;
uint64_t PEU_Receive_Uncorrectable_Error_Header1_Log_Register;
uint64_t PEU_Receive_Uncorrectable_Error_Header2_Log_Register;
uint64_t PEU_Transmit_Uncorrectable_Error_Header1_Log_Register;
uint64_t PEU_Transmit_Uncorrectable_Error_Header2_Log_Register;
uint64_t PEU_Correctable_Error_Log_Enable_Register;
uint64_t PEU_Correctable_Error_Interrupt_Enable_Register;
uint64_t PEU_Correctable_Error_Interrupt_Status_Register;
uint64_t PEU_Correctable_Error_Status_Clear_Register;
uint64_t PEU_Correctable_Error_Status_Set_Register;
uint64_t PEU_CXPL_SERDES_Revision_Register;
uint64_t PEU_CXPL_AckNak_Latency_Threshold_Register;
uint64_t PEU_CXPL_AckNak_Latency_Timer_Register;
uint64_t PEU_CXPL_Replay_Timer_Threshold_Register;
uint64_t PEU_CXPL_Replay_Timer_Register;
uint64_t PEU_CXPL_Vendor_DLLP_Message_Register;
uint64_t PEU_CXPL_LTSSM_Control_Register;
uint64_t PEU_CXPL_DLL_Control_Register;
uint64_t PEU_CXPL_MACL_PCS_Control_Register;
uint64_t PEU_CXPL_MACL_Lane_Skew_Control_Register;
uint64_t PEU_CXPL_MACL_Symbol_Number_Register;
uint64_t PEU_CXPL_MACL_Symbol_Timer_Register;
uint64_t PEU_CXPL_Core_Status_Register;
uint64_t PEU_CXPL_Event_Error_Log_Enable_Register;
uint64_t PEU_CXPL_Event_Error_Interrupt_Enable_Register;
uint64_t PEU_CXPL_Event_Error_Interrupt_Status_Register;
uint64_t PEU_CXPL_Event_Error_Status_Clear_Register;
uint64_t PEU_CXPL_Event_Error_Set_Register;
uint64_t PEU_Link_Bit_Error_Counter_I_Register;
uint64_t PEU_Link_Bit_Error_Counter_II_Register;
uint64_t PEU_SERDES_PLL_Control_Register;
uint64_t PEU_SERDES_Receiver_Lane_Control_Register[8];
uint64_t PEU_SERDES_Receiver_Lane_Status_Register[8];
uint64_t PEU_SERDES_Transmitter_Control_Register[8];
uint64_t PEU_SERDES_Transmitter_Status_Register[8];
uint64_t PEU_SERDES_Test_Configuration_Register[2];
} piu_csr_t;
#define WRITE_PIU_CSR(_r, _v, _m) ((_r) = ((_v) & (_m)) | ((_r) & ~(_m)))
/*
* Error macro to build lookup table for simulating PIU errors:
*
* <type, name, error bit, interrupt enable bit>
*/
#define PIU_ERR( _name, _i) _name, #_name, ((uint64_t)1<<_i), ((uint64_t)1<<_i)
/*
* IMMU error
*/
#define IMU_ERROR_MAXNUM 64
typedef enum {
RDS,
SCS,
EQS
} imu_group_t;
typedef enum imu_error_type {
IMU_NONE = -1,
MSI_NOT_EN_P = 0,
COR_MES_NOT_EN_P = 1,
NONFATAL_MES_NOT_EN_P = 2,
FATAL_MES_NOT_EN_P = 3,
PMPME_MES_NOT_EN_P = 4,
PMEACK_MES_NOT_EN_P = 5,
MSI_PAR_ERR_P = 6,
MSI_MAL_ERR_P = 7,
EQ_NOT_EN_P = 8,
EQ_OVER_P = 9,
MSI_NOT_EN_S = 32,
COR_MES_NOT_EN_S = 33,
NONFATAL_MES_NOT_EN_S = 34,
FATAL_MES_NOT_EN_S = 35,
PMPME_MES_NOT_EN_SEQ_OVER_S = 36,
PMEACK_MES_NOT_EN_S = 37,
MSI_PAR_ERR_S = 38,
MSI_MAL_ERR_S = 39,
EQ_NOT_EN_S = 40,
EQ_OVER_S = 41
} imu_error_type_t;
typedef struct imu_error_entry {
imu_error_type_t error_type;
char *error_name;
uint64_t error_code;
uint64_t intr_enable;
} imu_error_entry_t;
imu_error_entry_t imu_error_list[IMU_ERROR_MAXNUM];
/*
* MMU error
*/
#define MMU_ERROR_MAXNUM 64
typedef enum mmu_error_type {
MMU_NONE = -1,
BYP_ERR_P = 0,
BYP_OOR_P = 1,
SUN4V_INV_PG_SZ_P = 2,
SPARE1_P = 3,
TRN_ERR_P = 4,
TRN_OOR_P = 5,
TTE_INV_P = 6,
TTE_PRT_P = 7,
TTC_DPE_P = 8,
TTC_CAE_P = 9,
SPARE2_P = 10,
SPARE3_P = 11,
TBW_DME_P = 12,
TBW_UDE_P = 13,
TBW_ERR_P = 14,
TBW_DPE_P = 15,
IOTSBDESC_INV_P = 16,
IOTSBDESC_DPE_P = 17,
SUN4V_VA_OOR_P = 18,
SUN4V_VA_ADJ_UF_P = 19,
SUN4V_KEY_ERR_P = 20,
BYP_ERR_S = 32,
BYP_OOR_S = 33,
SUN4V_INV_PG_SZ_S = 34,
SPARE1_S = 35,
TRN_ERR_S = 36,
TRN_OOR_S = 37,
TTE_INV_S = 38,
TTE_PRT_S = 39,
TTC_DPE_S = 40,
TTC_CAE_S = 41,
SPARE2_S = 42,
SPARE3_S = 43,
TBW_DME_S = 44,
TBW_UDE_S = 45,
TBW_ERR_S = 46,
TBW_DPE_S = 47,
IOTSBDESC_INV_S = 48,
IOTSBDESC_DPE_S = 49,
SUN4V_VA_OOR_S = 50,
SUN4V_VA_ADJ_UF_S = 51,
SUN4V_KEY_ERR_S = 52
} mmu_error_type_t;
typedef struct mmu_error_entry {
mmu_error_type_t error_type;
char *error_name;
uint64_t error_code;
uint64_t intr_enable;
} mmu_error_entry_t;
mmu_error_entry_t mmu_error_list[MMU_ERROR_MAXNUM];
/*
* PCIE interface unit (PIU) for Niagara 2
*/
#define MAX_PCIE_INO_NUM 64 /* max interrupt number */
#define PCIE_IO_ADDR_MASK MASK64(27,0)
#define PCIE_IOCON_ADDR_MASK MASK64(28,0)
#define PCIE_MEM64_ADDR_MASK MASK64(35,0)
struct PCIE_MODEL {
char *proc_type_namep; /* processor type name */
piu_csr_t csrs; /* PCIE CSRs */
uint8_t interrupt[MAX_PCIE_INO_NUM];
config_dev_t *config_devp; /* back pointer to device tree */
config_proc_t *config_procp; /* back pointer to processor */
pcie_dev_inst_t *pcie_devices_list_head; /* end device linked list */
};
/*
* Interrupt Mondo INO mapping info
*/
typedef enum {
INO_INTA = 20,
INO_INTB = 21,
INO_INTC = 22,
INO_INTD = 23,
INO_EQLO = 24,
INO_EQHI = 59,
INO_DMU = 62,
INO_PEU = 63
} irq_ino_t;
/*
* Interrupt Mondo State (see N2 PRM section 16.4.3.2 for Interrupt Clear Register)
*/
typedef enum {
IRQ_IDLE = 0,
IRQ_RECEIVED = 1,
IRQ_RESERVED = 2, /* not used */
IRQ_PENDING = 3
} irq_state_t;
#define IRQ_STATE_MASK 0x3LL
/*
* Event Queue Interrupt State (INO 24 - 59)
*/
typedef enum {
EQ_IDLE = 1,
EQ_ACTIVE = 2,
EQ_ERROR = 4
} eq_state_t;
#define EQ_NUM_ENTRIES 128
#define EQ_RECORD_SIZE 64
/*
* Event Queue Record
*/
typedef struct eq_record {
/*
* bit fields for record[0]
*/
uint32_t :1; /* reserved, bit 63 */
uint32_t fmt_type :7; /* bit 62:56 */
uint32_t length :10; /* bit 55:46 */
uint32_t addr_15_2 :14; /* bit 45:32, copy of msi/msi-x addr[15:2] */
uint32_t rid :16; /* bit 31:16, requester Id */
uint32_t data0 :16; /* bit 15:0, msi/msi-x data[15,0] */
/*
* bit fields for record[1]
*/
uint32_t addr_hi :32; /* bit 63:32, copy of msi/msi-x addr[63:32] */
uint32_t addr_31_16 :16; /* bit 31:16, copy of msi/msi-x addr[31:16] */
uint32_t data1 :16; /* bit 15:0, msi-x data[31:16], not valid for msi */
/*
* the rest of the records
*/
uint64_t record[6]; /* reserved */
} eq_record_t;
/*
* PCIE TLP Fmt[1:0] and Type[4:0] Field Encodings
*/
#define TLP_MRd_FMT_TYPE_IS32 0 /* 32-bit addressed memory read */
#define TLP_MRd_FMT_TYPE_IS64 (0x1<<5) /* 64-bit addressed memory read */
#define TLP_MWr_FMT_TYPE_IS32 (0x2<<5) /* 32-bit addressed memory write */
#define TLP_MWr_FMT_TYPE_IS64 (0x3<<5) /* 64-bit addressed memory write */
#define TLP_MSI_FMT_TYPE_IS32 ((0x2<<5) | (0x18)) /* 32-bit addressed MSI */
#define TLP_MSI_FMT_TYPE_IS64 ((0x3<<5) | (0x18)) /* 64-bit addressed MSI */
/*
* Macros, functions used for handling PCIE downbound transactions
*/
#define PCIE_BUS_NO_MASK MASK64(27,20)
#define PCIE_DEV_NO_MASK MASK64(19,15)
#define PCIE_FUN_NO_MASK MASK64(14,12)
#define PCIE_REG_NO_MASK MASK64(11, 0)
#define PCIE_BUS_NO_SHIFT 20
#define PCIE_DEV_NO_SHIFT 15
#define PCIE_FUN_NO_SHIFT 12
piu_region_t piu_decode_region(simcpu_t *sp, pcie_model_t *piup, uint64_t pa, uint64_t *offset);
bool_t piu_decode_cfgio(pcie_model_t *piup, uint64_t pa, uint64_t *offset);
bool_t piu_decode_mem32(pcie_model_t *piup, uint64_t pa, uint64_t *offset);
bool_t piu_decode_mem64(pcie_model_t *piup, uint64_t pa, uint64_t *offset);
bool_t piu_csr_access(simcpu_t *sp, pcie_model_t *piup, maccess_t op, uint64_t offset, uint64_t *regp);
bool_t piu_cfg_access(pcie_model_t *piup, maccess_t op, uint64_t ioaddr, uint32_t count, uint64_t *regp);
bool_t piu_io_access(pcie_model_t *piup, maccess_t op, uint64_t ioaddr, uint32_t count, uint64_t *regp);
bool_t piu_mem_access(pcie_model_t *piup, maccess_t op, uint64_t ioaddr, uint32_t count, uint64_t *regp,
pcie_space_t space_id);
/*
* Macros, functions used for handling PCIE upbound transactions
*/
bool_t piu_dma_access(pcie_model_t *piup, tvaddr_t va, uint8_t *datap, int count, uint16_t req_id,
dev_access_t type, dev_mode_t mode);
bool_t piu_assert_intx(pcie_model_t *piup, uint8_t pin, uint8_t dev_no);
bool_t piu_deassert_intx(pcie_model_t *piup, uint8_t pin, uint8_t dev_no);
bool_t piu_iommu(pcie_model_t *piup, tvaddr_t va, uint16_t req_id, dev_access_t type,
dev_mode_t mode, tpaddr_t *pa);
bool_t piu_iommu_sun4u(pcie_model_t *piup, tvaddr_t va, uint16_t req_id, dev_access_t type,
dev_mode_t mode, tpaddr_t *pa);
bool_t piu_iommu_sun4v(pcie_model_t *piup, tvaddr_t va, uint16_t req_id, dev_access_t type,
dev_mode_t mode, tpaddr_t *pa);
bool_t piu_iommu_va2pa(uint64_t tte, int ps, tvaddr_t va, uint16_t req_id, dev_access_t type,
dev_mode_t mode, tpaddr_t *pa);
void piu_set_irq_state(pcie_model_t *piup, uint8_t ino, irq_state_t new);
int piu_get_irq_state(pcie_model_t *piup, uint8_t ino);
void piu_set_intx_state(pcie_model_t *piup, uint8_t ino, irq_state_t new);
int piu_get_intx_state(pcie_model_t *piup, uint8_t ino);
void piu_mondo_interrupt(pcie_model_t *piup, uint8_t ino, irq_state_t new);
bool_t piu_eq_write(pcie_model_t *piup, int eqnum, eq_record_t *record, uint16_t req_id);
bool_t piu_msi_write(pcie_model_t *piup, uint64_t msi_addr, uint8_t *msi_datap, int count,
uint16_t req_id, dev_mode_t mode);
/*
* piu error handling routines
*/
void piu_init_error_list();
void piu_simulate_imu_error(pcie_model_t *piup, uint64_t error);
void piu_simulate_mmu_error(pcie_model_t *piup, uint64_t error);
void piu_raise_imu_error(pcie_model_t *piup, uint64_t error_code);
void piu_raise_mmu_error(pcie_model_t *piup, uint64_t error_code);
/*
* internal function prototypes
*/
void piu_register_pcie_device(pcie_model_t *piup, pcie_dev_inst_t *new);
pcie_csr_t piu_offset2reg(uint64_t offset, int *regx);
pcie_dev_inst_t *piu_find_pcie_dev(pcie_model_t *piup, void *dptr, pcie_space_t space);
#ifdef __cplusplus
}
#endif
#endif /* _PIU_H */
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