projects / OpenSPARC-T2-SAM / blame
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| 920dae64 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: niagara2_err_trap.h | |
| 5 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
| 6 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. | |
| 7 | * | |
| 8 | * The above named program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public | |
| 10 | * License version 2 as published by the Free Software Foundation. | |
| 11 | * | |
| 12 | * The above named program is distributed in the hope that it will be | |
| 13 | * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 15 | * General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public | |
| 18 | * License along with this work; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. | |
| 20 | * | |
| 21 | * ========== Copyright Header End ============================================ | |
| 22 | */ | |
| 23 | /* | |
| 24 | * Copyright 2007 Sun Microsystems, Inc. All rights reserved. | |
| 25 | * Use is subject to license terms. | |
| 26 | */ | |
| 27 | ||
| 28 | #pragma ident "@(#)niagara2_err_trap.h 1.9 07/02/20 SMI" | |
| 29 | ||
| 30 | #ifndef _NIAGARA2_ERR_TRAP_H_ | |
| 31 | #define _NIAGARA2_ERR_TRAP_H_ | |
| 32 | ||
| 33 | #ifdef __cplusplus | |
| 34 | extern "C" { | |
| 35 | #endif | |
| 36 | ||
| 37 | #ifdef NIAGARA2 /* { */ | |
| 38 | ||
| 39 | #if ERROR_TRAP_GEN /* { */ | |
| 40 | ||
| 41 | #include "ss_err_trap.h" | |
| 42 | #include "basics.h" | |
| 43 | ||
| 44 | /* | |
| 45 | * Per chip Error Trap state register. | |
| 46 | * This struct will hold all the CPU | |
| 47 | * specific state information related | |
| 48 | * to the various ESRs and EERs. | |
| 49 | */ | |
| 50 | typedef struct { | |
| 51 | uint64_t desr[64]; /* One per strand */ | |
| 52 | uint64_t clesr[8]; /* One per core */ | |
| 53 | uint64_t c_erer[8]; /* One per core */ | |
| 54 | uint64_t s_eter[64]; /* One per strand */ | |
| 55 | uint64_t dfesr[64]; /* One per strand */ | |
| 56 | } cpu_error_state_t; | |
| 57 | ||
| 58 | /* | |
| 59 | * Per-strand struct of pointers which | |
| 60 | * provides short-cut access to the | |
| 61 | * error registers defined in | |
| 62 | * cpu_error_state_t | |
| 63 | * | |
| 64 | * Make sure all these pointers are properly | |
| 65 | * initialized in ss_error_trap_init() | |
| 66 | */ | |
| 67 | typedef struct { | |
| 68 | uint64_t *desr_ptr; | |
| 69 | uint64_t *clesr_ptr; | |
| 70 | uint64_t *c_erer_ptr; | |
| 71 | uint64_t *s_eter_ptr; | |
| 72 | uint64_t *dfesr_ptr; | |
| 73 | } cpu_error_reg_t; | |
| 74 | ||
| 75 | ||
| 76 | #define CERER_MASK ( MASK64(63,61) | MASK64(59,58) | MASK64(55,52) | MASK64(50,50) \ | |
| 77 | | MASK64(48,46) | MASK64(40,36) | MASK64(33,27) | MASK64(23,23) \ | |
| 78 | | MASK64(21,0) ) | |
| 79 | ||
| 80 | #define CE_MASK ( MASK64(53,53) | MASK64(51,51) | MASK64(49,49) | MASK64(47,47) \ | |
| 81 | | MASK64(45,45) | MASK64(42,42) | MASK64(40,40) | MASK64(38,38) \ | |
| 82 | | MASK64(36,36) | MASK64(34,34) ) | |
| 83 | ||
| 84 | #define UE_MASK ( MASK64(52,52) | MASK64(50,50) | MASK64(48,48) | MASK64(46,46) \ | |
| 85 | | MASK64(44,44) | MASK64(43,43) | MASK64(41,41) | MASK64(39,39) \ | |
| 86 | | MASK64(37,37) ) | |
| 87 | ||
| 88 | #define DESR_MASK ( MASK64(60,56) | MASK64(10,0) ) | |
| 89 | ||
| 90 | #define DFESR_MASK MASK64(61,55) | |
| 91 | ||
| 92 | /* This trap never gets taken. The error info is forwarded to the core | |
| 93 | * with the err_inject_name given in the error entry in the table | |
| 94 | */ | |
| 95 | #define SS_CE_trap_forward_2_core NULL | |
| 96 | ||
| 97 | #define SS_UE_trap_forward_2_core NULL | |
| 98 | ||
| 99 | ||
| 100 | #endif /* } ERROR_TRAP_GEN */ | |
| 101 | ||
| 102 | extern bool_t n2_sp_interrupt(simcpu_t *sp, uint64_t intr_level, char* error_name); | |
| 103 | ||
| 104 | #endif /* } NIAGARA2*/ | |
| 105 | ||
| 106 | #ifdef __cplusplus | |
| 107 | } | |
| 108 | #endif | |
| 109 | ||
| 110 | #endif /* _NIAGARA2_ERR_TRAP_H_ */ |