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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / legion / src / procs / sunsparc / libniagara2 / niagara2_err_trap.c
CommitLineData
920dae64
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: niagara2_err_trap.c
5* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
6* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
7*
8* The above named program is free software; you can redistribute it and/or
9* modify it under the terms of the GNU General Public
10* License version 2 as published by the Free Software Foundation.
11*
12* The above named program is distributed in the hope that it will be
13* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
14* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15* General Public License for more details.
16*
17* You should have received a copy of the GNU General Public
18* License along with this work; if not, write to the Free Software
19* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
20*
21* ========== Copyright Header End ============================================
22*/
23/*
24 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
25 * Use is subject to license terms.
26 */
27#pragma ident "@(#)niagara2_err_trap.c 1.18 07/02/28 SMI"
28
29#include <stdio.h>
30#include <stdlib.h>
31#include <unistd.h>
32#include <string.h> /* memcpy/memset */
33#include <strings.h>
34#include <thread.h>
35
36#include "ss_common.h"
37#include "niagara2.h"
38
39#if ERROR_TRAP_GEN /* { */
40
41/* Core error registers */
42EAR_DEFINITION( isfsr );
43EIR_DEFINITION( isfsr );
44EAR_DEFINITION( dsfsr );
45EIR_DEFINITION( dsfsr );
46EAR_DEFINITION( desr );
47EIR_DEFINITION( desr );
48EAR_DEFINITION( c_erer );
49EAR_DEFINITION( s_eter );
50EAR_DEFINITION( clesr );
51EAR_DEFINITION( dfesr );
52EIR_DEFINITION( dfesr );
53
54/* L2$ error registers */
55EAR_DEFINITION( l2_b0_eer );
56EAR_DEFINITION( l2_b1_eer );
57EAR_DEFINITION( l2_b2_eer );
58EAR_DEFINITION( l2_b3_eer );
59EAR_DEFINITION( l2_b4_eer );
60EAR_DEFINITION( l2_b5_eer );
61EAR_DEFINITION( l2_b6_eer );
62EAR_DEFINITION( l2_b7_eer );
63
64EAR_DEFINITION( l2_b0_esr );
65EAR_DEFINITION( l2_b1_esr );
66EAR_DEFINITION( l2_b2_esr );
67EAR_DEFINITION( l2_b3_esr );
68EAR_DEFINITION( l2_b4_esr );
69EAR_DEFINITION( l2_b5_esr );
70EAR_DEFINITION( l2_b6_esr );
71EAR_DEFINITION( l2_b7_esr );
72
73EIR_DEFINITION( l2_b0_esr );
74EIR_DEFINITION( l2_b1_esr );
75EIR_DEFINITION( l2_b2_esr );
76EIR_DEFINITION( l2_b3_esr );
77EIR_DEFINITION( l2_b4_esr );
78EIR_DEFINITION( l2_b5_esr );
79EIR_DEFINITION( l2_b6_esr );
80EIR_DEFINITION( l2_b7_esr );
81
82EAR_DEFINITION( l2nd_b0_esr );
83EAR_DEFINITION( l2nd_b1_esr );
84EAR_DEFINITION( l2nd_b2_esr );
85EAR_DEFINITION( l2nd_b3_esr );
86EAR_DEFINITION( l2nd_b4_esr );
87EAR_DEFINITION( l2nd_b5_esr );
88EAR_DEFINITION( l2nd_b6_esr );
89EAR_DEFINITION( l2nd_b7_esr );
90
91EIR_DEFINITION( l2nd_b0_esr );
92EIR_DEFINITION( l2nd_b1_esr );
93EIR_DEFINITION( l2nd_b2_esr );
94EIR_DEFINITION( l2nd_b3_esr );
95EIR_DEFINITION( l2nd_b4_esr );
96EIR_DEFINITION( l2nd_b5_esr );
97EIR_DEFINITION( l2nd_b6_esr );
98EIR_DEFINITION( l2nd_b7_esr );
99
100/* DRAM error registers */
101EAR_DEFINITION( dram_b0_esr );
102EAR_DEFINITION( dram_b1_esr );
103EAR_DEFINITION( dram_b2_esr );
104EAR_DEFINITION( dram_b3_esr );
105EAR_DEFINITION( dram_b4_esr );
106EAR_DEFINITION( dram_b5_esr );
107EAR_DEFINITION( dram_b6_esr );
108EAR_DEFINITION( dram_b7_esr );
109
110EIR_DEFINITION( dram_b0_esr );
111EIR_DEFINITION( dram_b1_esr );
112EIR_DEFINITION( dram_b2_esr );
113EIR_DEFINITION( dram_b3_esr );
114EIR_DEFINITION( dram_b4_esr );
115EIR_DEFINITION( dram_b5_esr );
116EIR_DEFINITION( dram_b6_esr );
117EIR_DEFINITION( dram_b7_esr );
118
119static bool_t l2_esr_inject (int idx, EIR_ARGS);
120static uint64_t l2_esr_access (int idx, EAR_ARGS);
121static uint64_t l2_eer_access (int idx, EAR_ARGS);
122static bool_t l2nd_esr_inject (int idx, EIR_ARGS);
123static uint64_t l2nd_esr_access (int idx, EAR_ARGS);
124
125static bool_t dram_esr_inject (int idx, EIR_ARGS);
126static uint64_t dram_esr_access (int idx, EAR_ARGS);
127
128
129/*
130 * This routine will initilize all error trap
131 * related state which is associated with a
132 * particular ss_proc_t struct. For now just
133 * provides CPU error for generating traps which
134 * are not associated with any particular error.
135 */
136void ss_error_trap_proc_init(config_proc_t * config_procp) {
137
138/*
139 * Table of Error Registers supported by Niagara2:
140 * For Starters, we are only supporting:
141 *
142 * ESRs: ASI_CLESR
143 * ASI_DESR
144 *
145 * EERs: ASI_CERER
146 * ASI_SETER
147 *
148 *
149 */
150static ss_err_reg_t err_reg_table[] = {
151
152/* ESRs: */
153/* ASI VA Access Routine */
154
155{ SS_ASI_IMMU, 0x18, EAR( isfsr ) },
156{ SS_ASI_DMMU, 0x18, EAR( dsfsr ) },
157{ N2_ASI_DESR, 0x0, EAR( desr ) },
158{ N2_ASI_DESR, 0x20, EAR( clesr ) },
159{ N2_ASI_DESR, 0x8, EAR( dfesr ) },
160
161
162/* EERs: */
163/* ASI VA Access Routine */
164
165{ N2_ASI_DESR, 0x10, EAR( c_erer ) },
166{ N2_ASI_DESR, 0x18, EAR( s_eter ) },
167
168
169/* ASI VA Access Routine */
170
171{ INVALID_ASI, 0, NULL },
172};
173
174/*
175 * CPU specific table of CPU errors for which Legion supports
176 * error trap injection.
177 *
178 * For Starters, we only supporting
179 *
180 * ERRORs: ICVP
181 * ICTP
182 * ICTM
183 * ICDP
184 * DCVP
185 * DCTP
186 * DCTM
187 * DCDP
188 * L2C
189 * SBDPC
190 *
191 */
192static ss_error_entry_t error_table[] = {
193
194/* Error, Trap Type, Trap Class, persistent?, Target Strand */
195/* (init val only) */
196
197{ "ICVP", SS_trap_hw_corrected_error, DISRUPTING_TT, true, TARGET_MYSELF,
198
199/* error_status[] */ { EAR( desr ), EIR( desr ), ( MASK64(56,56) | MASK64(2,2) ), DESR_MASK },
200/* error_record[] */ { EAR( c_erer ), MASK64(18,18) },
201/* error_report[] */ { EAR( s_eter ), MASK64(60,60) },
202},
203
204
205{ "ICTP", SS_trap_hw_corrected_error, DISRUPTING_TT, true, TARGET_MYSELF,
206
207/* error_status[] */ { EAR( desr ), EIR( desr ), ( MASK64(57,57) | MASK64(2,2) ), DESR_MASK },
208/* error_record[] */ { EAR( c_erer ), MASK64(17,17) },
209/* error_report[] */ { EAR( s_eter ), MASK64(60,60) },
210},
211
212
213{ "ICTM", SS_trap_hw_corrected_error, DISRUPTING_TT, true, TARGET_MYSELF,
214
215/* error_status[] */ { EAR( desr ), EIR( desr ), ( MASK64(57,56) | MASK64(2,2) ), DESR_MASK },
216/* error_record[] */ { EAR( c_erer ), MASK64(16,16) },
217/* error_report[] */ { EAR( s_eter ), MASK64(60,60) },
218},
219
220
221{ "ICDP", SS_trap_hw_corrected_error, DISRUPTING_TT, true, TARGET_MYSELF,
222
223/* error_status[] */ { EAR( desr ), EIR( desr ), ( MASK64(58,58) | MASK64(2,2) ), DESR_MASK },
224/* error_record[] */ { EAR( c_erer ), MASK64(15,15) },
225/* error_report[] */ { EAR( s_eter ), MASK64(60,60) },
226},
227
228
229{ "DCVP", SS_trap_hw_corrected_error, DISRUPTING_TT, true, TARGET_MYSELF,
230
231/* error_status[] */ {EAR( desr ), EIR( desr ), ( MASK64(58,58) | MASK64(56,56) | MASK64(2,2) | MASK64(0,0) ), DESR_MASK },
232/* error_record[] */ {EAR( c_erer ), MASK64(14,14)},
233/* error_report[] */ {EAR( s_eter ), MASK64(60,60)},
234},
235
236
237{ "DCTP", SS_trap_hw_corrected_error, DISRUPTING_TT, true, TARGET_MYSELF,
238
239/* error_status[] */ { EAR( desr ), EIR( desr ), ( MASK64(58,57) | MASK64(2,2) | MASK64(0,0) ), DESR_MASK },
240/* error_record[] */ { EAR( c_erer ), MASK64(13,13) },
241/* error_report[] */ { EAR( s_eter ), MASK64(60,60) },
242},
243
244
245{ "DCTM", SS_trap_hw_corrected_error, DISRUPTING_TT, true, TARGET_MYSELF,
246
247/* error_status[] */ { EAR( desr ), EIR( desr ), ( MASK64(58,56) | MASK64(2,2) | MASK64(0,0) ), DESR_MASK },
248/* error_record[] */ { EAR( c_erer ), MASK64(12,12) },
249/* error_report[] */ { EAR( s_eter ), MASK64(60,60) },
250},
251
252
253{ "DCDP", SS_trap_hw_corrected_error, DISRUPTING_TT, true, TARGET_MYSELF,
254
255/* error_status[] */ { EAR( desr ), EIR( desr ), ( MASK64(59,59) | MASK64(2,2) | MASK64(0,0) ), DESR_MASK },
256/* error_record[] */ { EAR( c_erer ), MASK64(11,11) },
257/* error_report[] */ { EAR( s_eter ), MASK64(60,60) },
258},
259
260
261{ "L2C", SS_trap_hw_corrected_error, DISRUPTING_TT, false, TARGET_MYSELF,
262/* For now assigning it to current strand. Need set esr to ERRORSTEER */
263
264/* error_status[] */ { EAR( desr ), EIR( desr ), ( MASK64(59,59) | MASK64(56,56) | MASK64(1,0) ), DESR_MASK },
265/* error_record[] */ { EAR( c_erer ), MASK64(21,21) },
266/* error_report[] */ { EAR( s_eter ), MASK64(60,60) },
267},
268
269
270{ "L2C_CE_ECC", SS_trap_sw_recoverable_error, DISRUPTING_TT, false, TARGET_MYSELF,
271/* For now assigning it to current strand. Need set esr to ERRORSTEER */
272
273/* error_status[] */ { EAR( desr ), EIR( desr ), ( MASK64(60,60) | MASK64(58,58) | MASK64(1,0) ), DESR_MASK },
274/* error_record[] */ { EAR( c_erer ), MASK64(21,21) },
275/* error_report[] */ { EAR( s_eter ), MASK64(61,61) },
276},
277
278
279{ "SBDPC", SS_trap_hw_corrected_error, DISRUPTING_TT, true, TARGET_MYSELF,
280
281/* error_status[] */ { EAR( desr ), EIR( desr ), ( MASK64(59,59) | MASK64(57,57) | MASK64(1,0) ), DESR_MASK },
282/* error_record[] */ { EAR( c_erer ), MASK64(10,10) },
283/* error_report[] */ { EAR( s_eter ), MASK64(60,60) },
284},
285
286
287{ "SBDPU", SS_trap_sw_recoverable_error, DISRUPTING_TT, true, TARGET_MYSELF,
288
289/* error_status[] */ { EAR( desr ), EIR( desr ), MASK64(58,57) | MASK64(2,1), DESR_MASK },
290/* error_record[] */ { EAR( c_erer ), MASK64(9,9) },
291/* error_report[] */ { EAR( s_eter ), MASK64(61,61) },
292},
293
294
295{ "ITTM", SS_trap_instruction_access_MMU_error, PRECISE_TT, true, TARGET_MYSELF,
296
297/* error_status[] */ { EAR( isfsr ), EIR( isfsr ), MASK64(0,0), MMU_SFSR_MASK },
298/* error_record[] */ { EAR( c_erer ), MASK64(61,61) },
299/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
300},
301
302{ "ITTP", SS_trap_instruction_access_MMU_error, PRECISE_TT, true, TARGET_MYSELF,
303
304/* error_status[] */ { EAR( isfsr ), EIR( isfsr ), MASK64(1,1),MMU_SFSR_MASK },
305/* error_record[] */ { EAR( c_erer ), MASK64(63,63) },
306/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
307},
308
309{ "ITDP", SS_trap_instruction_access_MMU_error, PRECISE_TT, true, TARGET_MYSELF,
310
311/* error_status[] */ { EAR( isfsr ), EIR( isfsr ), MASK64(1,0), MMU_SFSR_MASK },
312/* error_record[] */ { EAR( c_erer ), MASK64(62,62) },
313/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
314},
315
316{ "ITMU", SS_trap_instruction_access_MMU_error, PRECISE_TT, true, TARGET_MYSELF,
317
318/* error_status[] */ { EAR( isfsr ), EIR( isfsr ), MASK64(2,2), MMU_SFSR_MASK },
319/* error_record[] */ { EAR( c_erer ), MASK64(59,59) },
320/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
321},
322
323{ "DTTM", SS_trap_data_access_MMU_error, PRECISE_TT, true, TARGET_MYSELF,
324
325/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(0,0), MMU_SFSR_MASK },
326/* error_record[] */ { EAR( c_erer ), MASK64(47,47) },
327/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
328},
329
330{ "DTTP", SS_trap_data_access_MMU_error, PRECISE_TT, true, TARGET_MYSELF,
331
332/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(1,1), MMU_SFSR_MASK },
333/* error_record[] */ { EAR( c_erer ), MASK64(48,48) },
334/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
335},
336
337{ "DTDP", SS_trap_data_access_MMU_error, PRECISE_TT, true, TARGET_MYSELF,
338
339/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(1,0), MMU_SFSR_MASK },
340/* error_record[] */ { EAR( c_erer ), MASK64(46,46) },
341/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
342},
343
344{ "DTMU", SS_trap_data_access_MMU_error, PRECISE_TT, true, TARGET_MYSELF,
345
346/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(2,2), MMU_SFSR_MASK },
347/* error_record[] */ { EAR( c_erer ), MASK64(59,59) },
348/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
349},
350
351{ "ITL2C", SS_trap_sw_recoverable_error, DISRUPTING_TT, false, TARGET_MYSELF,
352/* For now assigning it to current strand. Need set esr to ERRORSTEER */
353
354/* error_status[] */ { EAR( desr ), EIR( desr ), MASK64(56,56), DESR_MASK },
355/* error_record[] */ { EAR( c_erer ), MASK64(58,58) },
356/* error_report[] */ { EAR( s_eter ), MASK64(61,61) },
357},
358
359
360{ "ICL2C", SS_trap_sw_recoverable_error, DISRUPTING_TT, false, TARGET_MYSELF,
361/* For now assigning it to current strand. Need set esr to ERRORSTEER */
362
363/* error_status[] */ { EAR( desr ), EIR( desr ), MASK64(57,57), DESR_MASK },
364/* error_record[] */ { EAR( c_erer ), MASK64(55,55) },
365/* error_report[] */ { EAR( s_eter ), MASK64(61,61) },
366},
367
368
369{ "DTL2C", SS_trap_sw_recoverable_error, DISRUPTING_TT, false, TARGET_MYSELF,
370/* For now assigning it to current strand. Need set esr to ERRORSTEER */
371
372/* error_status[] */ { EAR( desr ), EIR( desr ), MASK64(57,56), DESR_MASK },
373/* error_record[] */ { EAR( c_erer ), MASK64(58,58) },
374/* error_report[] */ { EAR( s_eter ), MASK64(61,61) },
375},
376
377
378{ "DCL2C", SS_trap_sw_recoverable_error, DISRUPTING_TT, false, TARGET_MYSELF,
379/* For now assigning it to current strand. Need set esr to ERRORSTEER */
380
381/* error_status[] */ { EAR( desr ), EIR( desr ), MASK64(58,58), DESR_MASK },
382/* error_record[] */ { EAR( c_erer ), MASK64(40,40) },
383/* error_report[] */ { EAR( s_eter ), MASK64(61,61) },
384},
385
386
387{ "MAL2C", SS_trap_sw_recoverable_error, DISRUPTING_TT, false, TARGET_MYSELF,
388/* For now assigning it to current strand. Need to assign to the STRAND field of MA_CTL reg*/
389
390/* error_status[] */ { EAR( desr ), EIR( desr ), MASK64(59,59), DESR_MASK },
391/* error_record[] */ { EAR( c_erer ), MASK64(5,5) },
392/* error_report[] */ { EAR( s_eter ), MASK64(61,61) },
393},
394
395
396{ "CWQL2C", SS_trap_sw_recoverable_error, DISRUPTING_TT, false, TARGET_MYSELF,
397/* For now assigning it to current strand. Need to assign to the CoreID field of the CWQ entry*/
398
399/* error_status[] */ { EAR( desr ), EIR( desr ), MASK64(59,59)|MASK64(57,56), DESR_MASK },
400/* error_record[] */ { EAR( c_erer ), MASK64(2,2) },
401/* error_report[] */ { EAR( s_eter ), MASK64(61,61) },
402},
403
404
405{ "IRFU", SS_trap_internal_processor_error, PRECISE_TT, false, TARGET_MYSELF,
406
407/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(0,0), MMU_SFSR_MASK },
408/* error_record[] */ { EAR( c_erer ), MASK64(52,52) },
409/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
410},
411
412
413{ "IRFC", SS_trap_internal_processor_error, PRECISE_TT, false, TARGET_MYSELF,
414
415/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(1,1), MMU_SFSR_MASK },
416/* error_record[] */ { EAR( c_erer ), MASK64(52,52) },
417/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
418},
419
420
421{ "FRFU", SS_trap_internal_processor_error, PRECISE_TT, false, TARGET_MYSELF,
422
423/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(1,0), MMU_SFSR_MASK },
424/* error_record[] */ { EAR( c_erer ), MASK64(50,50) },
425/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
426},
427
428
429{ "FRFC", SS_trap_internal_processor_error, PRECISE_TT, false, TARGET_MYSELF,
430
431/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(2,2), MMU_SFSR_MASK },
432/* error_record[] */ { EAR( c_erer ), MASK64(50,50) },
433/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
434},
435
436
437{ "SBDLU", SS_trap_internal_processor_error, PRECISE_TT, false, TARGET_MYSELF,
438
439/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(2,1), MMU_SFSR_MASK },
440/* error_record[] */ { EAR( c_erer ), MASK64(36,36) },
441/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
442},
443
444
445{ "SBDLC", SS_trap_internal_processor_error, PRECISE_TT, false, TARGET_MYSELF,
446
447/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(2,2)|MASK64(0,0), MMU_SFSR_MASK },
448/* error_record[] */ { EAR( c_erer ), MASK64(37,37) },
449/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
450},
451
452
453{ "SCAC", SS_trap_internal_processor_error, PRECISE_TT, false, TARGET_MYSELF,
454
455/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(3,3)|MASK64(1,1), MMU_SFSR_MASK },
456/* error_record[] */ { EAR( c_erer ), MASK64(30,30) },
457/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
458},
459
460
461{ "SCAU", SS_trap_internal_processor_error, PRECISE_TT, false, TARGET_MYSELF,
462
463/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(3,3)|MASK64(1,0), MMU_SFSR_MASK },
464/* error_record[] */ { EAR( c_erer ), MASK64(29,29) },
465/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
466},
467
468
469{ "TCCP", SS_trap_internal_processor_error, PRECISE_TT, false, TARGET_MYSELF,
470
471/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(3,2), MMU_SFSR_MASK },
472/* error_record[] */ { EAR( c_erer ), MASK64(28,28) },
473/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
474},
475
476
477{ "TCUP", SS_trap_internal_processor_error, PRECISE_TT, false, TARGET_MYSELF,
478
479/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(3,2)|MASK64(0,0), MMU_SFSR_MASK },
480/* error_record[] */ { EAR( c_erer ), MASK64(27,27) },
481/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
482},
483
484
485{ "TCCD", SS_trap_sw_recoverable_error, DISRUPTING_TT, false, TARGET_MYSELF,
486
487/* error_status[] */ { EAR( desr ), EIR( desr ), MASK64(59,57), DESR_MASK },
488/* error_record[] */ { EAR( c_erer ), MASK64(7,7) },
489/* error_report[] */ { EAR( s_eter ), MASK64(61,61) },
490},
491
492
493{ "TCUD", SS_trap_sw_recoverable_error, DISRUPTING_TT, false, TARGET_MYSELF,
494
495/* error_status[] */ { EAR( desr ), EIR( desr ), MASK64(59,56), DESR_MASK },
496/* error_record[] */ { EAR( c_erer ), MASK64(6,6) },
497/* error_report[] */ { EAR( s_eter ), MASK64(61,61) },
498},
499
500
501{ "TSAC", SS_trap_internal_processor_error, PRECISE_TT, false, TARGET_MYSELF,
502
503/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(3,3), MMU_SFSR_MASK },
504/* error_record[] */ { EAR( c_erer ), MASK64(32,32) },
505/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
506},
507
508
509{ "TSAU", SS_trap_internal_processor_error, PRECISE_TT, false, TARGET_MYSELF,
510
511/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(3,3)|MASK64(0,0), MMU_SFSR_MASK },
512/* error_record[] */ { EAR( c_erer ), MASK64(31,31) },
513/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
514},
515
516
517{ "MRAU", SS_trap_internal_processor_error, PRECISE_TT, false, TARGET_MYSELF,
518
519/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(2,0), MMU_SFSR_MASK },
520/* error_record[] */ { EAR( c_erer ), MASK64(33,33) },
521/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
522},
523
524
525{ "SBDIOU", N2_trap_store_error, DEFERRED_TT, false, TARGET_MYSELF,
526
527/* error_status[] */ { EAR( dfesr ), EIR( dfesr ), MASK64(60,60), DFESR_MASK },
528/* error_record[] */ { EAR( c_erer ), MASK64(9,9) },
529/* error_report[] */ { NULL, 0 },
530},
531
532
533{ "SBAPP", N2_trap_store_error, DEFERRED_TT, false, TARGET_MYSELF,
534
535/* error_status[] */ { EAR( dfesr ), EIR( dfesr ), MASK64(61,61), DFESR_MASK },
536/* error_record[] */ { EAR( c_erer ), MASK64(23,23) },
537/* error_report[] */ { NULL, 0 },
538},
539
540
541{ "ITL2U", SS_trap_instruction_access_MMU_error, PRECISE_TT, false, TARGET_MYSELF,
542
543/* error_status[] */ { EAR( isfsr ), EIR( isfsr ), MASK64(2,2)|MASK64(0,0), DESR_MASK },
544/* error_record[] */ { EAR( c_erer ), MASK64(58,58) },
545/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
546},
547
548
549{ "DTL2U", SS_trap_data_access_MMU_error, PRECISE_TT, false, TARGET_MYSELF,
550
551/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(2,2)|MASK64(0,0), DESR_MASK },
552/* error_record[] */ { EAR( c_erer ), MASK64(58,58) },
553/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
554},
555
556
557{ "ICL2U", SS_trap_instruction_access_error, PRECISE_TT, false, TARGET_MYSELF,
558
559/* error_status[] */ { EAR( isfsr ), EIR( isfsr ), MASK64(0,0), DESR_MASK },
560/* error_record[] */ { EAR( c_erer ), MASK64(54,54) },
561/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
562},
563
564
565{ "DCL2U", SS_trap_data_access_error, PRECISE_TT, false, TARGET_MYSELF,
566
567/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(0,0), DESR_MASK },
568/* error_record[] */ { EAR( c_erer ), MASK64(39,39) },
569/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
570},
571
572
573{ "L2U", SS_trap_sw_recoverable_error, DISRUPTING_TT, false, TARGET_MYSELF,
574
575/* error_status[] */ { EAR( desr ), EIR( desr ), MASK64(60,60), DESR_MASK },
576/* error_record[] */ { EAR( c_erer ), MASK64(20,20) },
577/* error_report[] */ { EAR( s_eter ), MASK64(61,61) },
578},
579
580
581{ "L2U_PART_ST", SS_trap_sw_recoverable_error, DISRUPTING_TT, false, TARGET_MYSELF,
582
583/* error_status[] */ { EAR( desr ), EIR( desr ), MASK64(60,60), DESR_MASK },
584/* error_record[] */ { EAR( c_erer ), MASK64(20,20) },
585/* error_report[] */ { EAR( s_eter ), MASK64(60,60) },
586},
587
588
589{ "CWQL2U", SS_trap_sw_recoverable_error, DISRUPTING_TT, false, TARGET_MYSELF,
590
591/* error_status[] */ { EAR( desr ), EIR( desr ), MASK64(59,58), DESR_MASK },
592/* error_record[] */ { EAR( c_erer ), MASK64(1,1) },
593/* error_report[] */ { EAR( s_eter ), MASK64(61,61) },
594},
595
596
597{ "MAL2U", SS_trap_sw_recoverable_error, DISRUPTING_TT, false, TARGET_MYSELF,
598
599/* error_status[] */ { EAR( desr ), EIR( desr ), MASK64(59,59)|MASK64(56,56), DESR_MASK },
600/* error_record[] */ { EAR( c_erer ), MASK64(4,4) },
601/* error_report[] */ { EAR( s_eter ), MASK64(61,61) },
602},
603
604{ "ITL2ND", SS_trap_instruction_access_MMU_error, PRECISE_TT, false, TARGET_MYSELF,
605
606/* error_status[] */ { EAR( isfsr ), EIR( isfsr ), MASK64(2,1), DESR_MASK },
607/* error_record[] */ { EAR( c_erer ), MASK64(58,58) },
608/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
609},
610
611
612{ "DTL2ND", SS_trap_data_access_MMU_error, PRECISE_TT, false, TARGET_MYSELF,
613
614/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(2,1), DESR_MASK },
615/* error_record[] */ { EAR( c_erer ), MASK64(58,58) },
616/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
617},
618
619
620{ "ICL2ND", SS_trap_instruction_access_error, PRECISE_TT, false, TARGET_MYSELF,
621
622/* error_status[] */ { EAR( isfsr ), EIR( isfsr ), MASK64(1,1), DESR_MASK },
623/* error_record[] */ { EAR( c_erer ), MASK64(53,53) },
624/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
625},
626
627
628{ "DCL2ND", SS_trap_data_access_error, PRECISE_TT, false, TARGET_MYSELF,
629
630/* error_status[] */ { EAR( dsfsr ), EIR( dsfsr ), MASK64(1,1), DESR_MASK },
631/* error_record[] */ { EAR( c_erer ), MASK64(38,38) },
632/* error_report[] */ { EAR( s_eter ), MASK64(62,62) },
633},
634
635
636{ "L2ND", SS_trap_sw_recoverable_error, DISRUPTING_TT, false, TARGET_MYSELF,
637
638/* error_status[] */ { EAR( desr ), EIR( desr ), MASK64(60,60)|MASK64(56,56), DESR_MASK },
639/* error_record[] */ { EAR( c_erer ), MASK64(19,19) },
640/* error_report[] */ { EAR( s_eter ), MASK64(61,61) },
641},
642
643
644{ "CWQL2ND", SS_trap_sw_recoverable_error, DISRUPTING_TT, false, TARGET_MYSELF,
645
646/* error_status[] */ { EAR( desr ), EIR( desr ), MASK64(59,58)|MASK64(56,56), DESR_MASK },
647/* error_record[] */ { EAR( c_erer ), MASK64(0,0) },
648/* error_report[] */ { EAR( s_eter ), MASK64(61,61) },
649},
650
651
652{ "MAL2ND", SS_trap_sw_recoverable_error, DISRUPTING_TT, false, TARGET_MYSELF,
653
654/* error_status[] */ { EAR( desr ), EIR( desr ), MASK64(59,59)|MASK64(57,57), DESR_MASK },
655/* error_record[] */ { EAR( c_erer ), MASK64(3,3) },
656/* error_report[] */ { EAR( s_eter ), MASK64(61,61) },
657},
658
659/*
660 * L2$ Errors. These errors are not persistent because the framework doesn't have the required functionality for
661 * for these error. The functionality will be added if required in the future.
662 */
663
664{ "LDWC_0", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
665
666/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(51,51), NULL, "L2C" },
667/* error_record[] */ { NULL, 0 },
668/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
669},
670
671
672{ "LDWC_1", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
673
674/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(51,51), NULL, "L2C" },
675/* error_record[] */ { NULL, 0 },
676/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
677},
678
679
680{ "LDWC_2", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
681
682/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(51,51), NULL, "L2C" },
683/* error_record[] */ { NULL, 0 },
684/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
685},
686
687
688{ "LDWC_3", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
689
690/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(51,51), NULL, "L2C" },
691/* error_record[] */ { NULL, 0 },
692/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
693},
694
695
696{ "LDWC_4", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
697
698/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(51,51), NULL, "L2C" },
699/* error_record[] */ { NULL, 0 },
700/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
701},
702
703
704{ "LDWC_5", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
705
706/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(51,51), NULL, "L2C" },
707/* error_record[] */ { NULL, 0 },
708/* error_report[] */ { EAR( l2_b5_eer ), MASK64(0,0) },
709},
710
711
712{ "LDWC_6", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
713
714/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(51,51), NULL, "L2C" },
715/* error_record[] */ { NULL, 0 },
716/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
717},
718
719
720{ "LDWC_7", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
721
722/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(51,51), NULL, "L2C" },
723/* error_record[] */ { NULL, 0 },
724/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
725},
726
727{ "LDSC_0", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
728
729/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(47,47), NULL, "L2C" },
730/* error_record[] */ { NULL, 0 },
731/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
732},
733
734
735{ "LDSC_1", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
736
737/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(47,47), NULL, "L2C" },
738/* error_record[] */ { NULL, 0 },
739/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
740},
741
742
743{ "LDSC_2", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
744
745/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(47,47), NULL, "L2C" },
746/* error_record[] */ { NULL, 0 },
747/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
748},
749
750
751{ "LDSC_3", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
752
753/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(47,47), NULL, "L2C" },
754/* error_record[] */ { NULL, 0 },
755/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
756},
757
758
759{ "LDSC_4", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
760
761/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(47,47), NULL, "L2C" },
762/* error_record[] */ { NULL, 0 },
763/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
764},
765
766
767{ "LDSC_5", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
768
769/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(47,47), NULL, "L2C" },
770/* error_record[] */ { NULL, 0 },
771/* error_report[] */ { EAR( l2_b5_eer ), MASK64(0,0) },
772},
773
774
775{ "LDSC_6", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
776
777/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(47,47), NULL, "L2C" },
778/* error_record[] */ { NULL, 0 },
779/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
780},
781
782
783{ "LDSC_7", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
784
785/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(47,47), NULL, "L2C" },
786/* error_record[] */ { NULL, 0 },
787/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
788},
789
790{ "LTC_0", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
791
792/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(45,45), NULL, "L2C" },
793/* error_record[] */ { NULL, 0 },
794/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
795},
796
797
798{ "LTC_1", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
799
800/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(45,45), NULL, "L2C" },
801/* error_record[] */ { NULL, 0 },
802/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
803},
804
805
806{ "LTC_2", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
807
808/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(45,45), NULL, "L2C" },
809/* error_record[] */ { NULL, 0 },
810/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
811},
812
813
814{ "LTC_3", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
815
816/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(45,45), NULL, "L2C" },
817/* error_record[] */ { NULL, 0 },
818/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
819},
820
821
822{ "LTC_4", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
823
824/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(45,45), NULL, "L2C" },
825/* error_record[] */ { NULL, 0 },
826/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
827},
828
829
830{ "LTC_5", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
831
832/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(45,45), NULL, "L2C" },
833/* error_record[] */ { NULL, 0 },
834/* error_report[] */ { EAR( l2_b5_eer ), MASK64(0,0) },
835},
836
837
838{ "LTC_6", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
839
840/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(45,45), NULL, "L2C" },
841/* error_record[] */ { NULL, 0 },
842/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
843},
844
845
846{ "LTC_7", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
847
848/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(45,45), NULL, "L2C" },
849/* error_record[] */ { NULL, 0 },
850/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
851},
852
853{ "LVC_0", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
854
855/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(34,34), NULL, "L2C" },
856/* error_record[] */ { NULL, 0 },
857/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
858},
859
860
861{ "LVC_1", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
862
863/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(34,34), NULL, "L2C" },
864/* error_record[] */ { NULL, 0 },
865/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
866},
867
868
869{ "LVC_2", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
870
871/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(34,34), NULL, "L2C" },
872/* error_record[] */ { NULL, 0 },
873/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
874},
875
876
877{ "LVC_3", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
878
879/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(34,34), NULL, "L2C" },
880/* error_record[] */ { NULL, 0 },
881/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
882},
883
884
885{ "LVC_4", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
886
887/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(34,34), NULL, "L2C" },
888/* error_record[] */ { NULL, 0 },
889/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
890},
891
892
893{ "LVC_5", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
894
895/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(34,34), NULL, "L2C" },
896/* error_record[] */ { NULL, 0 },
897/* error_report[] */ { EAR( l2_b5_eer ), MASK64(0,0) },
898},
899
900
901{ "LVC_6", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
902
903/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(34,34), NULL, "L2C" },
904/* error_record[] */ { NULL, 0 },
905/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
906},
907
908
909{ "LVC_7", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
910
911/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(34,34), NULL, "L2C" },
912/* error_record[] */ { NULL, 0 },
913/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
914},
915
916
917{ "ITL2C_0", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
918
919/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(53,53), NULL, "ITL2C" },
920/* error_record[] */ { NULL, 0 },
921/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
922},
923
924
925{ "ITL2C_1", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
926
927/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(53,53), NULL, "ITL2C" },
928/* error_record[] */ { NULL, 0 },
929/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
930},
931
932
933{ "ITL2C_2", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
934
935/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(53,53), NULL, "ITL2C" },
936/* error_record[] */ { NULL, 0 },
937/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
938},
939
940
941{ "ITL2C_3", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
942
943/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(53,53), NULL, "ITL2C" },
944/* error_record[] */ { NULL, 0 },
945/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
946},
947
948
949{ "ITL2C_4", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
950
951/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(53,53), NULL, "ITL2C" },
952/* error_record[] */ { NULL, 0 },
953/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
954},
955
956
957{ "ITL2C_5", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
958
959/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(53,53), NULL, "ITL2C" },
960/* error_record[] */ { NULL, 0 },
961/* error_report[] */ { EAR( l2_b5_eer ), MASK64(0,0) },
962},
963
964
965{ "ITL2C_6", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
966
967/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(53,53), NULL, "ITL2C" },
968/* error_record[] */ { NULL, 0 },
969/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
970},
971
972
973{ "ITL2C_7", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
974
975/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(53,53), NULL, "ITL2C" },
976/* error_record[] */ { NULL, 0 },
977/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
978},
979
980
981{ "ICL2C_0", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
982
983/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(53,53), NULL, "ICL2C" },
984/* error_record[] */ { NULL, 0 },
985/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
986},
987
988
989{ "ICL2C_1", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
990
991/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(53,53), NULL, "ICL2C" },
992/* error_record[] */ { NULL, 0 },
993/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
994},
995
996
997{ "ICL2C_2", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
998
999/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(53,53), NULL, "ICL2C" },
1000/* error_record[] */ { NULL, 0 },
1001/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
1002},
1003
1004
1005{ "ICL2C_3", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1006
1007/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(53,53), NULL, "ICL2C" },
1008/* error_record[] */ { NULL, 0 },
1009/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
1010},
1011
1012
1013{ "ICL2C_4", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1014
1015/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(53,53), NULL, "ICL2C" },
1016/* error_record[] */ { NULL, 0 },
1017/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
1018},
1019
1020
1021{ "ICL2C_5", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1022
1023/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(53,53), NULL, "ICL2C" },
1024/* error_record[] */ { NULL, 0 },
1025/* error_report[] */ { EAR( l2_b5_eer ), MASK64(0,0) },
1026},
1027
1028
1029{ "ICL2C_6", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1030
1031/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(53,53), NULL, "ICL2C" },
1032/* error_record[] */ { NULL, 0 },
1033/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
1034},
1035
1036
1037{ "ICL2C_7", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1038
1039/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(53,53), NULL, "ICL2C" },
1040/* error_record[] */ { NULL, 0 },
1041/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
1042},
1043
1044
1045{ "DTL2C_0", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1046
1047/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(53,53), NULL, "DTL2C" },
1048/* error_record[] */ { NULL, 0 },
1049/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
1050},
1051
1052
1053{ "DTL2C_1", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1054
1055/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(53,53), NULL, "DTL2C" },
1056/* error_record[] */ { NULL, 0 },
1057/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
1058},
1059
1060
1061{ "DTL2C_2", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1062
1063/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(53,53), NULL, "DTL2C" },
1064/* error_record[] */ { NULL, 0 },
1065/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
1066},
1067
1068
1069{ "DTL2C_3", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1070
1071/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(53,53), NULL, "DTL2C" },
1072/* error_record[] */ { NULL, 0 },
1073/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
1074},
1075
1076
1077{ "DTL2C_4", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1078
1079/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(53,53), NULL, "DTL2C" },
1080/* error_record[] */ { NULL, 0 },
1081/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
1082},
1083
1084
1085{ "DTL2C_5", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1086
1087/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(53,53), NULL, "DTL2C" },
1088/* error_record[] */ { NULL, 0 },
1089/* error_report[] */ { EAR( l2_b5_eer ), MASK64(0,0) },
1090},
1091
1092
1093{ "DTL2C_6", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1094
1095/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(53,53), NULL, "DTL2C" },
1096/* error_record[] */ { NULL, 0 },
1097/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
1098},
1099
1100
1101{ "DTL2C_7", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1102
1103/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(53,53), NULL, "DTL2C" },
1104/* error_record[] */ { NULL, 0 },
1105/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
1106},
1107
1108
1109/* Load Hit DCL2C Errors */
1110{ "DCL2C_LD_0", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1111
1112/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(53,53), NULL, "DCL2C" },
1113/* error_record[] */ { NULL, 0 },
1114/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
1115},
1116
1117
1118{ "DCL2C_LD_1", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1119
1120/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(53,53), NULL, "DCL2C" },
1121/* error_record[] */ { NULL, 0 },
1122/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
1123},
1124
1125
1126{ "DCL2C_LD_2", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1127
1128/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(53,53), NULL, "DCL2C" },
1129/* error_record[] */ { NULL, 0 },
1130/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
1131},
1132
1133
1134{ "DCL2C_LD_3", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1135
1136/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(53,53), NULL, "DCL2C" },
1137/* error_record[] */ { NULL, 0 },
1138/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
1139},
1140
1141
1142{ "DCL2C_LD_4", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1143
1144/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(53,53), NULL, "DCL2C" },
1145/* error_record[] */ { NULL, 0 },
1146/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
1147},
1148
1149
1150{ "DCL2C_LD_5", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1151
1152/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(53,53), NULL, "DCL2C" },
1153/* error_record[] */ { NULL, 0 },
1154/* error_report[] */ { EAR( l2_b5_eer ), MASK64(0,0) },
1155},
1156
1157
1158{ "DCL2C_LD_6", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1159
1160/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(53,53), NULL, "DCL2C" },
1161/* error_record[] */ { NULL, 0 },
1162/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
1163},
1164
1165
1166{ "DCL2C_LD_7", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1167
1168/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(53,53), NULL, "DCL2C" },
1169/* error_record[] */ { NULL, 0 },
1170/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
1171},
1172
1173
1174/* Prefetch Hit Errors */
1175{ "L2C_PREFETCH_0", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1176
1177/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(53,53), NULL, "L2C_CE_ECC" },
1178/* error_record[] */ { NULL, 0 },
1179/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
1180},
1181
1182
1183{ "L2C_PREFETCH_1", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1184
1185/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(53,53), NULL, "L2C_CE_ECC" },
1186/* error_record[] */ { NULL, 0 },
1187/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
1188},
1189
1190
1191{ "L2C_PREFETCH_2", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1192
1193/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(53,53), NULL, "L2C_CE_ECC" },
1194/* error_record[] */ { NULL, 0 },
1195/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
1196},
1197
1198
1199{ "L2C_PREFETCH_3", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1200
1201/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(53,53), NULL, "L2C_CE_ECC" },
1202/* error_record[] */ { NULL, 0 },
1203/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
1204},
1205
1206
1207{ "L2C_PREFETCH_4", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1208
1209/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(53,53), NULL, "L2C_CE_ECC" },
1210/* error_record[] */ { NULL, 0 },
1211/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
1212},
1213
1214
1215{ "L2C_PREFETCH_5", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1216
1217/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(53,53), NULL, "L2C_CE_ECC" },
1218/* error_record[] */ { NULL, 0 },
1219/* error_report[] */ { EAR( l2_b5_eer ), MASK64(0,0) },
1220},
1221
1222
1223{ "L2C_PREFETCH_6", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1224
1225/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(53,53), NULL, "L2C_CE_ECC" },
1226/* error_record[] */ { NULL, 0 },
1227/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
1228},
1229
1230
1231{ "L2C_PREFETCH_7", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1232
1233/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(53,53), NULL, "L2C_CE_ECC" },
1234/* error_record[] */ { NULL, 0 },
1235/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
1236},
1237
1238
1239
1240/* Partial Store Hit/CWQ Partial Store Hit DCL2C Errors */
1241{ "DCL2C_ST_0", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1242
1243/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(53,53), NULL, "L2C" },
1244/* error_record[] */ { NULL, 0 },
1245/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
1246},
1247
1248
1249{ "DCL2C_ST_1", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1250
1251/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(53,53), NULL, "L2C" },
1252/* error_record[] */ { NULL, 0 },
1253/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
1254},
1255
1256
1257{ "DCL2C_ST_2", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1258
1259/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(53,53), NULL, "L2C" },
1260/* error_record[] */ { NULL, 0 },
1261/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
1262},
1263
1264
1265{ "DCL2C_ST_3", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1266
1267/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(53,53), NULL, "L2C" },
1268/* error_record[] */ { NULL, 0 },
1269/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
1270},
1271
1272
1273{ "DCL2C_ST_4", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1274
1275/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(53,53), NULL, "L2C" },
1276/* error_record[] */ { NULL, 0 },
1277/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
1278},
1279
1280
1281{ "DCL2C_ST_5", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1282
1283/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(53,53), NULL, "L2C" },
1284/* error_record[] */ { NULL, 0 },
1285/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
1286},
1287
1288
1289{ "DCL2C_ST_6", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1290
1291/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(53,53), NULL, "L2C" },
1292/* error_record[] */ { NULL, 0 },
1293/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
1294},
1295
1296
1297{ "DCL2C_ST_7", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1298
1299/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(53,53), NULL, "L2C" },
1300/* error_record[] */ { NULL, 0 },
1301/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
1302},
1303
1304
1305{ "MAL2C_0", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1306
1307/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(53,53), NULL, "MAL2C" },
1308/* error_record[] */ { NULL, 0 },
1309/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
1310},
1311
1312
1313{ "MAL2C_1", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1314
1315/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(53,53), NULL, "MAL2C" },
1316/* error_record[] */ { NULL, 0 },
1317/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
1318},
1319
1320
1321{ "MAL2C_2", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1322
1323/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(53,53), NULL, "MAL2C" },
1324/* error_record[] */ { NULL, 0 },
1325/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
1326},
1327
1328
1329{ "MAL2C_3", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1330
1331/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(53,53), NULL, "MAL2C" },
1332/* error_record[] */ { NULL, 0 },
1333/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
1334},
1335
1336
1337{ "MAL2C_4", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1338
1339/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(53,53), NULL, "MAL2C" },
1340/* error_record[] */ { NULL, 0 },
1341/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
1342},
1343
1344
1345{ "MAL2C_5", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1346
1347/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(53,53), NULL, "MAL2C" },
1348/* error_record[] */ { NULL, 0 },
1349/* error_report[] */ { EAR( l2_b5_eer ), MASK64(0,0) },
1350},
1351
1352
1353{ "MAL2C_6", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1354
1355/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(53,53), NULL, "MAL2C" },
1356/* error_record[] */ { NULL, 0 },
1357/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
1358},
1359
1360
1361{ "MAL2C_7", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1362
1363/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(53,53), NULL, "MAL2C" },
1364/* error_record[] */ { NULL, 0 },
1365/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
1366},
1367
1368
1369{ "CWQL2C_0", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1370
1371/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(53,53), NULL, "CWQL2C" },
1372/* error_record[] */ { NULL, 0 },
1373/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
1374},
1375
1376
1377{ "CWQL2C_1", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1378
1379/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(53,53), NULL, "CWQL2C" },
1380/* error_record[] */ { NULL, 0 },
1381/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
1382},
1383
1384
1385{ "CWQL2C_2", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1386
1387/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(53,53), NULL, "CWQL2C" },
1388/* error_record[] */ { NULL, 0 },
1389/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
1390},
1391
1392
1393{ "CWQL2C_3", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1394
1395/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(53,53), NULL, "CWQL2C" },
1396/* error_record[] */ { NULL, 0 },
1397/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
1398},
1399
1400
1401{ "CWQL2C_4", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1402
1403/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(53,53), NULL, "CWQL2C" },
1404/* error_record[] */ { NULL, 0 },
1405/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
1406},
1407
1408
1409{ "CWQL2C_5", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1410
1411/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(53,53), NULL, "CWQL2C" },
1412/* error_record[] */ { NULL, 0 },
1413/* error_report[] */ { EAR( l2_b5_eer ), MASK64(0,0) },
1414},
1415
1416
1417{ "CWQL2C_6", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1418
1419/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(53,53), NULL, "CWQL2C" },
1420/* error_record[] */ { NULL, 0 },
1421/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
1422},
1423
1424
1425{ "CWQL2C_7", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1426
1427/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(53,53), NULL, "CWQL2C" },
1428/* error_record[] */ { NULL, 0 },
1429/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
1430},
1431
1432
1433{ "LDRC_DMA_RD_0", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1434
1435/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(49,49), NULL, "L2C_CE_ECC" },
1436/* error_record[] */ { NULL, 0 },
1437/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
1438},
1439
1440
1441{ "LDRC_DMA_RD_1", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1442
1443/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(49,49), NULL, "L2C_CE_ECC" },
1444/* error_record[] */ { NULL, 0 },
1445/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
1446},
1447
1448
1449{ "LDRC_DMA_RD_2", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1450
1451/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(49,49), NULL, "L2C_CE_ECC" },
1452/* error_record[] */ { NULL, 0 },
1453/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
1454},
1455
1456
1457{ "LDRC_DMA_RD_3", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1458
1459/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(49,49), NULL, "L2C_CE_ECC" },
1460/* error_record[] */ { NULL, 0 },
1461/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
1462},
1463
1464
1465{ "LDRC_DMA_RD_4", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1466
1467/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(49,49), NULL, "L2C_CE_ECC" },
1468/* error_record[] */ { NULL, 0 },
1469/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
1470},
1471
1472
1473{ "LDRC_DMA_RD_5", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1474
1475/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(49,49), NULL, "L2C_CE_ECC" },
1476/* error_record[] */ { NULL, 0 },
1477/* error_report[] */ { EAR( l2_b5_eer ), MASK64(0,0) },
1478},
1479
1480
1481{ "LDRC_DMA_RD_6", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1482
1483/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(49,49), NULL, "L2C_CE_ECC" },
1484/* error_record[] */ { NULL, 0 },
1485/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
1486},
1487
1488
1489{ "LDRC_DMA_RD_7", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1490
1491/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(49,49), NULL, "L2C_CE_ECC" },
1492/* error_record[] */ { NULL, 0 },
1493/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
1494},
1495
1496
1497{ "LDRC_DMA_PART_WR_0", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1498
1499/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(49,49), NULL, "L2C" },
1500/* error_record[] */ { NULL, 0 },
1501/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
1502},
1503
1504
1505{ "LDRC_DMA_PART_WR_1", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1506
1507/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(49,49), NULL, "L2C" },
1508/* error_record[] */ { NULL, 0 },
1509/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
1510},
1511
1512
1513{ "LDRC_DMA_PART_WR_2", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1514
1515/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(49,49), NULL, "L2C" },
1516/* error_record[] */ { NULL, 0 },
1517/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
1518},
1519
1520
1521{ "LDRC_DMA_PART_WR_3", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1522
1523/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(49,49), NULL, "L2C" },
1524/* error_record[] */ { NULL, 0 },
1525/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
1526},
1527
1528
1529{ "LDRC_DMA_PART_WR_4", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1530
1531/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(49,49), NULL, "L2C" },
1532/* error_record[] */ { NULL, 0 },
1533/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
1534},
1535
1536
1537{ "LDRC_DMA_PART_WR_5", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1538
1539/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(49,49), NULL, "L2C" },
1540/* error_record[] */ { NULL, 0 },
1541/* error_report[] */ { EAR( l2_b5_eer ), MASK64(0,0) },
1542},
1543
1544
1545{ "LDRC_DMA_PART_WR_6", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1546
1547/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(49,49), NULL, "L2C" },
1548/* error_record[] */ { NULL, 0 },
1549/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
1550},
1551
1552
1553{ "LDRC_DMA_PART_WR_7", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1554
1555/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(49,49), NULL, "L2C" },
1556/* error_record[] */ { NULL, 0 },
1557/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
1558},
1559
1560
1561{ "ITL2U_0", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1562
1563/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(52,52), NULL, "ITL2U" },
1564/* error_record[] */ { NULL, 0 },
1565/* error_report[] */ { EAR( l2_b0_eer ), MASK64(1,1) },
1566},
1567
1568
1569{ "ITL2U_1", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1570
1571/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(52,52), NULL, "ITL2U" },
1572/* error_record[] */ { NULL, 0 },
1573/* error_report[] */ { EAR( l2_b1_eer ), MASK64(1,1) },
1574},
1575
1576
1577{ "ITL2U_2", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1578
1579/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(52,52), NULL, "ITL2U" },
1580/* error_record[] */ { NULL, 0 },
1581/* error_report[] */ { EAR( l2_b2_eer ), MASK64(1,1) },
1582},
1583
1584
1585{ "ITL2U_3", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1586
1587/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(52,52), NULL, "ITL2U" },
1588/* error_record[] */ { NULL, 0 },
1589/* error_report[] */ { EAR( l2_b3_eer ), MASK64(1,1) },
1590},
1591
1592
1593{ "ITL2U_4", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1594
1595/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(52,52), NULL, "ITL2U" },
1596/* error_record[] */ { NULL, 0 },
1597/* error_report[] */ { EAR( l2_b4_eer ), MASK64(1,1) },
1598},
1599
1600
1601{ "ITL2U_5", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1602
1603/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(52,52), NULL, "ITL2U" },
1604/* error_record[] */ { NULL, 0 },
1605/* error_report[] */ { EAR( l2_b5_eer ), MASK64(1,1) },
1606},
1607
1608
1609{ "ITL2U_6", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1610
1611/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(52,52), NULL, "ITL2U" },
1612/* error_record[] */ { NULL, 0 },
1613/* error_report[] */ { EAR( l2_b6_eer ), MASK64(1,1) },
1614},
1615
1616
1617{ "ITL2U_7", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1618
1619/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(52,52), NULL, "ITL2U" },
1620/* error_record[] */ { NULL, 0 },
1621/* error_report[] */ { EAR( l2_b7_eer ), MASK64(1,1) },
1622},
1623
1624
1625{ "DTL2U_0", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1626
1627/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(52,52), NULL, "DTL2U" },
1628/* error_record[] */ { NULL, 0 },
1629/* error_report[] */ { EAR( l2_b0_eer ), MASK64(1,1) },
1630},
1631
1632
1633{ "DTL2U_1", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1634
1635/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(52,52), NULL, "DTL2U" },
1636/* error_record[] */ { NULL, 0 },
1637/* error_report[] */ { EAR( l2_b1_eer ), MASK64(1,1) },
1638},
1639
1640
1641{ "DTL2U_2", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1642
1643/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(52,52), NULL, "DTL2U" },
1644/* error_record[] */ { NULL, 0 },
1645/* error_report[] */ { EAR( l2_b2_eer ), MASK64(1,1) },
1646},
1647
1648
1649{ "DTL2U_3", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1650
1651/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(52,52), NULL, "DTL2U" },
1652/* error_record[] */ { NULL, 0 },
1653/* error_report[] */ { EAR( l2_b3_eer ), MASK64(1,1) },
1654},
1655
1656
1657{ "DTL2U_4", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1658
1659/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(52,52), NULL, "DTL2U" },
1660/* error_record[] */ { NULL, 0 },
1661/* error_report[] */ { EAR( l2_b4_eer ), MASK64(1,1) },
1662},
1663
1664
1665{ "DTL2U_5", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1666
1667/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(52,52), NULL, "DTL2U" },
1668/* error_record[] */ { NULL, 0 },
1669/* error_report[] */ { EAR( l2_b5_eer ), MASK64(1,1) },
1670},
1671
1672
1673{ "DTL2U_6", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1674
1675/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(52,52), NULL, "DTL2U" },
1676/* error_record[] */ { NULL, 0 },
1677/* error_report[] */ { EAR( l2_b6_eer ), MASK64(1,1) },
1678},
1679
1680
1681{ "DTL2U_7", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1682
1683/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(52,52), NULL, "DTL2U" },
1684/* error_record[] */ { NULL, 0 },
1685/* error_report[] */ { EAR( l2_b7_eer ), MASK64(1,1) },
1686},
1687
1688
1689{ "ICL2U_0", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1690
1691/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(52,52), NULL, "ICL2U" },
1692/* error_record[] */ { NULL, 0 },
1693/* error_report[] */ { EAR( l2_b0_eer ), MASK64(1,1) },
1694},
1695
1696
1697{ "ICL2U_1", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1698
1699/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(52,52), NULL, "ICL2U" },
1700/* error_record[] */ { NULL, 0 },
1701/* error_report[] */ { EAR( l2_b1_eer ), MASK64(1,1) },
1702},
1703
1704
1705{ "ICL2U_2", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1706
1707/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(52,52), NULL, "ICL2U" },
1708/* error_record[] */ { NULL, 0 },
1709/* error_report[] */ { EAR( l2_b2_eer ), MASK64(1,1) },
1710},
1711
1712
1713{ "ICL2U_3", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1714
1715/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(52,52), NULL, "ICL2U" },
1716/* error_record[] */ { NULL, 0 },
1717/* error_report[] */ { EAR( l2_b3_eer ), MASK64(1,1) },
1718},
1719
1720
1721{ "ICL2U_4", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1722
1723/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(52,52), NULL, "ICL2U" },
1724/* error_record[] */ { NULL, 0 },
1725/* error_report[] */ { EAR( l2_b4_eer ), MASK64(1,1) },
1726},
1727
1728
1729{ "ICL2U_5", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1730
1731/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(52,52), NULL, "ICL2U" },
1732/* error_record[] */ { NULL, 0 },
1733/* error_report[] */ { EAR( l2_b5_eer ), MASK64(1,1) },
1734},
1735
1736
1737{ "ICL2U_6", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1738
1739/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(52,52), NULL, "ICL2U" },
1740/* error_record[] */ { NULL, 0 },
1741/* error_report[] */ { EAR( l2_b6_eer ), MASK64(1,1) },
1742},
1743
1744
1745{ "ICL2U_7", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
1746
1747/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(52,52), NULL, "ICL2U" },
1748/* error_record[] */ { NULL, 0 },
1749/* error_report[] */ { EAR( l2_b7_eer ), MASK64(1,1) },
1750},
1751
1752
1753
1754{ "DCL2U_0", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1755
1756/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(52,52), NULL, "DCL2U" },
1757/* error_record[] */ { NULL, 0 },
1758/* error_report[] */ { EAR( l2_b0_eer ), MASK64(1,1) },
1759},
1760
1761
1762{ "DCL2U_1", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1763
1764/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(52,52), NULL, "DCL2U" },
1765/* error_record[] */ { NULL, 0 },
1766/* error_report[] */ { EAR( l2_b1_eer ), MASK64(1,1) },
1767},
1768
1769
1770{ "DCL2U_2", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1771
1772/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(52,52), NULL, "DCL2U" },
1773/* error_record[] */ { NULL, 0 },
1774/* error_report[] */ { EAR( l2_b2_eer ), MASK64(1,1) },
1775},
1776
1777
1778{ "DCL2U_3", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1779
1780/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(52,52), NULL, "DCL2U" },
1781/* error_record[] */ { NULL, 0 },
1782/* error_report[] */ { EAR( l2_b3_eer ), MASK64(1,1) },
1783},
1784
1785
1786{ "DCL2U_4", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1787
1788/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(52,52), NULL, "DCL2U" },
1789/* error_record[] */ { NULL, 0 },
1790/* error_report[] */ { EAR( l2_b4_eer ), MASK64(1,1) },
1791},
1792
1793
1794{ "DCL2U_5", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1795
1796/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(52,52), NULL, "DCL2U" },
1797/* error_record[] */ { NULL, 0 },
1798/* error_report[] */ { EAR( l2_b5_eer ), MASK64(1,1) },
1799},
1800
1801
1802{ "DCL2U_6", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1803
1804/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(52,52), NULL, "DCL2U" },
1805/* error_record[] */ { NULL, 0 },
1806/* error_report[] */ { EAR( l2_b6_eer ), MASK64(1,1) },
1807},
1808
1809
1810{ "DCL2U_7", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1811
1812/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(52,52), NULL, "DCL2U" },
1813/* error_record[] */ { NULL, 0 },
1814/* error_report[] */ { EAR( l2_b7_eer ), MASK64(1,1) },
1815},
1816
1817
1818/* Prefetch Hit Errors */
1819{ "L2U_PREFETCH_0", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1820
1821/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(52,52), NULL, "L2U" },
1822/* error_record[] */ { NULL, 0 },
1823/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
1824},
1825
1826
1827{ "L2U_PREFETCH_1", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1828
1829/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(52,52), NULL, "L2U" },
1830/* error_record[] */ { NULL, 0 },
1831/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
1832},
1833
1834
1835{ "L2U_PREFETCH_2", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1836
1837/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(52,52), NULL, "L2U" },
1838/* error_record[] */ { NULL, 0 },
1839/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
1840},
1841
1842
1843{ "L2U_PREFETCH_3", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1844
1845/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(52,52), NULL, "L2U" },
1846/* error_record[] */ { NULL, 0 },
1847/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
1848},
1849
1850
1851{ "L2U_PREFETCH_4", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1852
1853/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(52,52), NULL, "L2U" },
1854/* error_record[] */ { NULL, 0 },
1855/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
1856},
1857
1858
1859{ "L2U_PREFETCH_5", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1860
1861/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(52,52), NULL, "L2U" },
1862/* error_record[] */ { NULL, 0 },
1863/* error_report[] */ { EAR( l2_b5_eer ), MASK64(0,0) },
1864},
1865
1866
1867{ "L2U_PREFETCH_6", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1868
1869/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(52,52), NULL, "L2U" },
1870/* error_record[] */ { NULL, 0 },
1871/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
1872},
1873
1874
1875{ "L2U_PREFETCH_7", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1876
1877/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(52,52), NULL, "L2U" },
1878/* error_record[] */ { NULL, 0 },
1879/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
1880},
1881
1882
1883/* Partial Store Hit/CWQ Partial Store Hit Errors */
1884{ "L2U_ST_0", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1885
1886/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(52,52), NULL, "L2U_PART_ST" },
1887/* error_record[] */ { NULL, 0 },
1888/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
1889},
1890
1891
1892{ "L2U_ST_1", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1893
1894/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(52,52), NULL, "L2U_PART_ST" },
1895/* error_record[] */ { NULL, 0 },
1896/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
1897},
1898
1899
1900{ "L2U_ST_2", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1901
1902/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(52,52), NULL, "L2U_PART_ST" },
1903/* error_record[] */ { NULL, 0 },
1904/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
1905},
1906
1907
1908{ "L2U_ST_3", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1909
1910/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(52,52), NULL, "L2U_PART_ST" },
1911/* error_record[] */ { NULL, 0 },
1912/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
1913},
1914
1915
1916{ "L2U_ST_4", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1917
1918/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(52,52), NULL, "L2U_PART_ST" },
1919/* error_record[] */ { NULL, 0 },
1920/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
1921},
1922
1923
1924{ "L2U_ST_5", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1925
1926/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(52,52), NULL, "L2U_PART_ST" },
1927/* error_record[] */ { NULL, 0 },
1928/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
1929},
1930
1931
1932{ "L2U_ST_6", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1933
1934/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(52,52), NULL, "L2U_PART_ST" },
1935/* error_record[] */ { NULL, 0 },
1936/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
1937},
1938
1939
1940{ "L2U_ST_7", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1941
1942/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(52,52), NULL, "L2U_PART_ST" },
1943/* error_record[] */ { NULL, 0 },
1944/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
1945},
1946
1947
1948{ "CWQL2U_0", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1949
1950/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(52,52), NULL, "CWQL2U" },
1951/* error_record[] */ { NULL, 0 },
1952/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
1953},
1954
1955
1956{ "CWQL2U_1", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1957
1958/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(52,52), NULL, "CWQL2U" },
1959/* error_record[] */ { NULL, 0 },
1960/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
1961},
1962
1963
1964{ "CWQL2U_2", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1965
1966/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(52,52), NULL, "CWQL2U" },
1967/* error_record[] */ { NULL, 0 },
1968/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
1969},
1970
1971
1972{ "CWQL2U_3", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1973
1974/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(52,52), NULL, "CWQL2U" },
1975/* error_record[] */ { NULL, 0 },
1976/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
1977},
1978
1979
1980{ "CWQL2U_4", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1981
1982/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(52,52), NULL, "CWQL2U" },
1983/* error_record[] */ { NULL, 0 },
1984/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
1985},
1986
1987
1988{ "CWQL2U_5", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1989
1990/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(52,52), NULL, "CWQL2U" },
1991/* error_record[] */ { NULL, 0 },
1992/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
1993},
1994
1995
1996{ "CWQL2U_6", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
1997
1998/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(52,52), NULL, "CWQL2U" },
1999/* error_record[] */ { NULL, 0 },
2000/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
2001},
2002
2003
2004{ "CWQL2U_7", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2005
2006/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(52,52), NULL, "CWQL2U" },
2007/* error_record[] */ { NULL, 0 },
2008/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
2009},
2010
2011
2012{ "MAL2U_0", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2013
2014/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(52,52), NULL, "MAL2U" },
2015/* error_record[] */ { NULL, 0 },
2016/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
2017},
2018
2019
2020{ "MAL2U_1", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2021
2022/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(52,52), NULL, "MAL2U" },
2023/* error_record[] */ { NULL, 0 },
2024/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
2025},
2026
2027
2028{ "MAL2U_2", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2029
2030/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(52,52), NULL, "MAL2U" },
2031/* error_record[] */ { NULL, 0 },
2032/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
2033},
2034
2035
2036{ "MAL2U_3", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2037
2038/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(52,52), NULL, "MAL2U" },
2039/* error_record[] */ { NULL, 0 },
2040/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
2041},
2042
2043
2044{ "MAL2U_4", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2045
2046/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(52,52), NULL, "MAL2U" },
2047/* error_record[] */ { NULL, 0 },
2048/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
2049},
2050
2051
2052{ "MAL2U_5", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2053
2054/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(52,52), NULL, "MAL2U" },
2055/* error_record[] */ { NULL, 0 },
2056/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
2057},
2058
2059
2060{ "MAL2U_6", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2061
2062/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(52,52), NULL, "MAL2U" },
2063/* error_record[] */ { NULL, 0 },
2064/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
2065},
2066
2067
2068{ "MAL2U_7", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2069
2070/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(52,52), NULL, "MAL2U" },
2071/* error_record[] */ { NULL, 0 },
2072/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
2073},
2074
2075
2076{ "ITL2ND_0", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2077
2078/* error_status[] */ { EAR( l2nd_b0_esr ), EIR( l2nd_b0_esr ), MASK64(49,49), NULL, "ITL2ND" },
2079/* error_record[] */ { NULL, 0 },
2080/* error_report[] */ { EAR( l2_b0_eer ), MASK64(1,1) },
2081},
2082
2083
2084{ "ITL2ND_1", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2085
2086/* error_status[] */ { EAR( l2nd_b1_esr ), EIR( l2nd_b1_esr ), MASK64(49,49), NULL, "ITL2ND" },
2087/* error_record[] */ { NULL, 0 },
2088/* error_report[] */ { EAR( l2_b1_eer ), MASK64(1,1) },
2089},
2090
2091
2092{ "ITL2ND_2", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2093
2094/* error_status[] */ { EAR( l2nd_b2_esr ), EIR( l2nd_b2_esr ), MASK64(49,49), NULL, "ITL2ND" },
2095/* error_record[] */ { NULL, 0 },
2096/* error_report[] */ { EAR( l2_b2_eer ), MASK64(1,1) },
2097},
2098
2099
2100{ "ITL2ND_3", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2101
2102/* error_status[] */ { EAR( l2nd_b3_esr ), EIR( l2nd_b3_esr ), MASK64(49,49), NULL, "ITL2ND" },
2103/* error_record[] */ { NULL, 0 },
2104/* error_report[] */ { EAR( l2_b3_eer ), MASK64(1,1) },
2105},
2106
2107
2108{ "ITL2ND_4", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2109
2110/* error_status[] */ { EAR( l2nd_b4_esr ), EIR( l2nd_b4_esr ), MASK64(49,49), NULL, "ITL2ND" },
2111/* error_record[] */ { NULL, 0 },
2112/* error_report[] */ { EAR( l2_b4_eer ), MASK64(1,1) },
2113},
2114
2115
2116{ "ITL2ND_5", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2117
2118/* error_status[] */ { EAR( l2nd_b5_esr ), EIR( l2nd_b5_esr ), MASK64(49,49), NULL, "ITL2ND" },
2119/* error_record[] */ { NULL, 0 },
2120/* error_report[] */ { EAR( l2_b5_eer ), MASK64(1,1) },
2121},
2122
2123
2124{ "ITL2ND_6", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2125
2126/* error_status[] */ { EAR( l2nd_b6_esr ), EIR( l2nd_b6_esr ), MASK64(49,49), NULL, "ITL2ND" },
2127/* error_record[] */ { NULL, 0 },
2128/* error_report[] */ { EAR( l2_b6_eer ), MASK64(1,1) },
2129},
2130
2131
2132{ "ITL2ND_7", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2133
2134/* error_status[] */ { EAR( l2nd_b7_esr ), EIR( l2nd_b7_esr ), MASK64(49,49), NULL, "ITL2ND" },
2135/* error_record[] */ { NULL, 0 },
2136/* error_report[] */ { EAR( l2_b7_eer ), MASK64(1,1) },
2137},
2138
2139
2140{ "DTL2ND_0", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2141
2142/* error_status[] */ { EAR( l2nd_b0_esr ), EIR( l2nd_b0_esr ), MASK64(49,49), NULL, "DTL2ND" },
2143/* error_record[] */ { NULL, 0 },
2144/* error_report[] */ { EAR( l2_b0_eer ), MASK64(1,1) },
2145},
2146
2147
2148{ "DTL2ND_1", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2149
2150/* error_status[] */ { EAR( l2nd_b1_esr ), EIR( l2nd_b1_esr ), MASK64(49,49), NULL, "DTL2ND" },
2151/* error_record[] */ { NULL, 0 },
2152/* error_report[] */ { EAR( l2_b1_eer ), MASK64(1,1) },
2153},
2154
2155
2156{ "DTL2ND_2", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2157
2158/* error_status[] */ { EAR( l2nd_b2_esr ), EIR( l2nd_b2_esr ), MASK64(49,49), NULL, "DTL2ND" },
2159/* error_record[] */ { NULL, 0 },
2160/* error_report[] */ { EAR( l2_b2_eer ), MASK64(1,1) },
2161},
2162
2163
2164{ "DTL2ND_3", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2165
2166/* error_status[] */ { EAR( l2nd_b3_esr ), EIR( l2nd_b3_esr ), MASK64(49,49), NULL, "DTL2ND" },
2167/* error_record[] */ { NULL, 0 },
2168/* error_report[] */ { EAR( l2_b3_eer ), MASK64(1,1) },
2169},
2170
2171
2172{ "DTL2ND_4", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2173
2174/* error_status[] */ { EAR( l2nd_b4_esr ), EIR( l2nd_b4_esr ), MASK64(49,49), NULL, "DTL2ND" },
2175/* error_record[] */ { NULL, 0 },
2176/* error_report[] */ { EAR( l2_b4_eer ), MASK64(1,1) },
2177},
2178
2179
2180{ "DTL2ND_5", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2181
2182/* error_status[] */ { EAR( l2nd_b5_esr ), EIR( l2nd_b5_esr ), MASK64(49,49), NULL, "DTL2ND" },
2183/* error_record[] */ { NULL, 0 },
2184/* error_report[] */ { EAR( l2_b5_eer ), MASK64(1,1) },
2185},
2186
2187
2188{ "DTL2ND_6", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2189
2190/* error_status[] */ { EAR( l2nd_b6_esr ), EIR( l2nd_b6_esr ), MASK64(49,49), NULL, "DTL2ND" },
2191/* error_record[] */ { NULL, 0 },
2192/* error_report[] */ { EAR( l2_b6_eer ), MASK64(1,1) },
2193},
2194
2195
2196{ "DTL2ND_0", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2197
2198/* error_status[] */ { EAR( l2nd_b0_esr ), EIR( l2nd_b0_esr ), MASK64(49,49), NULL, "DTL2ND" },
2199/* error_record[] */ { NULL, 0 },
2200/* error_report[] */ { EAR( l2_b0_eer ), MASK64(1,1) },
2201},
2202
2203
2204{ "ICL2ND_0", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2205
2206/* error_status[] */ { EAR( l2nd_b0_esr ), EIR( l2nd_b0_esr ), MASK64(52,52), NULL, "ICL2ND" },
2207/* error_record[] */ { NULL, 0 },
2208/* error_report[] */ { EAR( l2_b0_eer ), MASK64(1,1) },
2209},
2210
2211
2212{ "ICL2ND_1", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2213
2214/* error_status[] */ { EAR( l2nd_b1_esr ), EIR( l2nd_b1_esr ), MASK64(52,52), NULL, "ICL2ND" },
2215/* error_record[] */ { NULL, 0 },
2216/* error_report[] */ { EAR( l2_b1_eer ), MASK64(1,1) },
2217},
2218
2219
2220{ "ICL2ND_2", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2221
2222/* error_status[] */ { EAR( l2nd_b2_esr ), EIR( l2nd_b2_esr ), MASK64(52,52), NULL, "ICL2ND" },
2223/* error_record[] */ { NULL, 0 },
2224/* error_report[] */ { EAR( l2_b2_eer ), MASK64(1,1) },
2225},
2226
2227
2228{ "ICL2ND_3", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2229
2230/* error_status[] */ { EAR( l2nd_b3_esr ), EIR( l2nd_b3_esr ), MASK64(52,52), NULL, "ICL2ND" },
2231/* error_record[] */ { NULL, 0 },
2232/* error_report[] */ { EAR( l2_b3_eer ), MASK64(1,1) },
2233},
2234
2235
2236{ "ICL2ND_4", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2237
2238/* error_status[] */ { EAR( l2nd_b4_esr ), EIR( l2nd_b4_esr ), MASK64(52,52), NULL, "ICL2ND" },
2239/* error_record[] */ { NULL, 0 },
2240/* error_report[] */ { EAR( l2_b4_eer ), MASK64(1,1) },
2241},
2242
2243
2244{ "ICL2ND_5", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2245
2246/* error_status[] */ { EAR( l2nd_b5_esr ), EIR( l2nd_b5_esr ), MASK64(52,52), NULL, "ICL2ND" },
2247/* error_record[] */ { NULL, 0 },
2248/* error_report[] */ { EAR( l2_b5_eer ), MASK64(1,1) },
2249},
2250
2251
2252{ "ICL2ND_6", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2253
2254/* error_status[] */ { EAR( l2nd_b6_esr ), EIR( l2nd_b6_esr ), MASK64(52,52), NULL, "ICL2ND" },
2255/* error_record[] */ { NULL, 0 },
2256/* error_report[] */ { EAR( l2_b6_eer ), MASK64(1,1) },
2257},
2258
2259
2260{ "ICL2ND_7", SS_UE_trap_forward_2_core, PRECISE_TT, false, TARGET_MYSELF,
2261
2262/* error_status[] */ { EAR( l2nd_b7_esr ), EIR( l2nd_b7_esr ), MASK64(52,52), NULL, "ICL2ND" },
2263/* error_record[] */ { NULL, 0 },
2264/* error_report[] */ { EAR( l2_b7_eer ), MASK64(1,1) },
2265},
2266
2267
2268{ "DCL2ND_0", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2269
2270/* error_status[] */ { EAR( l2nd_b0_esr ), EIR( l2nd_b0_esr ), MASK64(49,49), NULL, "DCL2ND" },
2271/* error_record[] */ { NULL, 0 },
2272/* error_report[] */ { EAR( l2_b0_eer ), MASK64(1,1) },
2273},
2274
2275
2276{ "DCL2ND_1", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2277
2278/* error_status[] */ { EAR( l2nd_b1_esr ), EIR( l2nd_b1_esr ), MASK64(49,49), NULL, "DCL2ND" },
2279/* error_record[] */ { NULL, 0 },
2280/* error_report[] */ { EAR( l2_b1_eer ), MASK64(1,1) },
2281},
2282
2283
2284{ "DCL2ND_2", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2285
2286/* error_status[] */ { EAR( l2nd_b2_esr ), EIR( l2nd_b2_esr ), MASK64(49,49), NULL, "DCL2ND" },
2287/* error_record[] */ { NULL, 0 },
2288/* error_report[] */ { EAR( l2_b2_eer ), MASK64(1,1) },
2289},
2290
2291
2292{ "DCL2ND_3", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2293
2294/* error_status[] */ { EAR( l2nd_b3_esr ), EIR( l2nd_b3_esr ), MASK64(49,49), NULL, "DCL2ND" },
2295/* error_record[] */ { NULL, 0 },
2296/* error_report[] */ { EAR( l2_b3_eer ), MASK64(1,1) },
2297},
2298
2299
2300{ "DCL2ND_4", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2301
2302/* error_status[] */ { EAR( l2nd_b4_esr ), EIR( l2nd_b4_esr ), MASK64(49,49), NULL, "DCL2ND" },
2303/* error_record[] */ { NULL, 0 },
2304/* error_report[] */ { EAR( l2_b4_eer ), MASK64(1,1) },
2305},
2306
2307
2308{ "DCL2ND_5", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2309
2310/* error_status[] */ { EAR( l2nd_b5_esr ), EIR( l2nd_b5_esr ), MASK64(49,49), NULL, "DCL2ND" },
2311/* error_record[] */ { NULL, 0 },
2312/* error_report[] */ { EAR( l2_b5_eer ), MASK64(1,1) },
2313},
2314
2315
2316{ "DCL2ND_6", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2317
2318/* error_status[] */ { EAR( l2nd_b6_esr ), EIR( l2nd_b6_esr ), MASK64(49,49), NULL, "DCL2ND" },
2319/* error_record[] */ { NULL, 0 },
2320/* error_report[] */ { EAR( l2_b6_eer ), MASK64(1,1) },
2321},
2322
2323
2324{ "DCL2ND_7", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2325
2326/* error_status[] */ { EAR( l2nd_b7_esr ), EIR( l2nd_b7_esr ), MASK64(49,49), NULL, "DCL2ND" },
2327/* error_record[] */ { NULL, 0 },
2328/* error_report[] */ { EAR( l2_b7_eer ), MASK64(1,1) },
2329},
2330
2331
2332{ "L2ND_PREFETCH_0", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2333
2334/* error_status[] */ { EAR( l2nd_b0_esr ), EIR( l2nd_b0_esr ), MASK64(49,49), NULL, "L2ND" },
2335/* error_record[] */ { NULL, 0 },
2336/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
2337},
2338
2339
2340{ "L2ND_PREFETCH_1", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2341
2342/* error_status[] */ { EAR( l2nd_b1_esr ), EIR( l2nd_b1_esr ), MASK64(49,49), NULL, "L2ND" },
2343/* error_record[] */ { NULL, 0 },
2344/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
2345},
2346
2347
2348{ "L2ND_PREFETCH_2", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2349
2350/* error_status[] */ { EAR( l2nd_b2_esr ), EIR( l2nd_b2_esr ), MASK64(49,49), NULL, "L2ND" },
2351/* error_record[] */ { NULL, 0 },
2352/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
2353},
2354
2355
2356{ "L2ND_PREFETCH_3", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2357
2358/* error_status[] */ { EAR( l2nd_b3_esr ), EIR( l2nd_b3_esr ), MASK64(49,49), NULL, "L2ND" },
2359/* error_record[] */ { NULL, 0 },
2360/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
2361},
2362
2363
2364{ "L2ND_PREFETCH_4", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2365
2366/* error_status[] */ { EAR( l2nd_b4_esr ), EIR( l2nd_b4_esr ), MASK64(49,49), NULL, "L2ND" },
2367/* error_record[] */ { NULL, 0 },
2368/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
2369},
2370
2371
2372{ "L2ND_PREFETCH_5", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2373
2374/* error_status[] */ { EAR( l2nd_b5_esr ), EIR( l2nd_b5_esr ), MASK64(49,49), NULL, "L2ND" },
2375/* error_record[] */ { NULL, 0 },
2376/* error_report[] */ { EAR( l2_b5_eer ), MASK64(0,0) },
2377},
2378
2379
2380{ "L2ND_PREFETCH_6", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2381
2382/* error_status[] */ { EAR( l2nd_b6_esr ), EIR( l2nd_b6_esr ), MASK64(49,49), NULL, "L2ND" },
2383/* error_record[] */ { NULL, 0 },
2384/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
2385},
2386
2387
2388{ "L2ND_PREFETCH_7", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2389
2390/* error_status[] */ { EAR( l2nd_b7_esr ), EIR( l2nd_b7_esr ), MASK64(49,49), NULL, "L2ND" },
2391/* error_record[] */ { NULL, 0 },
2392/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
2393},
2394
2395
2396{ "CWQL2ND_0", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2397
2398/* error_status[] */ { EAR( l2nd_b0_esr ), EIR( l2nd_b0_esr ), MASK64(49,49), NULL, "CWQL2ND" },
2399/* error_record[] */ { NULL, 0 },
2400/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
2401},
2402
2403
2404{ "CWQL2ND_1", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2405
2406/* error_status[] */ { EAR( l2nd_b1_esr ), EIR( l2nd_b1_esr ), MASK64(49,49), NULL, "CWQL2ND" },
2407/* error_record[] */ { NULL, 0 },
2408/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
2409},
2410
2411
2412{ "CWQL2ND_2", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2413
2414/* error_status[] */ { EAR( l2nd_b2_esr ), EIR( l2nd_b2_esr ), MASK64(49,49), NULL, "CWQL2ND" },
2415/* error_record[] */ { NULL, 0 },
2416/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
2417},
2418
2419
2420{ "CWQL2ND_3", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2421
2422/* error_status[] */ { EAR( l2nd_b3_esr ), EIR( l2nd_b3_esr ), MASK64(49,49), NULL, "CWQL2ND" },
2423/* error_record[] */ { NULL, 0 },
2424/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
2425},
2426
2427
2428{ "CWQL2ND_4", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2429
2430/* error_status[] */ { EAR( l2nd_b4_esr ), EIR( l2nd_b4_esr ), MASK64(49,49), NULL, "CWQL2ND" },
2431/* error_record[] */ { NULL, 0 },
2432/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
2433},
2434
2435
2436{ "CWQL2ND_5", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2437
2438/* error_status[] */ { EAR( l2nd_b5_esr ), EIR( l2nd_b5_esr ), MASK64(49,49), NULL, "CWQL2ND" },
2439/* error_record[] */ { NULL, 0 },
2440/* error_report[] */ { EAR( l2_b5_eer ), MASK64(0,0) },
2441},
2442
2443
2444{ "CWQL2ND_6", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2445
2446/* error_status[] */ { EAR( l2nd_b6_esr ), EIR( l2nd_b6_esr ), MASK64(49,49), NULL, "CWQL2ND" },
2447/* error_record[] */ { NULL, 0 },
2448/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
2449},
2450
2451
2452{ "CWQL2ND_7", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2453
2454/* error_status[] */ { EAR( l2nd_b7_esr ), EIR( l2nd_b7_esr ), MASK64(49,49), NULL, "CWQL2ND" },
2455/* error_record[] */ { NULL, 0 },
2456/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
2457},
2458
2459
2460{ "MAL2ND_0", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2461
2462/* error_status[] */ { EAR( l2nd_b0_esr ), EIR( l2nd_b0_esr ), MASK64(49,49), NULL, "MAL2ND" },
2463/* error_record[] */ { NULL, 0 },
2464/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
2465},
2466
2467
2468{ "MAL2ND_1", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2469
2470/* error_status[] */ { EAR( l2nd_b1_esr ), EIR( l2nd_b1_esr ), MASK64(49,49), NULL, "MAL2ND" },
2471/* error_record[] */ { NULL, 0 },
2472/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
2473},
2474
2475
2476{ "MAL2ND_2", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2477
2478/* error_status[] */ { EAR( l2nd_b2_esr ), EIR( l2nd_b2_esr ), MASK64(49,49), NULL, "MAL2ND" },
2479/* error_record[] */ { NULL, 0 },
2480/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
2481},
2482
2483
2484{ "MAL2ND_3", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2485
2486/* error_status[] */ { EAR( l2nd_b3_esr ), EIR( l2nd_b3_esr ), MASK64(49,49), NULL, "MAL2ND" },
2487/* error_record[] */ { NULL, 0 },
2488/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
2489},
2490
2491
2492{ "MAL2ND_4", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2493
2494/* error_status[] */ { EAR( l2nd_b4_esr ), EIR( l2nd_b4_esr ), MASK64(49,49), NULL, "MAL2ND" },
2495/* error_record[] */ { NULL, 0 },
2496/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
2497},
2498
2499
2500{ "MAL2ND_5", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2501
2502/* error_status[] */ { EAR( l2nd_b5_esr ), EIR( l2nd_b5_esr ), MASK64(49,49), NULL, "MAL2ND" },
2503/* error_record[] */ { NULL, 0 },
2504/* error_report[] */ { EAR( l2_b5_eer ), MASK64(0,0) },
2505},
2506
2507
2508{ "MAL2ND_6", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2509
2510/* error_status[] */ { EAR( l2nd_b6_esr ), EIR( l2nd_b6_esr ), MASK64(49,49), NULL, "MAL2ND" },
2511/* error_record[] */ { NULL, 0 },
2512/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
2513},
2514
2515
2516{ "MAL2ND_7", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2517
2518/* error_status[] */ { EAR( l2nd_b7_esr ), EIR( l2nd_b7_esr ), MASK64(49,49), NULL, "MAL2ND" },
2519/* error_record[] */ { NULL, 0 },
2520/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
2521},
2522
2523
2524{ "LDWU_0", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2525
2526/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(50,50), NULL, "L2U" },
2527/* error_record[] */ { NULL, 0 },
2528/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
2529},
2530
2531
2532{ "LDWU_1", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2533
2534/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(50,50), NULL, "L2U" },
2535/* error_record[] */ { NULL, 0 },
2536/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
2537},
2538
2539
2540{ "LDWU_2", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2541
2542/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(50,50), NULL, "L2U" },
2543/* error_record[] */ { NULL, 0 },
2544/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
2545},
2546
2547
2548{ "LDWU_3", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2549
2550/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(50,50), NULL, "L2U" },
2551/* error_record[] */ { NULL, 0 },
2552/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
2553},
2554
2555
2556{ "LDWU_4", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2557
2558/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(50,50), NULL, "L2U" },
2559/* error_record[] */ { NULL, 0 },
2560/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
2561},
2562
2563
2564{ "LDWU_5", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2565
2566/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(50,50), NULL, "L2U" },
2567/* error_record[] */ { NULL, 0 },
2568/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
2569},
2570
2571
2572{ "LDWU_6", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2573
2574/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(50,50), NULL, "L2U" },
2575/* error_record[] */ { NULL, 0 },
2576/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
2577},
2578
2579
2580{ "LDWU_7", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2581
2582/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(50,50), NULL, "L2U" },
2583/* error_record[] */ { NULL, 0 },
2584/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
2585},
2586
2587
2588{ "LDRU_0", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2589
2590/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(48,48), NULL, "L2U" },
2591/* error_record[] */ { NULL, 0 },
2592/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
2593},
2594
2595
2596{ "LDRU_1", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2597
2598/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(48,48), NULL, "L2U" },
2599/* error_record[] */ { NULL, 0 },
2600/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
2601},
2602
2603
2604{ "LDRU_2", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2605
2606/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(48,48), NULL, "L2U" },
2607/* error_record[] */ { NULL, 0 },
2608/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
2609},
2610
2611
2612{ "LDRU_3", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2613
2614/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(48,48), NULL, "L2U" },
2615/* error_record[] */ { NULL, 0 },
2616/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
2617},
2618
2619
2620{ "LDRU_4", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2621
2622/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(48,48), NULL, "L2U" },
2623/* error_record[] */ { NULL, 0 },
2624/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
2625},
2626
2627
2628{ "LDRU_5", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2629
2630/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(48,48), NULL, "L2U" },
2631/* error_record[] */ { NULL, 0 },
2632/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
2633},
2634
2635
2636{ "LDRU_6", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2637
2638/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(48,48), NULL, "L2U" },
2639/* error_record[] */ { NULL, 0 },
2640/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
2641},
2642
2643
2644{ "LDRU_7", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2645
2646/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(48,48), NULL, "L2U" },
2647/* error_record[] */ { NULL, 0 },
2648/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
2649},
2650
2651
2652{ "LDSU_0", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2653
2654/* error_status[] */ { EAR( l2_b0_esr ), EIR( l2_b0_esr ), MASK64(46,46), NULL, "L2U" },
2655/* error_record[] */ { NULL, 0 },
2656/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
2657},
2658
2659
2660{ "LDSU_1", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2661
2662/* error_status[] */ { EAR( l2_b1_esr ), EIR( l2_b1_esr ), MASK64(46,46), NULL, "L2U" },
2663/* error_record[] */ { NULL, 0 },
2664/* error_report[] */ { EAR( l2_b1_eer ), MASK64(0,0) },
2665},
2666
2667
2668{ "LDSU_2", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2669
2670/* error_status[] */ { EAR( l2_b2_esr ), EIR( l2_b2_esr ), MASK64(46,46), NULL, "L2U" },
2671/* error_record[] */ { NULL, 0 },
2672/* error_report[] */ { EAR( l2_b2_eer ), MASK64(0,0) },
2673},
2674
2675
2676{ "LDSU_3", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2677
2678/* error_status[] */ { EAR( l2_b3_esr ), EIR( l2_b3_esr ), MASK64(46,46), NULL, "L2U" },
2679/* error_record[] */ { NULL, 0 },
2680/* error_report[] */ { EAR( l2_b3_eer ), MASK64(0,0) },
2681},
2682
2683
2684{ "LDSU_4", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2685
2686/* error_status[] */ { EAR( l2_b4_esr ), EIR( l2_b4_esr ), MASK64(46,46), NULL, "L2U" },
2687/* error_record[] */ { NULL, 0 },
2688/* error_report[] */ { EAR( l2_b4_eer ), MASK64(0,0) },
2689},
2690
2691
2692{ "LDSU_5", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2693
2694/* error_status[] */ { EAR( l2_b5_esr ), EIR( l2_b5_esr ), MASK64(46,46), NULL, "L2U" },
2695/* error_record[] */ { NULL, 0 },
2696/* error_report[] */ { EAR( l2_b0_eer ), MASK64(0,0) },
2697},
2698
2699
2700{ "LDSU_6", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2701
2702/* error_status[] */ { EAR( l2_b6_esr ), EIR( l2_b6_esr ), MASK64(46,46), NULL, "L2U" },
2703/* error_record[] */ { NULL, 0 },
2704/* error_report[] */ { EAR( l2_b6_eer ), MASK64(0,0) },
2705},
2706
2707
2708{ "LDSU_7", SS_UE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2709
2710/* error_status[] */ { EAR( l2_b7_esr ), EIR( l2_b7_esr ), MASK64(46,46), NULL, "L2U" },
2711/* error_record[] */ { NULL, 0 },
2712/* error_report[] */ { EAR( l2_b7_eer ), MASK64(0,0) },
2713},
2714
2715
2716/* DRAM Errors */
2717{ "DAC_LD_FTCH_TTE_MISS_0_L2_0", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2718
2719/* error_status[] */ { EAR( dram_b0_esr ), EIR( dram_b0_esr), DRAM_DAC_bit, NULL, "L2C" },
2720/* error_record[] */ { NULL, 0 },
2721/* error_report[] */ { NULL, 0 },
2722},
2723
2724
2725{ "DAC_LD_FTCH_TTE_MISS_0_L2_1", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2726
2727/* error_status[] */ { EAR( dram_b0_esr ), EIR( dram_b0_esr), DRAM_DAC_bit, NULL, "L2C" },
2728/* error_record[] */ { NULL, 0 },
2729/* error_report[] */ { NULL, 0 },
2730},
2731
2732
2733{ "DAC_LD_FTCH_TTE_MISS_1_L2_2", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2734
2735/* error_status[] */ { EAR( dram_b0_esr ), EIR( dram_b0_esr), DRAM_DAC_bit, NULL, "L2C" },
2736/* error_record[] */ { NULL, 0 },
2737/* error_report[] */ { NULL, 0 },
2738},
2739
2740
2741{ "DAC_LD_FTCH_TTE_MISS_1_L2_3", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2742
2743/* error_status[] */ { EAR( dram_b0_esr ), EIR( dram_b0_esr), DRAM_DAC_bit, NULL, "L2C" },
2744/* error_record[] */ { NULL, 0 },
2745/* error_report[] */ { NULL, 0 },
2746},
2747
2748
2749{ "DAC_LD_FTCH_TTE_MISS_2_L2_4", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2750
2751/* error_status[] */ { EAR( dram_b2_esr ), EIR( dram_b2_esr), DRAM_DAC_bit, NULL, "L2C" },
2752/* error_record[] */ { NULL, 0 },
2753/* error_report[] */ { NULL, 0 },
2754},
2755
2756
2757{ "DAC_LD_FTCH_TTE_MISS_2_L2_5", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2758
2759/* error_status[] */ { EAR( dram_b2_esr ), EIR( dram_b2_esr), DRAM_DAC_bit, NULL, "L2C" },
2760/* error_record[] */ { NULL, 0 },
2761/* error_report[] */ { NULL, 0 },
2762},
2763
2764
2765{ "DAC_LD_FTCH_TTE_MISS_3_L2_6", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2766
2767/* error_status[] */ { EAR( dram_b3_esr ), EIR( dram_b3_esr), DRAM_DAC_bit, NULL, "L2C" },
2768/* error_record[] */ { NULL, 0 },
2769/* error_report[] */ { NULL, 0 },
2770},
2771
2772
2773{ "DAC_LD_FTCH_TTE_MISS_3_L2_7", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2774
2775/* error_status[] */ { EAR( dram_b3_esr ), EIR( dram_b3_esr), DRAM_DAC_bit, NULL, "L2C" },
2776/* error_record[] */ { NULL, 0 },
2777/* error_report[] */ { NULL, 0 },
2778},
2779
2780
2781{ "DAC_ATOMIC_MISS_0_L2_0", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2782
2783/* error_status[] */ { EAR( dram_b0_esr ), EIR( dram_b0_esr), DRAM_DAC_bit, NULL, "L2C" },
2784/* error_record[] */ { NULL, 0 },
2785/* error_report[] */ { NULL, 0 },
2786},
2787
2788
2789{ "DAC_ATOMIC_MISS_0_L2_1", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2790
2791/* error_status[] */ { EAR( dram_b0_esr ), EIR( dram_b0_esr), DRAM_DAC_bit, NULL, "L2C" },
2792/* error_record[] */ { NULL, 0 },
2793/* error_report[] */ { NULL, 0 },
2794},
2795
2796
2797{ "DAC_ATOMIC_MISS_1_L2_2", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2798
2799/* error_status[] */ { EAR( dram_b1_esr ), EIR( dram_b1_esr), DRAM_DAC_bit, NULL, "L2C" },
2800/* error_record[] */ { NULL, 0 },
2801/* error_report[] */ { NULL, 0 },
2802},
2803
2804
2805{ "DAC_ATOMIC_MISS_1_L2_3", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2806
2807/* error_status[] */ { EAR( dram_b1_esr ), EIR( dram_b1_esr), DRAM_DAC_bit, NULL, "L2C" },
2808/* error_record[] */ { NULL, 0 },
2809/* error_report[] */ { NULL, 0 },
2810},
2811
2812
2813{ "DAC_ATOMIC_MISS_2_L2_4", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2814
2815/* error_status[] */ { EAR( dram_b2_esr ), EIR( dram_b2_esr), DRAM_DAC_bit, NULL, "L2C" },
2816/* error_record[] */ { NULL, 0 },
2817/* error_report[] */ { NULL, 0 },
2818},
2819
2820
2821{ "DAC_ATOMIC_MISS_2_L2_5", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2822
2823/* error_status[] */ { EAR( dram_b2_esr ), EIR( dram_b2_esr), DRAM_DAC_bit, NULL, "L2C" },
2824/* error_record[] */ { NULL, 0 },
2825/* error_report[] */ { NULL, 0 },
2826},
2827
2828
2829{ "DAC_ATOMIC_MISS_3_L2_6", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2830
2831/* error_status[] */ { EAR( dram_b3_esr ), EIR( dram_b3_esr), DRAM_DAC_bit, NULL, "L2C" },
2832/* error_record[] */ { NULL, 0 },
2833/* error_report[] */ { NULL, 0 },
2834},
2835
2836
2837{ "DAC_ATOMIC_MISS_3_L2_7", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2838
2839/* error_status[] */ { EAR( dram_b3_esr ), EIR( dram_b3_esr), DRAM_DAC_bit, NULL, "L2C" },
2840/* error_record[] */ { NULL, 0 },
2841/* error_report[] */ { NULL, 0 },
2842},
2843
2844
2845/* Partial Store Miss / CWQ Partial Store Miss */
2846{ "DAC_PART_STX_MISS_0_L2_0", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2847
2848/* error_status[] */ { EAR( dram_b0_esr ), EIR( dram_b0_esr), DRAM_DAC_bit, NULL, "L2C" },
2849/* error_record[] */ { NULL, 0 },
2850/* error_report[] */ { NULL, 0 },
2851},
2852
2853
2854{ "DAC_PART_STX_MISS_0_L2_1", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2855
2856/* error_status[] */ { EAR( dram_b0_esr ), EIR( dram_b0_esr), DRAM_DAC_bit, NULL, "L2C" },
2857/* error_record[] */ { NULL, 0 },
2858/* error_report[] */ { NULL, 0 },
2859},
2860
2861
2862{ "DAC_PART_STX_MISS_1_L2_2", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2863
2864/* error_status[] */ { EAR( dram_b1_esr ), EIR( dram_b1_esr), DRAM_DAC_bit, NULL, "L2C" },
2865/* error_record[] */ { NULL, 0 },
2866/* error_report[] */ { NULL, 0 },
2867},
2868
2869
2870{ "DAC_PART_STX_MISS_1_L2_3", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2871
2872/* error_status[] */ { EAR( dram_b1_esr ), EIR( dram_b1_esr), DRAM_DAC_bit, NULL, "L2C" },
2873/* error_record[] */ { NULL, 0 },
2874/* error_report[] */ { NULL, 0 },
2875},
2876
2877
2878{ "DAC_PART_STX_MISS_2_L2_4", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2879
2880/* error_status[] */ { EAR( dram_b2_esr ), EIR( dram_b2_esr), DRAM_DAC_bit, NULL, "L2C" },
2881/* error_record[] */ { NULL, 0 },
2882/* error_report[] */ { NULL, 0 },
2883},
2884
2885
2886{ "DAC_PART_STX_MISS_2_L2_5", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2887
2888/* error_status[] */ { EAR( dram_b2_esr ), EIR( dram_b2_esr), DRAM_DAC_bit, NULL, "L2C" },
2889/* error_record[] */ { NULL, 0 },
2890/* error_report[] */ { NULL, 0 },
2891},
2892
2893
2894{ "DAC_PART_STX_MISS_3_L2_6", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2895
2896/* error_status[] */ { EAR( dram_b3_esr ), EIR( dram_b3_esr), DRAM_DAC_bit, NULL, "L2C" },
2897/* error_record[] */ { NULL, 0 },
2898/* error_report[] */ { NULL, 0 },
2899},
2900
2901
2902{ "DAC_PART_STX_MISS_3_L2_7", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2903
2904/* error_status[] */ { EAR( dram_b3_esr ), EIR( dram_b3_esr), DRAM_DAC_bit, NULL, "L2C" },
2905/* error_record[] */ { NULL, 0 },
2906/* error_report[] */ { NULL, 0 },
2907},
2908
2909
2910/* Store Miss / Modular Arithmetic Store Miss/ CWQ Store Miss */
2911{ "DAC_STX_MISS_0_L2_0", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2912
2913/* error_status[] */ { EAR( dram_b0_esr ), EIR( dram_b0_esr), DRAM_DAC_bit, NULL, "L2C" },
2914/* error_record[] */ { NULL, 0 },
2915/* error_report[] */ { NULL, 0 },
2916},
2917
2918
2919{ "DAC_STX_MISS_0_L2_1", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2920
2921/* error_status[] */ { EAR( dram_b0_esr ), EIR( dram_b0_esr), DRAM_DAC_bit, NULL, "L2C" },
2922/* error_record[] */ { NULL, 0 },
2923/* error_report[] */ { NULL, 0 },
2924},
2925
2926
2927{ "DAC_STX_MISS_1_L2_2", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2928
2929/* error_status[] */ { EAR( dram_b1_esr ), EIR( dram_b1_esr), DRAM_DAC_bit, NULL, "L2C" },
2930/* error_record[] */ { NULL, 0 },
2931/* error_report[] */ { NULL, 0 },
2932},
2933
2934
2935{ "DAC_STX_MISS_1_L2_3", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2936
2937/* error_status[] */ { EAR( dram_b1_esr ), EIR( dram_b1_esr), DRAM_DAC_bit, NULL, "L2C" },
2938/* error_record[] */ { NULL, 0 },
2939/* error_report[] */ { NULL, 0 },
2940},
2941
2942
2943{ "DAC_STX_MISS_2_L2_4", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2944
2945/* error_status[] */ { EAR( dram_b2_esr ), EIR( dram_b2_esr), DRAM_DAC_bit, NULL, "L2C" },
2946/* error_record[] */ { NULL, 0 },
2947/* error_report[] */ { NULL, 0 },
2948},
2949
2950
2951{ "DAC_STX_MISS_2_L2_5", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2952
2953/* error_status[] */ { EAR( dram_b2_esr ), EIR( dram_b2_esr), DRAM_DAC_bit, NULL, "L2C" },
2954/* error_record[] */ { NULL, 0 },
2955/* error_report[] */ { NULL, 0 },
2956},
2957
2958
2959{ "DAC_STX_MISS_3_L2_6", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2960
2961/* error_status[] */ { EAR( dram_b3_esr ), EIR( dram_b3_esr), DRAM_DAC_bit, NULL, "L2C" },
2962/* error_record[] */ { NULL, 0 },
2963/* error_report[] */ { NULL, 0 },
2964},
2965
2966
2967{ "DAC_STX_MISS_3_L2_7", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2968
2969/* error_status[] */ { EAR( dram_b3_esr ), EIR( dram_b3_esr), DRAM_DAC_bit, NULL, "L2C" },
2970/* error_record[] */ { NULL, 0 },
2971/* error_report[] */ { NULL, 0 },
2972},
2973
2974
2975{ "DSC_0_L2_0", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2976
2977/* error_status[] */ { EAR( dram_b0_esr ), EIR( dram_b0_esr), DRAM_DSC_bit, NULL, "L2C" },
2978/* error_record[] */ { NULL, 0 },
2979/* error_report[] */ { NULL, 0 },
2980},
2981
2982
2983{ "DSC_0_L2_1", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2984
2985/* error_status[] */ { EAR( dram_b0_esr ), EIR( dram_b0_esr), DRAM_DSC_bit, NULL, "L2C" },
2986/* error_record[] */ { NULL, 0 },
2987/* error_report[] */ { NULL, 0 },
2988},
2989
2990
2991{ "DSC_1_L2_2", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
2992
2993/* error_status[] */ { EAR( dram_b1_esr ), EIR( dram_b1_esr), DRAM_DSC_bit, NULL, "L2C" },
2994/* error_record[] */ { NULL, 0 },
2995/* error_report[] */ { NULL, 0 },
2996},
2997
2998
2999{ "DSC_1_L2_3", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
3000
3001/* error_status[] */ { EAR( dram_b1_esr ), EIR( dram_b1_esr), DRAM_DSC_bit, NULL, "L2C" },
3002/* error_record[] */ { NULL, 0 },
3003/* error_report[] */ { NULL, 0 },
3004},
3005
3006
3007{ "DSC_2_L2_4", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
3008
3009/* error_status[] */ { EAR( dram_b2_esr ), EIR( dram_b2_esr), DRAM_DSC_bit, NULL, "L2C" },
3010/* error_record[] */ { NULL, 0 },
3011/* error_report[] */ { NULL, 0 },
3012},
3013
3014
3015{ "DSC_2_L2_5", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
3016
3017/* error_status[] */ { EAR( dram_b2_esr ), EIR( dram_b2_esr), DRAM_DSC_bit, NULL, "L2C" },
3018/* error_record[] */ { NULL, 0 },
3019/* error_report[] */ { NULL, 0 },
3020},
3021
3022
3023{ "DSC_3_L2_6", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
3024
3025/* error_status[] */ { EAR( dram_b3_esr ), EIR( dram_b3_esr), DRAM_DSC_bit, NULL, "L2C" },
3026/* error_record[] */ { NULL, 0 },
3027/* error_report[] */ { NULL, 0 },
3028},
3029
3030
3031{ "DSC_3_L2_7", SS_CE_trap_forward_2_core, DISRUPTING_TT, false, TARGET_MYSELF,
3032
3033/* error_status[] */ { EAR( dram_b3_esr ), EIR( dram_b3_esr), DRAM_DSC_bit, NULL, "L2C" },
3034/* error_record[] */ { NULL, 0 },
3035/* error_report[] */ { NULL, 0 },
3036},
3037
3038
3039/*
3040 * Special case for generating traps which are not associated
3041 * with any particular error.
3042 */
3043
3044{ TRAP_ERR_STRING, TRAP_ONLY_TT, PRECISE_TT, false, TARGET_MYSELF,
3045
3046 /* error_status[] */ { NULL, NULL, 0, NULL },
3047 /* error_record[] */ { NULL, 0 },
3048 /* error_report[] */ { NULL, 0 },
3049},
3050
3051/*
3052 * Special case for generating service processor interrupts
3053 * which are not associated with any particular error.
3054 */
3055{ SP_INTR_ERR_STRING, SS_generate_SP_interrupt, SP_INTR, false, TARGET_SP,
3056
3057 /* error_status */ { NULL, NULL, 0, NULL },
3058 /* error_record[] */ { NULL, 0 },
3059 /* error_report[] */ { NULL, 0 },
3060},
3061
3062/*
3063 * Special case for marking the end of the table.
3064 */
3065{ END_ERR_STRING, INVALID_TRAP, 0, 0, 0,
3066
3067 /* error_status */ { NULL, NULL, 0, NULL },
3068 /* error_record[] */ { NULL, 0 },
3069 /* error_report[] */ { NULL, 0 },
3070},
3071
3072};
3073
3074/*
3075 * CPU specific table of CPU errors for which Legion supports
3076 * SP interrupt generation
3077 */
3078static ss_sp_error_t sp_error_table[] = {
3079 { SP_INTR_ERR_STRING, NULL },
3080 { END_ERR_STRING, NULL },
3081};
3082 ss_proc_t * rpp;
3083 cpu_error_state_t *cpu_es;
3084
3085 rpp = (ss_proc_t*)(config_procp->procp);
3086
3087 rpp->ss_err_state.inj_error_trap = NULL;
3088 rpp->ss_err_state.ready_for_next_injection = true;
3089 rpp->ss_err_state.esrs_clear = true;
3090
3091
3092#if (ERROR_TRAP_GEN > 1)
3093 lprintf(-1, "\n\nERROR_TRAP_GEN: ss_proc_t.ss_err_state = 0x%llx\n", &rpp->ss_err_state);
3094 lprintf(-1, " &(...inj_error_trap) = 0x%llx\n", &(rpp->ss_err_state.inj_error_trap));
3095 lprintf(-1, " &(...ready_for_next_injection) = 0x%llx\n", &(rpp->ss_err_state.ready_for_next_injection));
3096 lprintf(-1, " &(...esrs_clear) = 0x%llx\n", &(rpp->ss_err_state.esrs_clear));
3097 lprintf(-1, " &(...err_lock) = 0x%llx\n\n", &(rpp->ss_err_state.err_lock));
3098#endif
3099
3100 /*
3101 * Allocate space for and initialize the
3102 * CPU-specific Error Trap Injection state.
3103 */
3104 cpu_es = Xcalloc(1, cpu_error_state_t);
3105
3106 rpp->cpu_err_statep = cpu_es;
3107
3108 rpp->ss_err_state.err_reg_tbl = err_reg_table;
3109 rpp->ss_err_state.err_event_tbl = error_table;
3110 rpp->ss_err_state.sp_err_tbl = sp_error_table;
3111
3112#if (ERROR_TRAP_GEN > 1)
3113 lprintf(-1, "ERROR_TRAP_GEN: ss_proc_t->cpu_err_statep = 0x%llx\n", rpp->cpu_err_statep);
3114 lprintf(-1, " &(...->desr[0]) = 0x%llx\n", &(rpp->cpu_err_statep->desr[0]));
3115 lprintf(-1, " &(...->c_erer[0]) = 0x%llx\n", &(rpp->cpu_err_statep->c_erer[0]));
3116 lprintf(-1, " &(...->s_eter) = 0x%llx\n", &(rpp->cpu_err_statep->s_eter));
3117 lprintf(-1, " &(...->dfesr[0]) = 0x%llx\n", &(rpp->cpu_err_statep->dfesr[0]));
3118#endif
3119
3120 lprintf(-1, "\nERROR_TRAP_GEN: CPU Error Table\n");
3121 dump_cpu_error_table(-1, error_table);
3122 lprintf(-1, "ERROR_TRAP_GEN: END CPU Error Table\n\n");
3123
3124 lprintf(-1, "ERROR_TRAP_GEN: Supported CPU Error Register Table\n");
3125 dump_cpu_error_reg_table(-1, err_reg_table);
3126 lprintf(-1, "ERROR_TRAP_GEN: END Supported CPU Error Register Table\n\n");
3127
3128 lprintf(-1, "ERROR_TRAP_GEN: initial Error Event list:\n");
3129 dump_error_event_list(-1, rpp->ss_err_state.error_event_list_rootp);
3130 lprintf(-1, "ERROR_TRAP_GEN: END initial Error Event list:\n\n");
3131
3132 lprintf(-1, "ERROR_TRAP_GEN: initial Error ASI Override list\n");
3133 dump_error_asi_list(-1, rpp->ss_err_state.error_asi_list_rootp);
3134 lprintf(-1, "ERROR_TRAP_GEN: END Error ASI Override list\n\n");
3135
3136 pthread_mutex_init(&rpp->ss_err_state.injection_lock, NULL);
3137 pthread_mutex_init(&rpp->ss_err_state.err_lock, NULL);
3138}
3139void ss_error_trap_strand_init(config_proc_t * config_procp, simcpu_t * sp) {
3140 ss_proc_t *rpp;
3141 sparcv9_cpu_t *v9p;
3142 ss_strand_t *rsp;
3143 cpu_error_state_t *cpu_es;
3144 cpu_error_reg_t *cpu_er;
3145 int strand_id;
3146 int core_num;
3147
3148 v9p = (sparcv9_cpu_t *)(sp->specificp);
3149 rsp = v9p->impl_specificp;
3150 rpp = (ss_proc_t*)(config_procp->procp);
3151
3152 cpu_es = rpp->cpu_err_statep;
3153
3154 /*
3155 * Allocate space for and initialize the
3156 * per strand access pointers. This struct
3157 * simply defines direct pointers from the
3158 * strand to the various register values
3159 * stored in the chip's cpu_error_state_t
3160 * struct.
3161 */
3162
3163 strand_id = rsp->vcore_id;
3164 core_num = rsp->core;
3165
3166 cpu_er = Xcalloc(1, cpu_error_reg_t);
3167
3168 cpu_er->desr_ptr = &(cpu_es->desr[strand_id]);
3169 cpu_er->clesr_ptr = &(cpu_es->clesr[core_num]);
3170 cpu_er->c_erer_ptr = &(cpu_es->c_erer[core_num]);
3171 cpu_er->s_eter_ptr = &(cpu_es->s_eter[strand_id]);
3172 cpu_er->dfesr_ptr = &(cpu_es->dfesr[strand_id]);
3173
3174 rsp->cpu_err_regp = cpu_er;
3175
3176
3177#if (ERROR_TRAP_GEN > 1)
3178 lprintf(sp->gid, "ERROR_TRAP_GEN: For Strand ID = %d we have initialized:\n", strand_id);
3179 lprintf(sp->gid, " ss_strand_t->cpu_err_regp = 0x%llx\n", rsp->cpu_err_regp);
3180 lprintf(sp->gid, " rsp->cpu_err_regp->desr_ptr = 0x%llx\n", rsp->cpu_err_regp->desr_ptr);
3181 lprintf(sp->gid, " rsp->cpu_err_regp->c_erer_ptr = 0x%llx core_num=%d\n",
3182 rsp->cpu_err_regp->c_erer_ptr, core_num);
3183 lprintf(sp->gid, " rsp->cpu_err_regp->s_eter_ptr = 0x%llx\n", rsp->cpu_err_regp->s_eter_ptr);
3184 lprintf(sp->gid, " rsp->error.isfsr = 0x%llx\n", &(rsp->error.isfsr));
3185 lprintf(sp->gid, " rsp->error.dsfsr = 0x%llx\n", &(rsp->error.dsfsr));
3186 lprintf(sp->gid, " rsp->error.dsfar = 0x%llx\n\n", &(rsp->error.dsfar));
3187 lprintf(sp->gid, " rsp->cpu_err_regp->dfesr_ptr = 0x%llx\n", rsp->cpu_err_regp->dfesr_ptr);
3188#endif
3189
3190 /*
3191 * See if there are any other events which may need to
3192 * be triggered on this CPU.
3193 */
3194 check_pending_error_events(sp);
3195}
3196
3197
3198
3199/*
3200 * One register per chip.
3201 *
3202 * This is a read only register. Much like the
3203 * HW implementation, we don't store any state
3204 * associated with this register. When there is
3205 * an access to this register, we simply go read
3206 * all the F bits of the other ESRs which are
3207 * latched to bits in this register and return
3208 * the result.
3209 */
3210EAR_DEFINITION( clesr ) {
3211 uint64_t val = 0;
3212 ss_proc_t *rpp;
3213 sparcv9_cpu_t *v9p;
3214 ss_strand_t *rsp;
3215 cpu_error_state_t *cesp;
3216 int strand_id, core_num, strand;
3217
3218
3219 rpp = (ss_proc_t *)(sp->config_procp->procp);
3220 v9p = (sparcv9_cpu_t *)(sp->specificp);
3221 rsp = v9p->impl_specificp;
3222
3223 strand_id = rsp->vcore_id;
3224 core_num = rsp->core;
3225 strand = core_num * 8;
3226
3227 cesp = rpp->cpu_err_statep;
3228
3229 if (!is_load) {
3230 /*
3231 * Not expected. I'm not sure if we should
3232 * generate a DAX at this point or not. For
3233 * now a warning message will do.
3234 */
3235 EXEC_WARNING(("ASI_CLESR is not writeble.\n"));
3236 return 0;
3237 }
3238
3239
3240 /* Core_num/strand0 desr */
3241 if (cesp->desr[strand] & MASK64(63,63))
3242 val |= BIT(49);
3243
3244 /* Core_num/strand1 desr */
3245 if (cesp->desr[strand + 1] & MASK64(63,63))
3246 val |= BIT(51);
3247
3248 /* Core_num/strand2 desr */
3249 if (cesp->desr[strand + 2] & MASK64(63,63))
3250 val |= BIT(53);
3251
3252 /* Core_num/strand3 desr */
3253 if (cesp->desr[strand + 3] & MASK64(63,63))
3254 val |= BIT(55);
3255
3256 /* Core_num/strand4 desr */
3257 if (cesp->desr[strand + 4] & MASK64(63,63))
3258 val |= BIT(57);
3259
3260 /* Core_num/strand5 desr */
3261 if (cesp->desr[strand + 5] & MASK64(63,63))
3262 val |= BIT(59);
3263
3264 /* Core_num/strand6 desr */
3265 if (cesp->desr[strand + 6] & MASK64(63,63))
3266 val |= BIT(61);
3267
3268 /* Core_num/strand7 desr */
3269 if (cesp->desr[strand + 7] & MASK64(63,63))
3270 val |= BIT(63);
3271
3272
3273 /* bits 47:0 reserved */
3274
3275DBGERRTRAP( lprintf(sp->gid, "ERROR_TRAP_GEN: access to clesr. returning val 0x%llx\n", val););
3276
3277 return val;
3278}
3279
3280
3281/*
3282 * One register per strand
3283 * but we define one access routine.
3284 *
3285 * Use sp to identify register being
3286 * accessed.
3287 */
3288EAR_DEFINITION( isfsr ) {
3289 ss_proc_t *rpp;
3290 sparcv9_cpu_t *v9p;
3291 ss_strand_t *rsp;
3292 uint64_t val;
3293 int idx;
3294
3295 rpp = (ss_proc_t *)(sp->config_procp->procp);
3296 v9p = (sparcv9_cpu_t *)(sp->specificp);
3297 rsp = v9p->impl_specificp;
3298
3299 /*
3300 * We are only interested in the register
3301 * associated with the strand in question.
3302 */
3303
3304 val = rsp->error.isfsr;
3305
3306
3307 /*
3308 * isfsr:
3309 * .----------------------------------------.
3310 * | R E S E R V E D | ERRTYPE |
3311 * `----------------------------------------'
3312 * 63:3 2:0
3313 * ^ ^
3314 * | |
3315 * | *----> RW
3316 * *-----------------------> RO
3317 *
3318 */
3319 if (is_load) {
3320DBGERRTRAP( lprintf(sp->gid, "ERROR_TRAP_GEN: access to isfsr. returning val 0x%llx\n", val););
3321 return (val);
3322 }
3323 /*
3324 * synchronize the read/modify/write
3325 */
3326 pthread_mutex_lock(&rpp->ss_err_state.err_lock);
3327
3328 val = store_val & MMU_SFSR_MASK;
3329 rsp->error.isfsr = val;
3330
3331DBGERRTRAP( lprintf(sp->gid, "ERROR_TRAP_GEN: access to isfsr. storing val 0x%llx\n", rsp->error.isfsr););
3332
3333 pthread_mutex_unlock(&rpp->ss_err_state.err_lock);
3334
3335 return 0; /* ignored for store operations */
3336
3337}
3338
3339
3340/*
3341 * One register per strand.
3342 * but we define one access routine.
3343 *
3344 * Use sp to identify register for
3345 * injection.
3346 */
3347EIR_DEFINITION( isfsr ) {
3348 ss_proc_t *rpp;
3349 sparcv9_cpu_t *v9p;
3350 ss_strand_t *rsp;
3351 ss_error_entry_t *ep;
3352 uint64_t val;
3353
3354 rpp = (ss_proc_t *)(sp->config_procp->procp);
3355 v9p = (sparcv9_cpu_t *)(sp->specificp);
3356 rsp = v9p->impl_specificp;
3357
3358 pthread_mutex_lock(&rpp->ss_err_state.err_lock);
3359
3360 /*
3361 * We are only interested in the register
3362 * associated with the strand in question.
3363 */
3364 val = rsp->error.isfsr;
3365
3366#if (ERROR_TRAP_GEN > 1)
3367 lprintf(sp->gid, "ERROR_TRAP_GEN: injecting isfsr. old value 0x%llx\n", val);
3368#endif
3369
3370 /*
3371 * See Register diagram in the register
3372 * access routine for isfsr.
3373 */
3374
3375 /*
3376 * There is no latching of the first error. If another
3377 * error occurs before the ISFSR has been examined, the
3378 * new error information is captured in the ISFSR, overwriting
3379 * the old information.
3380 */
3381 /*
3382 * Inject the ESR bit(s) specified
3383 */
3384 val = mask;
3385
3386 rsp->error.isfsr = val;
3387
3388
3389 /*
3390 *Update TPC[TL] with VA
3391 */
3392 v9p->tpc[(v9p->tl)] = sp->eep->address.addr;
3393
3394#if (ERROR_TRAP_GEN > 1)
3395 lprintf(sp->gid, "ERROR_TRAP_GEN: injecting isfsr. new value 0x%llx\n", rsp->error.isfsr);
3396#endif
3397
3398 pthread_mutex_unlock(&rpp->ss_err_state.err_lock);
3399
3400 return true;
3401}
3402
3403
3404/*
3405 * One register per strand
3406 * but we define one access routine.
3407 *
3408 * Use sp to identify register being
3409 * accessed.
3410 */
3411EAR_DEFINITION( dsfsr ) {
3412 ss_proc_t *rpp;
3413 sparcv9_cpu_t *v9p;
3414 ss_strand_t *rsp;
3415 uint64_t val;
3416 int idx;
3417
3418 rpp = (ss_proc_t *)(sp->config_procp->procp);
3419 v9p = (sparcv9_cpu_t *)(sp->specificp);
3420 rsp = v9p->impl_specificp;
3421
3422 /*
3423 * We are only interested in the register
3424 * associated with the strand in question.
3425 */
3426
3427 val = rsp->error.dsfsr;
3428
3429
3430 /*
3431 * dsfsr:
3432 * .----------------------------------------.
3433 * | R E S E R V E D | ERRTYPE |
3434 * `----------------------------------------'
3435 * 63:3 2:0
3436 * ^ ^
3437 * | |
3438 * | *----> RW
3439 * *-----------------------> RO
3440 *
3441 */
3442 if (is_load) {
3443DBGERRTRAP( lprintf(sp->gid, "ERROR_TRAP_GEN: access to dsfsr. returning val 0x%llx\n", val););
3444 return (val);
3445 }
3446 /*
3447 * synchronize the read/modify/write
3448 */
3449 pthread_mutex_lock(&rpp->ss_err_state.err_lock);
3450
3451 val = store_val & MMU_SFSR_MASK;
3452 rsp->error.dsfsr = val;
3453
3454DBGERRTRAP( lprintf(sp->gid, "ERROR_TRAP_GEN: access to dsfsr. storing val 0x%llx\n", val););
3455
3456 pthread_mutex_unlock(&rpp->ss_err_state.err_lock);
3457
3458 return 0; /* ignored for store operations */
3459
3460}
3461
3462
3463/*
3464 * One register per strand.
3465 * but we define one access routine.
3466 *
3467 * Use sp to identify register for
3468 * injection.
3469 */
3470EIR_DEFINITION( dsfsr ) {
3471 ss_proc_t *rpp;
3472 sparcv9_cpu_t *v9p;
3473 ss_strand_t *rsp;
3474 ss_error_entry_t *ep;
3475 uint64_t val;
3476
3477 rpp = (ss_proc_t *)(sp->config_procp->procp);
3478 v9p = (sparcv9_cpu_t *)(sp->specificp);
3479 rsp = v9p->impl_specificp;
3480
3481 pthread_mutex_lock(&rpp->ss_err_state.err_lock);
3482
3483 /*
3484 * We are only interested in the register
3485 * associated with the strand in question.
3486 */
3487 val = rsp->error.dsfsr;
3488
3489#if (ERROR_TRAP_GEN > 1)
3490 lprintf(sp->gid, "ERROR_TRAP_GEN: injecting dsfsr. old value 0x%llx\n", val);
3491#endif
3492
3493 /*
3494 * See Register diagram in the register
3495 * access routine for dsfsr.
3496 */
3497
3498 /*
3499 * There is no latching of the first error. If another
3500 * error occurs before the DSFSR has been examined, the
3501 * new error information is captured in the DSFSR, overwriting
3502 * the old information.
3503 */
3504 /*
3505 * Inject the ESR bit(s) specified
3506 */
3507 val = mask;
3508
3509 rsp->error.dsfsr = val;
3510
3511
3512 /*
3513 *Update dsfar with VA
3514 */
3515 rsp->error.dsfar = sp->eep->address.addr & MASK64(47,0);
3516
3517#if (ERROR_TRAP_GEN > 1)
3518 lprintf(sp->gid, "ERROR_TRAP_GEN: injecting dsfsr. new value 0x%llx\n", rsp->error.dsfsr);
3519 lprintf(sp->gid, "ERROR_TRAP_GEN: injecting dsfar. new value 0x%llx\n", rsp->error.dsfar);
3520#endif
3521
3522 pthread_mutex_unlock(&rpp->ss_err_state.err_lock);
3523
3524 return true;
3525}
3526
3527
3528/*
3529 * One register per strand
3530 * but we define one access routine.
3531 *
3532 * Use sp to identify register being
3533 * accessed.
3534 */
3535EAR_DEFINITION( desr ) {
3536 ss_proc_t *rpp;
3537 sparcv9_cpu_t *v9p;
3538 ss_strand_t *rsp;
3539 uint64_t *regp;
3540 uint64_t val;
3541 int idx;
3542
3543 rpp = (ss_proc_t *)(sp->config_procp->procp);
3544 v9p = (sparcv9_cpu_t *)(sp->specificp);
3545 rsp = v9p->impl_specificp;
3546
3547 /*
3548 * We are only interested in the register
3549 * associated with the strand in question.
3550 */
3551
3552 regp = rsp->cpu_err_regp->desr_ptr;
3553
3554
3555 /*
3556 * desr:
3557 * .----------------------------------------.
3558 * | F | ME | S | ERRTYPE | RSVD | ERRADDR |
3559 * `----------------------------------------'
3560 * 63 62 61 60:56 55:11 10:0
3561 * ^ ^ ^ ^ ^ ^
3562 * | | | | | *----> RO
3563 * | | | | *------------> RC
3564 * | | | *--------------------> RC
3565 * | | *---------------------------> RC
3566 * | *---------------------------------> RC
3567 * *-------------------------------------> RC
3568 *
3569 */
3570 if (is_load) {
3571DBGERRTRAP( lprintf(sp->gid, "ERROR_TRAP_GEN: access to desr. returning val 0x%llx\n", *regp););
3572 val = *regp;
3573 /* Most of the fields of this register are clear on read when accessed by HV.
3574 * legion_access flag is used to prevent clearing this reg when legion accesses it.
3575 */
3576 if (!legion_access) /* HV Access */
3577 *regp = 0; /* Clear all fields on read */
3578 return (val);
3579 }
3580 else {
3581 /* The ASI_DESR is clear on read, a store is not expected */
3582 EXEC_WARNING(("ASI_DESR is not writeble.\n"));
3583 return 0;
3584 }
3585
3586}
3587
3588
3589/*
3590 * One register per strand.
3591 * but we define one access routine.
3592 *
3593 * Use sp to identify register for
3594 * injection.
3595 */
3596EIR_DEFINITION( desr ) {
3597 ss_proc_t *rpp;
3598 sparcv9_cpu_t *v9p;
3599 ss_strand_t *rsp;
3600 ss_error_entry_t *ep;
3601 uint64_t val;
3602 bool_t new_trap;
3603
3604 rpp = (ss_proc_t *)(sp->config_procp->procp);
3605 v9p = (sparcv9_cpu_t *)(sp->specificp);
3606 rsp = v9p->impl_specificp;
3607
3608 pthread_mutex_lock(&rpp->ss_err_state.err_lock);
3609
3610 /*
3611 * We are only interested in the register
3612 * associated with the strand in question.
3613 */
3614 val = *(rsp->cpu_err_regp->desr_ptr);
3615
3616#if (ERROR_TRAP_GEN > 1)
3617 lprintf(sp->gid, "ERROR_TRAP_GEN: injecting desr. old value 0x%llx\n", val);
3618#endif
3619
3620 /*
3621 * See Register diagram in the register
3622 * access routine for desr.
3623 */
3624
3625 if (errp->trap_type == SS_trap_sw_recoverable_error) {
3626 if (val & MASK64(63,63)) { /* Checking the F bit */
3627 if (val & MASK64(61,61)) { /* Checking the S bit */
3628 val |= MASK64(62,62); /* Only turn on the ME bit */
3629 new_trap = false;
3630 } else {
3631 val |= mask; /* Update DESR.Errortype field */
3632 val |= MASK64(63,61); /* Turn on F, Me & S bits */
3633 new_trap = false;
3634 }
3635 } else { /* F bit is turned off */
3636 val |= mask; /* Update DESR.Errortype field */
3637 val |= (MASK64(63,63)|MASK64(61,61)); /* Turn on F & S bits */
3638
3639 /*Modify the additional bits if its CWQL2U/MAL2U error*/
3640 if (strcmp(sp->eep->error_str, "CWQL2U") == 0) {
3641 rpp->stream_cwq_p->cwq_CSR & CWQ_CSR_HWE & ~CWQ_CSR_BUSY & ~CWQ_CSR_ENABLED;
3642 } else if (strcmp(sp->eep->error_str, "MAL2U") == 0) {
3643 rpp->mod_arith_p->HWE = 1;
3644 rpp->mod_arith_p->busy = 0;
3645 }
3646 new_trap = true;
3647 }
3648 } else if (errp->trap_type == SS_trap_hw_corrected_error) {
3649 if (val & MASK64(63,63)) {
3650 /*
3651 * Only turn on the ME bit.
3652 */
3653 val |= MASK64(62,62);
3654 new_trap = false;
3655 } else {
3656 /*
3657 * Inject the ESR bit(s) specified
3658 * and update the F bit.
3659 */
3660 val |= mask;
3661 if (val & MASK64(60,56)) {
3662 /* make sure F bit is on */
3663 val |= MASK64(63,63);
3664 }
3665 new_trap = true;
3666 }
3667 }
3668
3669 *(rsp->cpu_err_regp->desr_ptr) = val;
3670
3671#if (ERROR_TRAP_GEN > 1)
3672 lprintf(sp->gid, "ERROR_TRAP_GEN: injecting desr. new value 0x%llx\n", val);
3673#endif
3674
3675 pthread_mutex_unlock(&rpp->ss_err_state.err_lock);
3676
3677 return (new_trap);
3678}
3679
3680/* One register per strand
3681 * but we define one access routine.
3682 *
3683 * Use sp to identify register being
3684 * accessed.
3685 */
3686EAR_DEFINITION( dfesr ) {
3687 ss_proc_t *rpp;
3688 sparcv9_cpu_t *v9p;
3689 ss_strand_t *rsp;
3690 uint64_t *regp;
3691 uint64_t val;
3692 int idx;
3693
3694 rpp = (ss_proc_t *)(sp->config_procp->procp);
3695 v9p = (sparcv9_cpu_t *)(sp->specificp);
3696 rsp = v9p->impl_specificp;
3697
3698 /*
3699 * We are only interested in the register
3700 * associated with the strand in question.
3701 */
3702
3703 regp = rsp->cpu_err_regp->dfesr_ptr;
3704
3705
3706 /*
3707 * dfesr:
3708 * .----------------------------------------.
3709 * | RSVD | TYPE | PRIV | STBIDX | RESERVED |
3710 * `----------------------------------------'
3711 * 63:62 61:60 59:58 57:55 54:0
3712 * ^ ^ ^ ^ ^
3713 * | | | | |
3714 * | | | | *---> RC
3715 * | | | *--------------> RC
3716 * | | *---------------------> RC
3717 * | *-----------------------------> RC
3718 * *------------------------------------> RC
3719 *
3720 */
3721 if (is_load) {
3722DBGERRTRAP( lprintf(sp->gid, "ERROR_TRAP_GEN: access to dfesr. returning val 0x%llx\n", *regp););
3723 val = *regp;
3724 /* All the fields of this register are cleared on read when accessed by HV.
3725 * legion_access flag is used to prevent clearing this reg when legion accesses it.
3726 */
3727 if (!legion_access) /* HV Access */
3728 *regp = 0; /* Clear all fields on read */
3729 return (val);
3730 }
3731 else {
3732 /* The ASI_DESR is clear on read, a store is not expected */
3733 EXEC_WARNING(("ASI_DESR (DFESR) is not writeble.\n"));
3734 return 0;
3735 }
3736
3737}
3738
3739
3740/*
3741 * One register per strand.
3742 * but we define one access routine.
3743 *
3744 * Use sp to identify register for
3745 * injection.
3746 */
3747EIR_DEFINITION( dfesr ) {
3748 ss_proc_t *rpp;
3749 sparcv9_cpu_t *v9p;
3750 ss_strand_t *rsp;
3751 uint64_t val;
3752
3753 rpp = (ss_proc_t *)(sp->config_procp->procp);
3754 v9p = (sparcv9_cpu_t *)(sp->specificp);
3755 rsp = v9p->impl_specificp;
3756
3757 pthread_mutex_lock(&rpp->ss_err_state.err_lock);
3758
3759 /*
3760 * We are only interested in the register
3761 * associated with the strand in question.
3762 */
3763 val = *(rsp->cpu_err_regp->dfesr_ptr);
3764
3765#if (ERROR_TRAP_GEN > 1)
3766 lprintf(sp->gid, "ERROR_TRAP_GEN: injecting dfesr. old value 0x%llx\n", val);
3767#endif
3768
3769
3770 val |= mask;
3771 /*Setting the priv level of this error as specified in error.conf*/
3772 switch (sp->eep->priv) {
3773 case V9_User:
3774#if (ERROR_TRAP_GEN > 1)
3775 lprintf(sp->gid, "ERROR_TRAP_GEN: %s priv level = USER\n", sp->eep->error_str);
3776#endif
3777 break;
3778 case V9_Priv:
3779 val |= MASK64(58,58);
3780#if (ERROR_TRAP_GEN > 1)
3781 lprintf(sp->gid, "ERROR_TRAP_GEN: %s priv level = PRIVILEDGED\n", sp->eep->error_str);
3782#endif
3783 break;
3784 case V9_HyperPriv:
3785 val |= MASK64(59,59);
3786#if (ERROR_TRAP_GEN > 1)
3787 lprintf(sp->gid, "ERROR_TRAP_GEN: %s priv level = HYPERPRIVILEDGED\n", sp->eep->error_str);
3788#endif
3789 break;
3790 default:
3791 val |= MASK64(58,58);
3792#if (ERROR_TRAP_GEN > 1)
3793 lprintf(sp->gid, "ERROR_TRAP_GEN: No priv level specified for %s, defaulting to PRIVILEDGED\n", sp->eep->error_str);
3794#endif
3795 }/*switch*/
3796
3797
3798 *(rsp->cpu_err_regp->dfesr_ptr) = val;
3799
3800#if (ERROR_TRAP_GEN > 1)
3801 lprintf(sp->gid, "ERROR_TRAP_GEN: injecting dfesr. new value 0x%llx\n", val);
3802#endif
3803
3804 pthread_mutex_unlock(&rpp->ss_err_state.err_lock);
3805
3806 return true;
3807}
3808
3809/*
3810 * One register per core. (8 total)
3811 * but we define one access routine.
3812 *
3813 * Use sp to identify register being
3814 * accessed.
3815 */
3816EAR_DEFINITION( c_erer ) {
3817 ss_proc_t *rpp;
3818 sparcv9_cpu_t *v9p;
3819 ss_strand_t *rsp;
3820 ss_error_entry_t *ep;
3821 uint64_t *regp;
3822 uint64_t val;
3823 int idx;
3824
3825 rpp = (ss_proc_t *)(sp->config_procp->procp);
3826 v9p = (sparcv9_cpu_t *)(sp->specificp);
3827 rsp = v9p->impl_specificp;
3828
3829 /*
3830 * We are only interested in the register
3831 * associated with the strand in question.
3832 */
3833 regp = rsp->cpu_err_regp->c_erer_ptr;
3834
3835 if (is_load) {
3836DBGERRTRAP( lprintf(sp->gid, "ERROR_TRAP_GEN: access to c_erer. returning val 0x%llx\n", *regp););
3837 return (*regp);
3838 }
3839
3840 val = store_val & CERER_MASK;
3841 *regp = val;
3842
3843DBGERRTRAP( lprintf(sp->gid, "ERROR_TRAP_GEN: access to c_erer. storing val 0x%llx\n", *regp););
3844
3845 return 0; /* ignored for store operations */
3846}
3847
3848/*
3849 * One register per strand.
3850 */
3851EAR_DEFINITION( s_eter ) {
3852 ss_proc_t *rpp;
3853 sparcv9_cpu_t *v9p;
3854 ss_strand_t *rsp;
3855 ss_error_entry_t *ep;
3856 uint64_t *regp;
3857 uint64_t val;
3858 int idx;
3859 ss_error_entry_t *error_table;
3860
3861
3862 rpp = (ss_proc_t *)(sp->config_procp->procp);
3863 v9p = (sparcv9_cpu_t *)(sp->specificp);
3864 rsp = v9p->impl_specificp;
3865
3866 error_table = rpp->ss_err_state.err_event_tbl;
3867
3868 regp = rsp->cpu_err_regp->s_eter_ptr;
3869
3870
3871 /*
3872 * s_eter:
3873 * .---------------------------------------------.
3874 * | RSVD | PSCCE | DE | DHCCE | RSVD |
3875 * `---------------------------------------------'
3876 * 63 62 61 60 59:0
3877 * ^ ^ ^ ^ ^
3878 * | | | | *-> R
3879 * | | | |
3880 * | | | *---------------> R/W
3881 * | | *---------------------> R/W
3882 * | *----------------------------> R/W
3883 * *------------------------------------> R
3884 *
3885 */
3886 if (is_load) {
3887DBGERRTRAP( lprintf(sp->gid, "ERROR_TRAP_GEN: access to s_eter. returning val 0x%llx\n", *regp););
3888 return (*regp);
3889 }
3890
3891 pthread_mutex_lock(&rpp->ss_err_state.err_lock);
3892
3893 val = store_val & MASK64(62,60);
3894 *regp = val;
3895
3896 /*
3897 * Get new StrandID value for disrupting traps
3898 */
3899 val = rsp->vcore_id;
3900
3901 /*
3902 * Update the trap target StrandID value for
3903 * all disrupting traps in our global error
3904 * table.
3905 */
3906 for (idx=0; error_table[idx].trap_type != INVALID_TRAP; idx++) {
3907 if (error_table[idx].trap_class == DISRUPTING_TT) {
3908 error_table[idx].trap_target = val;
3909 }
3910 }
3911
3912
3913
3914#if (ERROR_TRAP_GEN > 1)
3915 lprintf(sp->gid, "ERROR_TRAP_GEN: access to s_eter. storing val 0x%llx\n", *regp);
3916 lprintf(sp->gid, "ERROR_TRAP_GEN: access to s_eter: Updated all disrupting trap targets to CPU 0x%x\n", val);
3917 lprintf(sp->gid, "ERROR_TRAP_GEN: Updated CPU Error Table\n");
3918 dump_cpu_error_table(sp->gid, error_table);
3919 lprintf(sp->gid, "ERROR_TRAP_GEN: END Updated CPU Error Table\n\n");
3920#endif
3921
3922
3923 pthread_mutex_unlock(&rpp->ss_err_state.err_lock);
3924
3925 return 0; /* ignored for store operations */
3926}
3927
3928/*
3929 * One register per l2$ bank (8 total)
3930 * we define separate access routines.
3931 */
3932
3933EAR_DEFINITION( l2_b0_esr ) {
3934 return (l2_esr_access(0, sp, asi, addr, is_load, store_val, legion_access));
3935}
3936
3937EAR_DEFINITION( l2_b1_esr ) {
3938 return (l2_esr_access(1, sp, asi, addr, is_load, store_val, legion_access));
3939}
3940
3941EAR_DEFINITION( l2_b2_esr ) {
3942 return (l2_esr_access(2, sp, asi, addr, is_load, store_val, legion_access));
3943}
3944
3945EAR_DEFINITION( l2_b3_esr ) {
3946 return (l2_esr_access(3, sp, asi, addr, is_load, store_val, legion_access));
3947}
3948
3949EAR_DEFINITION( l2_b4_esr ) {
3950 return (l2_esr_access(4, sp, asi, addr, is_load, store_val, legion_access));
3951}
3952
3953EAR_DEFINITION( l2_b5_esr ) {
3954 return (l2_esr_access(5, sp, asi, addr, is_load, store_val, legion_access));
3955}
3956
3957EAR_DEFINITION( l2_b6_esr ) {
3958 return (l2_esr_access(6, sp, asi, addr, is_load, store_val, legion_access));
3959}
3960
3961EAR_DEFINITION( l2_b7_esr ) {
3962 return (l2_esr_access(7, sp, asi, addr, is_load, store_val, legion_access));
3963}
3964
3965
3966
3967uint64_t l2_esr_access (int bank, EAR_ARGS) {
3968 ss_proc_t *rpp;
3969 sparcv9_cpu_t *v9p;
3970 ss_strand_t *rsp;
3971 uint64_t reg;
3972 uint64_t val;
3973 l2c_t *l2p;
3974
3975 rpp = (ss_proc_t *)(sp->config_procp->procp);
3976 v9p = (sparcv9_cpu_t *)(sp->specificp);
3977 rsp = v9p->impl_specificp;
3978 l2p = rpp->l2p;
3979
3980
3981 reg = l2p->error_status[bank];
3982
3983 /*
3984 * l2_esr:
3985 * .--------------------------------------------------------------.
3986 * |MEU|MEC|RW|MODA| VCID |LDAC|LDAU|LDWC|LDWU|LDRC|LDRU|LDSC|LDSU|
3987 * `--------------------------------------------------------------'
3988 * 63 62 61 60 59:54 53 52 51 50 49 48 47 46
3989 * ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
3990 * | | | | | | | | | | | | |
3991 * | | | | | *----*----*----*----*----*----*----*
3992 * | | | | | |
3993 * | | | | | *--------------------> R/W1C
3994 * | | | | *-----------------------------------------> RW
3995 * | | | *-----------------------------------------------> RW
3996 * | | *---------------------------------------------------> RW
3997 * | *-------------------------------------------------------> R/W1C
3998 * *-----------------------------------------------------------> R/W1C
3999 *
4000 * .------------------------------------------------------------.
4001 * |LTC|LRF|LVF|DAC|DAU|DRC|DRU|DSC|DSU|VEC|VEU|LVC| RSVD1 |SYND|
4002 * `------------------------------------------------------------'
4003 * 45 44 43 42 41 40 39 38 37 36 35 34 33:28 27:0
4004 * ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
4005 * | | | | | | | | | | | | | |
4006 * *---*---*---*---*----*---*---*---*---*---*---* | *-> RW
4007 * | *--------> RO
4008 * *-------------------------------------> R/W1C
4009 *
4010 */
4011
4012 if (is_load) {
4013DBGERRTRAP( lprintf(sp->gid, "ERROR_TRAP_GEN: access to l2_b%d_esr. returning val 0x%llx\n", bank, reg););
4014 return (reg);
4015 }
4016 /*
4017 * synchronize the read/modify/write
4018 */
4019 pthread_mutex_lock(&rpp->ss_err_state.err_lock);
4020
4021 val = store_val & ( MASK64(63,62)|MASK64(53,34) );
4022 reg = reg & ~(val);
4023
4024 /*
4025 * Update the MODA bit
4026 */
4027 if (!(reg & ( MASK64(63,62)|MASK64(53,34) ))){
4028 /* make sure MODA bit is off */
4029 reg &= ~(MASK64(60,60));
4030 }
4031
4032 l2p->error_status[bank] = reg;
4033
4034DBGERRTRAP( lprintf(sp->gid, "ERROR_TRAP_GEN: access to l2_b%d_esr. storing val 0x%llx\n", bank, reg););
4035
4036 pthread_mutex_unlock(&rpp->ss_err_state.err_lock);
4037
4038 return 0; /* ignored for store operations */
4039}
4040
4041
4042EIR_DEFINITION( l2_b0_esr ) {
4043 return (l2_esr_inject(0, sp, mask, errp));
4044}
4045
4046EIR_DEFINITION( l2_b1_esr ) {
4047 return (l2_esr_inject(1, sp, mask, errp));
4048}
4049
4050EIR_DEFINITION( l2_b2_esr ) {
4051 return (l2_esr_inject(2, sp, mask, errp));
4052}
4053
4054EIR_DEFINITION( l2_b3_esr ) {
4055 return (l2_esr_inject(3, sp, mask, errp));
4056}
4057
4058EIR_DEFINITION( l2_b4_esr ) {
4059 return (l2_esr_inject(4, sp, mask, errp));
4060}
4061
4062EIR_DEFINITION( l2_b5_esr ) {
4063 return (l2_esr_inject(5, sp, mask, errp));
4064}
4065
4066EIR_DEFINITION( l2_b6_esr ) {
4067 return (l2_esr_inject(6, sp, mask, errp));
4068}
4069
4070EIR_DEFINITION( l2_b7_esr ) {
4071 return (l2_esr_inject(7, sp, mask, errp));
4072}
4073
4074
4075bool_t l2_esr_inject (int bank, EIR_ARGS) {
4076 ss_proc_t *rpp;
4077 sparcv9_cpu_t *v9p;
4078 ss_strand_t *rsp;
4079 uint64_t reg;
4080 bool_t new_trap, is_ready;
4081 l2c_t *l2p;
4082 char *err_string;
4083
4084 rpp = (ss_proc_t *)(sp->config_procp->procp);
4085 v9p = (sparcv9_cpu_t *)(sp->specificp);
4086 rsp = v9p->impl_specificp;
4087 l2p = rpp->l2p;
4088 err_string = errp->error_status.err_inject_name;
4089
4090 pthread_mutex_lock(&rpp->ss_err_state.err_lock);
4091
4092 reg = l2p->error_status[bank];
4093
4094#if (ERROR_TRAP_GEN > 1)
4095 lprintf(sp->gid, "ERROR_TRAP_GEN: injecting l2_b%d_esr. old value 0x%llx\n", bank, reg);
4096#endif
4097
4098 /*
4099 * See Register diagram in the register
4100 * access routine for l2_esr.
4101 */
4102
4103 if (mask & CE_MASK) { /* Correctable Error */
4104 if (l2_esr_access (bank, sp, ASI_NA, ADDR_NA, true, 0, true) & MASK64(36,36)) {
4105 /* VEC bit is already set in l2_esr
4106 * Update the MEC bit
4107 */
4108 reg |= MASK64(62,62);
4109 new_trap = false;
4110 } else {
4111 /*
4112 * Inject the ESR bit(s) specified
4113 * and update the VEC bit.
4114 */
4115 reg |= mask;
4116 if (reg & CE_MASK) {
4117 /* make sure VEC bit is on */
4118 reg |= MASK64(36,36);
4119 if (strncmp(sp->eep->error_str, "MAL2C_", 6) == 0)
4120 reg |= MASK64(60,60); /* Set the MODA bit */
4121
4122#if (ERROR_TRAP_GEN > 1)
4123 lprintf(sp->gid, "ERROR_TRAP_GEN: injecting l2_b%d_esr. new value 0x%llx\n", bank, reg);
4124#endif
4125
4126 l2p->error_status[bank] = reg;
4127
4128 is_ready = false;
4129 /* This error will be forwarded to the core and the error name
4130 * defined by error_inject_name field of this error_entry will be
4131 * injected into the core. The core error injection code will try
4132 * to grab this lock so releasing it here before injecting core error
4133 */
4134 pthread_mutex_unlock(&rpp->ss_err_state.err_lock);
4135 /*
4136 * Checking L2_eer to see if CEEN is set
4137 */
4138 if (l2_eer_access(bank, sp, ASI_NA, ADDR_NA, true, 0, true) & MASK64(0,0)){
4139 is_ready = true;
4140
4141 /*
4142 * The hw correctable L2$ error are posted as L2C disrupting traps
4143 */
4144
4145#if (ERROR_TRAP_GEN > 1)
4146 lprintf(sp->gid, "ERROR_TRAP_GEN: This L2$ error in l2_b%d_esr is actually posted as %s error trap\n", bank, err_string);
4147#endif
4148 ss_inject_error_trap(sp, err_string, 0, 0);
4149 }
4150 /*
4151 * The trap has already been posted as L2C error trap.
4152 * Hence setting new_trap to false
4153 */
4154 new_trap = false;
4155
4156#if (ERROR_TRAP_GEN > 1)
4157 lprintf(sp->gid, "ERROR_TRAP_GEN: CEEN in L2 Error Enable Register is %s\n",
4158 is_ready ? "ON" : "OFF" );
4159#endif
4160 }
4161 }
4162
4163 } else { /*Uncorrectable Error*/
4164 if (l2_esr_access (bank, sp, ASI_NA, ADDR_NA, true, 0, true) & MASK64(35,35)) {
4165 /* VEU bit is already set in l2_esr
4166 * Update the MEU bit
4167 */
4168 reg |= MASK64(63,63);
4169 new_trap = false;
4170 } else {
4171 /*
4172 * Inject the ESR bit(s) specified
4173 * and update the VEU bit.
4174 */
4175 reg |= mask;
4176
4177 if (reg & UE_MASK) {
4178 /* make sure VEU bit is on */
4179 reg |= MASK64(35,35);
4180 if (strncmp(sp->eep->error_str, "MAL2U_", 6) == 0)
4181 reg |= MASK64(60,60); /* Set the MODA bit */
4182
4183#if (ERROR_TRAP_GEN > 1)
4184 lprintf(sp->gid, "ERROR_TRAP_GEN: injecting l2_b%d_esr. new value 0x%llx\n", bank, reg);
4185#endif
4186
4187 l2p->error_status[bank] = reg;
4188
4189 is_ready = false;
4190 /* This error will be forwarded to the core and the error name
4191 * defined by error_inject_name field of this error_entry will be
4192 * injected into the core. The core error injection code will try
4193 * to grab this lock so releasing it here before injecting core error
4194 */
4195 pthread_mutex_unlock(&rpp->ss_err_state.err_lock);
4196 /*
4197 * Checking L2_eer to see if NCEEN is set
4198 */
4199 if (l2_eer_access(bank, sp, ASI_NA, ADDR_NA, true, 0, true) & MASK64(1,1)){
4200 is_ready = true;
4201
4202 /*
4203 * The hw uncorrectable L2$ error are posted as precise traps
4204 */
4205
4206#if (ERROR_TRAP_GEN > 1)
4207 lprintf(sp->gid, "ERROR_TRAP_GEN: This L2$ error in l2_b%d_esr is actually posted as %s error trap\n", bank, err_string);
4208#endif
4209 ss_inject_error_trap(sp, err_string, 0, 0);
4210 }
4211 /*
4212 * The trap has already been posted as L2C error trap.
4213 * Hence setting new_trap to false
4214 */
4215 new_trap = false;
4216
4217#if (ERROR_TRAP_GEN > 1)
4218 lprintf(sp->gid, "ERROR_TRAP_GEN: NCEEN in L2 Error Enable Register is %s\n",
4219 is_ready ? "ON" : "OFF" );
4220#endif
4221 }
4222 }
4223
4224 }
4225
4226
4227 return (new_trap);
4228}
4229
4230
4231/*
4232 * One register per l2$ bank (8 total)
4233 * we define separate access routines.
4234 */
4235
4236EAR_DEFINITION( l2_b0_eer ) {
4237 return (l2_eer_access(0, sp, asi, addr, is_load, store_val, legion_access));
4238}
4239
4240EAR_DEFINITION( l2_b1_eer ) {
4241 return (l2_eer_access(1, sp, asi, addr, is_load, store_val, legion_access));
4242}
4243
4244EAR_DEFINITION( l2_b2_eer ) {
4245 return (l2_eer_access(2, sp, asi, addr, is_load, store_val, legion_access));
4246}
4247
4248EAR_DEFINITION( l2_b3_eer ) {
4249 return (l2_eer_access(3, sp, asi, addr, is_load, store_val, legion_access));
4250}
4251
4252EAR_DEFINITION( l2_b4_eer ) {
4253 return (l2_eer_access(4, sp, asi, addr, is_load, store_val, legion_access));
4254}
4255
4256EAR_DEFINITION( l2_b5_eer ) {
4257 return (l2_eer_access(5, sp, asi, addr, is_load, store_val, legion_access));
4258}
4259
4260EAR_DEFINITION( l2_b6_eer ) {
4261 return (l2_eer_access(6, sp, asi, addr, is_load, store_val, legion_access));
4262}
4263
4264EAR_DEFINITION( l2_b7_eer ) {
4265 return (l2_eer_access(7, sp, asi, addr, is_load, store_val, legion_access));
4266}
4267
4268uint64_t l2_eer_access (int bank, EAR_ARGS) {
4269 ss_proc_t *rpp;
4270 sparcv9_cpu_t *v9p;
4271 ss_strand_t *rsp;
4272 uint64_t reg;
4273 l2c_t *l2p;
4274
4275 rpp = (ss_proc_t *)(sp->config_procp->procp);
4276 v9p = (sparcv9_cpu_t *)(sp->specificp);
4277 rsp = v9p->impl_specificp;
4278 l2p = rpp->l2p;
4279
4280 reg = l2p->error_enable[bank];
4281
4282 if (is_load) {
4283DBGERRTRAP( lprintf(sp->gid, "ERROR_TRAP_GEN: access to l2_b%d_eer. returning val 0x%llx\n", bank, reg););
4284 return (reg);
4285 }
4286
4287 reg = store_val & MASK64(2,0);
4288
4289DBGERRTRAP( lprintf(sp->gid, "ERROR_TRAP_GEN: access to l2_b%d_eer. storing val 0x%llx\n", bank, reg););
4290
4291 return 0; /* ignored for store operations */
4292}
4293
4294/*
4295 * L2 notdata registers, one per l2$ bank (8 total)
4296 * we define separate access routines.
4297 */
4298
4299EAR_DEFINITION( l2nd_b0_esr ) {
4300 return (l2nd_esr_access(0, sp, asi, addr, is_load, store_val, legion_access));
4301}
4302
4303EAR_DEFINITION( l2nd_b1_esr ) {
4304 return (l2nd_esr_access(1, sp, asi, addr, is_load, store_val, legion_access));
4305}
4306
4307EAR_DEFINITION( l2nd_b2_esr ) {
4308 return (l2_esr_access(2, sp, asi, addr, is_load, store_val, legion_access));
4309}
4310
4311EAR_DEFINITION( l2nd_b3_esr ) {
4312 return (l2nd_esr_access(3, sp, asi, addr, is_load, store_val, legion_access));
4313}
4314
4315EAR_DEFINITION( l2nd_b4_esr ) {
4316 return (l2nd_esr_access(4, sp, asi, addr, is_load, store_val, legion_access));
4317}
4318
4319EAR_DEFINITION( l2nd_b5_esr ) {
4320 return (l2nd_esr_access(5, sp, asi, addr, is_load, store_val, legion_access));
4321}
4322
4323EAR_DEFINITION( l2nd_b6_esr ) {
4324 return (l2nd_esr_access(6, sp, asi, addr, is_load, store_val, legion_access));
4325}
4326
4327EAR_DEFINITION( l2nd_b7_esr ) {
4328 return (l2nd_esr_access(7, sp, asi, addr, is_load, store_val, legion_access));
4329}
4330
4331
4332
4333uint64_t l2nd_esr_access (int bank, EAR_ARGS) {
4334 ss_proc_t *rpp;
4335 sparcv9_cpu_t *v9p;
4336 ss_strand_t *rsp;
4337 uint64_t reg;
4338 uint64_t val;
4339 l2c_t *l2p;
4340
4341 rpp = (ss_proc_t *)(sp->config_procp->procp);
4342 v9p = (sparcv9_cpu_t *)(sp->specificp);
4343 rsp = v9p->impl_specificp;
4344 l2p = rpp->l2p;
4345
4346
4347 reg = l2p->error_notdata[bank];
4348
4349 /*
4350 * l2nd_esr:
4351 *
4352 * .-------------------------------------------------------------.
4353 * | RESERVED |MEND|RW|NDSP|NDDM| RSVD | VCID | ADDRESS | RSVD |
4354 * `-------------------------------------------------------------'
4355 * 63:52 51 50 49 48 47:46 45:40 39:4 3:0
4356 * ^ ^ ^ ^ ^ ^ ^ ^ ^
4357 * | | | | | | | | |
4358 * | | | *----* | *---------* *---> RO
4359 * | | | | | |
4360 * | | | | | *---------------> RW
4361 * | | | | *----------------------------> RO
4362 * | | | *-------------------------------------> R/W1C
4363 * | | *-------------------------------------------> RW
4364 * | *-----------------------------------------------> R/W1C
4365 * *-------------------------------------------------------> RO
4366 */
4367
4368 if (is_load) {
4369DBGERRTRAP( lprintf(sp->gid, "ERROR_TRAP_GEN: access to l2nd_b%d_esr. returning val 0x%llx\n", bank, reg););
4370 return (reg);
4371 }
4372 /*
4373 * synchronize the read/modify/write
4374 */
4375 pthread_mutex_lock(&rpp->ss_err_state.err_lock);
4376
4377 val = store_val & ( MASK64(51,51)|MASK64(49,48) );
4378 reg = reg & ~(val);
4379
4380 l2p->error_notdata[bank] = reg;
4381
4382DBGERRTRAP( lprintf(sp->gid, "ERROR_TRAP_GEN: access to l2nd_b%d_esr. storing val 0x%llx\n", bank, reg););
4383
4384 pthread_mutex_unlock(&rpp->ss_err_state.err_lock);
4385
4386 return 0; /* ignored for store operations */
4387}
4388
4389
4390EIR_DEFINITION( l2nd_b0_esr ) {
4391 return (l2nd_esr_inject(0, sp, mask, errp));
4392}
4393
4394EIR_DEFINITION( l2nd_b1_esr ) {
4395 return (l2nd_esr_inject(1, sp, mask, errp));
4396}
4397
4398EIR_DEFINITION( l2nd_b2_esr ) {
4399 return (l2nd_esr_inject(2, sp, mask, errp));
4400}
4401
4402EIR_DEFINITION( l2nd_b3_esr ) {
4403 return (l2nd_esr_inject(3, sp, mask, errp));
4404}
4405
4406EIR_DEFINITION( l2nd_b4_esr ) {
4407 return (l2nd_esr_inject(4, sp, mask, errp));
4408}
4409
4410EIR_DEFINITION( l2nd_b5_esr ) {
4411 return (l2nd_esr_inject(5, sp, mask, errp));
4412}
4413
4414EIR_DEFINITION( l2nd_b6_esr ) {
4415 return (l2nd_esr_inject(6, sp, mask, errp));
4416}
4417
4418EIR_DEFINITION( l2nd_b7_esr ) {
4419 return (l2nd_esr_inject(7, sp, mask, errp));
4420}
4421
4422
4423bool_t l2nd_esr_inject (int bank, EIR_ARGS) {
4424 ss_proc_t *rpp;
4425 sparcv9_cpu_t *v9p;
4426 ss_strand_t *rsp;
4427 uint64_t reg;
4428 bool_t new_trap, is_ready;
4429 l2c_t *l2p;
4430 char *err_string;
4431
4432 rpp = (ss_proc_t *)(sp->config_procp->procp);
4433 v9p = (sparcv9_cpu_t *)(sp->specificp);
4434 rsp = v9p->impl_specificp;
4435 l2p = rpp->l2p;
4436 err_string = errp->error_status.err_inject_name;
4437
4438 pthread_mutex_lock(&rpp->ss_err_state.err_lock);
4439
4440 reg = l2p->error_notdata[bank];
4441
4442#if (ERROR_TRAP_GEN > 1)
4443 lprintf(sp->gid, "ERROR_TRAP_GEN: injecting l2nd_b%d_esr. old value 0x%llx\n", bank, reg);
4444#endif
4445
4446 /*
4447 * See Register diagram in the register
4448 * access routine for l2nd_esr.
4449 */
4450
4451 if (l2_esr_access (bank, sp, ASI_NA, ADDR_NA, true, 0, true) & MASK64(49,48)) {
4452 /*
4453 * Multiple Not Data errors, update the MEND bit
4454 */
4455 reg |= MASK64(51,51);
4456 new_trap = false;
4457 } else {
4458 /*
4459 * Inject the ESR bit(s) specified
4460 */
4461 reg |= mask;
4462
4463#if (ERROR_TRAP_GEN > 1)
4464 lprintf(sp->gid, "ERROR_TRAP_GEN: injecting l2nd_b%d_esr. new value 0x%llx\n", bank, reg);
4465#endif
4466
4467 l2p->error_notdata[bank] = reg;
4468
4469 is_ready = false;
4470 /* This error will be forwarded to the core and the error name
4471 * defined by error_inject_name field of this error_entry will be
4472 * injected into the core. The core error injection code will try
4473 * to grab this lock so releasing it here before injecting core error
4474 */
4475 pthread_mutex_unlock(&rpp->ss_err_state.err_lock);
4476 /*
4477 * Checking L2_eer to see if NCEEN is set
4478 */
4479 if (l2_eer_access(bank, sp, ASI_NA, ADDR_NA, true, 0, true) & MASK64(1,1)){
4480 is_ready = true;
4481
4482
4483#if (ERROR_TRAP_GEN > 1)
4484 lprintf(sp->gid, "ERROR_TRAP_GEN: This L2$ not data error in l2nd_b%d_esr is actually posted as %s error trap\n", bank, err_string);
4485#endif
4486 ss_inject_error_trap(sp, err_string, 0, 0);
4487 }
4488 /*
4489 * The trap has already been posted.
4490 * Hence setting new_trap to false
4491 */
4492 new_trap = false;
4493
4494#if (ERROR_TRAP_GEN > 1)
4495 lprintf(sp->gid, "ERROR_TRAP_GEN: NCEEN in L2 Error Enable Register is %s\n",
4496 is_ready ? "ON" : "OFF" );
4497#endif
4498 }
4499
4500 return (new_trap);
4501}
4502
4503
4504/*
4505 * One register per dram channel(8 total)
4506 * we define separate access routines.
4507 */
4508
4509EAR_DEFINITION( dram_b0_esr ) {
4510 return (dram_esr_access(0, sp, asi, addr, is_load, store_val, legion_access));
4511}
4512
4513EAR_DEFINITION( dram_b1_esr ) {
4514 return (dram_esr_access(1, sp, asi, addr, is_load, store_val, legion_access));
4515}
4516
4517EAR_DEFINITION( dram_b2_esr ) {
4518 return (dram_esr_access(2, sp, asi, addr, is_load, store_val, legion_access));
4519}
4520
4521EAR_DEFINITION( dram_b3_esr ) {
4522 return (dram_esr_access(3, sp, asi, addr, is_load, store_val, legion_access));
4523}
4524
4525
4526uint64_t dram_esr_access (int bank, EAR_ARGS) {
4527 ss_proc_t *rpp;
4528 sparcv9_cpu_t *v9p;
4529 ss_strand_t *rsp;
4530 uint64_t reg;
4531 uint64_t val;
4532 mcu_bank_t *mbankp;
4533
4534 rpp = (ss_proc_t *)(sp->config_procp->procp);
4535 v9p = (sparcv9_cpu_t *)(sp->specificp);
4536 rsp = v9p->impl_specificp;
4537 mbankp = rpp->mbankp;
4538
4539
4540 reg = mbankp->error_status;
4541
4542 /*
4543 * dram_esr:
4544 * .-------------------------------------------------------------------------.
4545 * | MEU | MEC | DAC | DAU | DSC | DSU | DBU | MEB | FBU | FBR | RSVD | SYND |
4546 * `-------------------------------------------------------------------------'
4547 * 63 62 61 60 59 58 57 56 55 54 53:16 15:0
4548 * ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
4549 * | | | | | | | | | | | |
4550 * *-----*-----*-----*-----*-----*-----*-----*-----*-----* | *----> RW
4551 * | *-----------> RO
4552 * *-----------------------------------------------> R/W1C
4553 *
4554 */
4555
4556 if (is_load) {
4557DBGERRTRAP( lprintf(sp->gid, "ERROR_TRAP_GEN: access to dram_b%d_esr. returning val 0x%llx\n", bank, reg););
4558 return (reg);
4559 }
4560 /*
4561 * synchronize the read/modify/write
4562 */
4563 pthread_mutex_lock(&rpp->ss_err_state.err_lock);
4564
4565 val = store_val & MASK64(63,54);
4566 reg = reg & ~(val);
4567
4568 mbankp->error_status = reg;
4569
4570DBGERRTRAP( lprintf(sp->gid, "ERROR_TRAP_GEN: access to dram_b%d_esr. storing val 0x%llx\n", bank, reg););
4571
4572 pthread_mutex_unlock(&rpp->ss_err_state.err_lock);
4573
4574 return 0; /* ignored for store operations */
4575}
4576
4577EIR_DEFINITION( dram_b0_esr ) {
4578 return (dram_esr_inject(0, sp, mask, errp));
4579}
4580
4581EIR_DEFINITION( dram_b1_esr ) {
4582 return (dram_esr_inject(1, sp, mask, errp));
4583}
4584
4585EIR_DEFINITION( dram_b2_esr ) {
4586 return (dram_esr_inject(2, sp, mask, errp));
4587}
4588
4589EIR_DEFINITION( dram_b3_esr ) {
4590 return (dram_esr_inject(3, sp, mask, errp));
4591}
4592
4593
4594bool_t dram_esr_inject (int bank, EIR_ARGS) {
4595 ss_proc_t *rpp;
4596 sparcv9_cpu_t *v9p;
4597 ss_strand_t *rsp;
4598 uint64_t reg;
4599 uint64_t l2_esr_mask; /* error bits to be set in L2$ ESR */
4600 bool_t new_trap;
4601 mcu_bank_t *mbankp;
4602 int l2_bank;
4603 int err_name_len;
4604
4605 rpp = (ss_proc_t *)(sp->config_procp->procp);
4606 v9p = (sparcv9_cpu_t *)(sp->specificp);
4607 rsp = v9p->impl_specificp;
4608 mbankp = &(rpp->mbankp[bank]);
4609
4610 pthread_mutex_lock(&rpp->ss_err_state.err_lock);
4611
4612 reg = mbankp->error_status;
4613
4614#if (ERROR_TRAP_GEN > 1)
4615 lprintf(sp->gid, "ERROR_TRAP_GEN: injecting dram_b%d_esr. old value 0x%llx\n", bank, reg);
4616#endif
4617
4618 /*
4619 * See Register diagram in the register
4620 * access routine for dram_esr.
4621 *
4622 * Checking only for existing errors. See
4623 * N2 PRM Table 12-31.
4624 *
4625 */
4626
4627 switch (mask) {
4628 case DRAM_DAC_bit:
4629 if ((reg & DRAM_DSU_bit) | (reg & DRAM_DAU_bit) | (reg & DRAM_FBU_bit))
4630 reg |= DRAM_MEC_bit;
4631 else if ((reg & DRAM_DSC_bit) | (reg & DRAM_DAC_bit) | (reg & DRAM_FBR_bit))
4632 reg |= DRAM_MEC_bit;
4633 else /* existing error == DBU or no existing error */
4634 reg |= DRAM_DAC_bit;
4635 l2_esr_mask = BIT(42);
4636 break;
4637 case DRAM_DAU_bit:
4638 if ((reg & DRAM_DSU_bit) | (reg & DRAM_DAU_bit) | (reg & DRAM_FBU_bit))
4639 reg |= DRAM_MEU_bit;
4640 else /* existing error == (DBU | DSC | DAC | FBR) or no existing error */
4641 reg |= DRAM_DAU_bit;
4642 l2_esr_mask = BIT(41);
4643 break;
4644 case DRAM_DSC_bit:
4645 if ((reg & DRAM_DSU_bit) | (reg & DRAM_DAU_bit) | (reg & DRAM_FBU_bit))
4646 reg |= DRAM_MEC_bit;
4647 else if ((reg & DRAM_DSC_bit) | (reg & DRAM_DAC_bit) | (reg & DRAM_FBR_bit))
4648 reg |= DRAM_MEC_bit;
4649 else /* existing error == DBU or no existing error */
4650 reg |= DRAM_DSC_bit;
4651 l2_esr_mask = BIT(38);
4652 break;
4653 case DRAM_DSU_bit:
4654 if ((reg & DRAM_DSU_bit) | (reg & DRAM_DAU_bit) | (reg & DRAM_FBU_bit))
4655 reg |= DRAM_MEU_bit;
4656 else /* existing error == (DBU | DSC | DAC | FBR) or no existing error */
4657 reg |= DRAM_DSU_bit;
4658 l2_esr_mask = BIT(37);
4659 break;
4660 case DRAM_DBU_bit:
4661 if (reg & DRAM_DBU_bit)
4662 reg |= DRAM_MEB_bit;
4663 else /* existing error == (DSU | DAU | FBU | DSC | DAC | FBR) or no existing error */
4664 reg |= DRAM_DBU_bit;
4665 break;
4666 case DRAM_FBU_bit:
4667 if ((reg & DRAM_DSU_bit) | (reg & DRAM_DAU_bit) | (reg & DRAM_FBU_bit))
4668 reg |= DRAM_MEU_bit;
4669 else /* existing error == (DBU | DSC | DAC | FBR) or no existing error */
4670 reg |= DRAM_FBU_bit;
4671 break;
4672 case DRAM_FBR_bit:
4673 if ((reg & DRAM_DSU_bit) | (reg & DRAM_DAU_bit) | (reg & DRAM_FBU_bit))
4674 reg |= DRAM_MEC_bit;
4675 else if ((reg & DRAM_DSC_bit) | (reg & DRAM_DAC_bit) | (reg & DRAM_FBR_bit))
4676 reg |= DRAM_MEC_bit;
4677 else /* existing error == DBU or no existing error */
4678 reg |= DRAM_FBR_bit;
4679 break;
4680 default:
4681 EXEC_WARNING( ("Invalid dram_b%d_esr mask = 0x%llx \n", bank, mask) );
4682 }
4683
4684
4685#if (ERROR_TRAP_GEN > 1)
4686 lprintf(sp->gid, "ERROR_TRAP_GEN: injecting dram_b%d_esr. new value 0x%llx\n", bank, reg);
4687#endif
4688
4689 mbankp->error_status = reg;
4690
4691 /* The DRAM error info is also captured in the L2$ ESRs and ultimately
4692 * presented to the core as L2C error (for correctable errors). The l2_esr_inject
4693 * code will try to grab this lock so releasing it here.
4694 */
4695
4696 pthread_mutex_unlock(&rpp->ss_err_state.err_lock);
4697
4698 /* Mapping dram banks to the L2$ banks*/
4699 err_name_len = strlen(errp->error_name);
4700 l2_bank = *(errp->error_name + err_name_len -1) -'0';
4701
4702 l2_esr_inject(l2_bank, sp, l2_esr_mask, errp);
4703
4704 /*
4705 * The trap has already been posted as L2C error trap.
4706 * Hence setting new_trap to false
4707 */
4708 new_trap = false;
4709
4710 return (new_trap);
4711}
4712
4713#endif /* } ERROR_TRAP_GEN */
4714
4715bool_t n2_sp_interrupt(simcpu_t * sp, uint64_t intr_level, char * error_name) {
4716 FIXME_WARNING(("SP interrupts not supported on Niagara2\n" \
4717 "\terror name = %s, intr_level = %d\n",
4718 error_name, intr_level));
4719 return false;
4720}
4721
4722int no_niagara2_error_trap_gen;
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