* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: niagara2_err_trap.c
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* ========== Copyright Header End ============================================
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
#pragma ident "@(#)niagara2_err_trap.c 1.18 07/02/28 SMI"
#include <string.h> /* memcpy/memset */
#if ERROR_TRAP_GEN /* { */
/* Core error registers */
EAR_DEFINITION( c_erer
);
EAR_DEFINITION( s_eter
);
/* L2$ error registers */
EAR_DEFINITION( l2_b0_eer
);
EAR_DEFINITION( l2_b1_eer
);
EAR_DEFINITION( l2_b2_eer
);
EAR_DEFINITION( l2_b3_eer
);
EAR_DEFINITION( l2_b4_eer
);
EAR_DEFINITION( l2_b5_eer
);
EAR_DEFINITION( l2_b6_eer
);
EAR_DEFINITION( l2_b7_eer
);
EAR_DEFINITION( l2_b0_esr
);
EAR_DEFINITION( l2_b1_esr
);
EAR_DEFINITION( l2_b2_esr
);
EAR_DEFINITION( l2_b3_esr
);
EAR_DEFINITION( l2_b4_esr
);
EAR_DEFINITION( l2_b5_esr
);
EAR_DEFINITION( l2_b6_esr
);
EAR_DEFINITION( l2_b7_esr
);
EIR_DEFINITION( l2_b0_esr
);
EIR_DEFINITION( l2_b1_esr
);
EIR_DEFINITION( l2_b2_esr
);
EIR_DEFINITION( l2_b3_esr
);
EIR_DEFINITION( l2_b4_esr
);
EIR_DEFINITION( l2_b5_esr
);
EIR_DEFINITION( l2_b6_esr
);
EIR_DEFINITION( l2_b7_esr
);
EAR_DEFINITION( l2nd_b0_esr
);
EAR_DEFINITION( l2nd_b1_esr
);
EAR_DEFINITION( l2nd_b2_esr
);
EAR_DEFINITION( l2nd_b3_esr
);
EAR_DEFINITION( l2nd_b4_esr
);
EAR_DEFINITION( l2nd_b5_esr
);
EAR_DEFINITION( l2nd_b6_esr
);
EAR_DEFINITION( l2nd_b7_esr
);
EIR_DEFINITION( l2nd_b0_esr
);
EIR_DEFINITION( l2nd_b1_esr
);
EIR_DEFINITION( l2nd_b2_esr
);
EIR_DEFINITION( l2nd_b3_esr
);
EIR_DEFINITION( l2nd_b4_esr
);
EIR_DEFINITION( l2nd_b5_esr
);
EIR_DEFINITION( l2nd_b6_esr
);
EIR_DEFINITION( l2nd_b7_esr
);
/* DRAM error registers */
EAR_DEFINITION( dram_b0_esr
);
EAR_DEFINITION( dram_b1_esr
);
EAR_DEFINITION( dram_b2_esr
);
EAR_DEFINITION( dram_b3_esr
);
EAR_DEFINITION( dram_b4_esr
);
EAR_DEFINITION( dram_b5_esr
);
EAR_DEFINITION( dram_b6_esr
);
EAR_DEFINITION( dram_b7_esr
);
EIR_DEFINITION( dram_b0_esr
);
EIR_DEFINITION( dram_b1_esr
);
EIR_DEFINITION( dram_b2_esr
);
EIR_DEFINITION( dram_b3_esr
);
EIR_DEFINITION( dram_b4_esr
);
EIR_DEFINITION( dram_b5_esr
);
EIR_DEFINITION( dram_b6_esr
);
EIR_DEFINITION( dram_b7_esr
);
static bool_t
l2_esr_inject (int idx
, EIR_ARGS
);
static uint64_t l2_esr_access (int idx
, EAR_ARGS
);
static uint64_t l2_eer_access (int idx
, EAR_ARGS
);
static bool_t
l2nd_esr_inject (int idx
, EIR_ARGS
);
static uint64_t l2nd_esr_access (int idx
, EAR_ARGS
);
static bool_t
dram_esr_inject (int idx
, EIR_ARGS
);
static uint64_t dram_esr_access (int idx
, EAR_ARGS
);
* This routine will initilize all error trap
* related state which is associated with a
* particular ss_proc_t struct. For now just
* provides CPU error for generating traps which
* are not associated with any particular error.
void ss_error_trap_proc_init(config_proc_t
* config_procp
) {
* Table of Error Registers supported by Niagara2:
* For Starters, we are only supporting:
static ss_err_reg_t err_reg_table
[] = {
/* ASI VA Access Routine */
{ SS_ASI_IMMU
, 0x18, EAR( isfsr
) },
{ SS_ASI_DMMU
, 0x18, EAR( dsfsr
) },
{ N2_ASI_DESR
, 0x0, EAR( desr
) },
{ N2_ASI_DESR
, 0x20, EAR( clesr
) },
{ N2_ASI_DESR
, 0x8, EAR( dfesr
) },
/* ASI VA Access Routine */
{ N2_ASI_DESR
, 0x10, EAR( c_erer
) },
{ N2_ASI_DESR
, 0x18, EAR( s_eter
) },
/* ASI VA Access Routine */
{ INVALID_ASI
, 0, NULL
},
* CPU specific table of CPU errors for which Legion supports
* For Starters, we only supporting
static ss_error_entry_t error_table
[] = {
/* Error, Trap Type, Trap Class, persistent?, Target Strand */
{ "ICVP", SS_trap_hw_corrected_error
, DISRUPTING_TT
, true, TARGET_MYSELF
,
/* error_status[] */ { EAR( desr
), EIR( desr
), ( MASK64(56,56) | MASK64(2,2) ), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(18,18) },
/* error_report[] */ { EAR( s_eter
), MASK64(60,60) },
{ "ICTP", SS_trap_hw_corrected_error
, DISRUPTING_TT
, true, TARGET_MYSELF
,
/* error_status[] */ { EAR( desr
), EIR( desr
), ( MASK64(57,57) | MASK64(2,2) ), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(17,17) },
/* error_report[] */ { EAR( s_eter
), MASK64(60,60) },
{ "ICTM", SS_trap_hw_corrected_error
, DISRUPTING_TT
, true, TARGET_MYSELF
,
/* error_status[] */ { EAR( desr
), EIR( desr
), ( MASK64(57,56) | MASK64(2,2) ), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(16,16) },
/* error_report[] */ { EAR( s_eter
), MASK64(60,60) },
{ "ICDP", SS_trap_hw_corrected_error
, DISRUPTING_TT
, true, TARGET_MYSELF
,
/* error_status[] */ { EAR( desr
), EIR( desr
), ( MASK64(58,58) | MASK64(2,2) ), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(15,15) },
/* error_report[] */ { EAR( s_eter
), MASK64(60,60) },
{ "DCVP", SS_trap_hw_corrected_error
, DISRUPTING_TT
, true, TARGET_MYSELF
,
/* error_status[] */ {EAR( desr
), EIR( desr
), ( MASK64(58,58) | MASK64(56,56) | MASK64(2,2) | MASK64(0,0) ), DESR_MASK
},
/* error_record[] */ {EAR( c_erer
), MASK64(14,14)},
/* error_report[] */ {EAR( s_eter
), MASK64(60,60)},
{ "DCTP", SS_trap_hw_corrected_error
, DISRUPTING_TT
, true, TARGET_MYSELF
,
/* error_status[] */ { EAR( desr
), EIR( desr
), ( MASK64(58,57) | MASK64(2,2) | MASK64(0,0) ), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(13,13) },
/* error_report[] */ { EAR( s_eter
), MASK64(60,60) },
{ "DCTM", SS_trap_hw_corrected_error
, DISRUPTING_TT
, true, TARGET_MYSELF
,
/* error_status[] */ { EAR( desr
), EIR( desr
), ( MASK64(58,56) | MASK64(2,2) | MASK64(0,0) ), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(12,12) },
/* error_report[] */ { EAR( s_eter
), MASK64(60,60) },
{ "DCDP", SS_trap_hw_corrected_error
, DISRUPTING_TT
, true, TARGET_MYSELF
,
/* error_status[] */ { EAR( desr
), EIR( desr
), ( MASK64(59,59) | MASK64(2,2) | MASK64(0,0) ), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(11,11) },
/* error_report[] */ { EAR( s_eter
), MASK64(60,60) },
{ "L2C", SS_trap_hw_corrected_error
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* For now assigning it to current strand. Need set esr to ERRORSTEER */
/* error_status[] */ { EAR( desr
), EIR( desr
), ( MASK64(59,59) | MASK64(56,56) | MASK64(1,0) ), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(21,21) },
/* error_report[] */ { EAR( s_eter
), MASK64(60,60) },
{ "L2C_CE_ECC", SS_trap_sw_recoverable_error
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* For now assigning it to current strand. Need set esr to ERRORSTEER */
/* error_status[] */ { EAR( desr
), EIR( desr
), ( MASK64(60,60) | MASK64(58,58) | MASK64(1,0) ), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(21,21) },
/* error_report[] */ { EAR( s_eter
), MASK64(61,61) },
{ "SBDPC", SS_trap_hw_corrected_error
, DISRUPTING_TT
, true, TARGET_MYSELF
,
/* error_status[] */ { EAR( desr
), EIR( desr
), ( MASK64(59,59) | MASK64(57,57) | MASK64(1,0) ), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(10,10) },
/* error_report[] */ { EAR( s_eter
), MASK64(60,60) },
{ "SBDPU", SS_trap_sw_recoverable_error
, DISRUPTING_TT
, true, TARGET_MYSELF
,
/* error_status[] */ { EAR( desr
), EIR( desr
), MASK64(58,57) | MASK64(2,1), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(9,9) },
/* error_report[] */ { EAR( s_eter
), MASK64(61,61) },
{ "ITTM", SS_trap_instruction_access_MMU_error
, PRECISE_TT
, true, TARGET_MYSELF
,
/* error_status[] */ { EAR( isfsr
), EIR( isfsr
), MASK64(0,0), MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(61,61) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "ITTP", SS_trap_instruction_access_MMU_error
, PRECISE_TT
, true, TARGET_MYSELF
,
/* error_status[] */ { EAR( isfsr
), EIR( isfsr
), MASK64(1,1),MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(63,63) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "ITDP", SS_trap_instruction_access_MMU_error
, PRECISE_TT
, true, TARGET_MYSELF
,
/* error_status[] */ { EAR( isfsr
), EIR( isfsr
), MASK64(1,0), MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(62,62) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "ITMU", SS_trap_instruction_access_MMU_error
, PRECISE_TT
, true, TARGET_MYSELF
,
/* error_status[] */ { EAR( isfsr
), EIR( isfsr
), MASK64(2,2), MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(59,59) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "DTTM", SS_trap_data_access_MMU_error
, PRECISE_TT
, true, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(0,0), MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(47,47) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "DTTP", SS_trap_data_access_MMU_error
, PRECISE_TT
, true, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(1,1), MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(48,48) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "DTDP", SS_trap_data_access_MMU_error
, PRECISE_TT
, true, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(1,0), MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(46,46) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "DTMU", SS_trap_data_access_MMU_error
, PRECISE_TT
, true, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(2,2), MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(59,59) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "ITL2C", SS_trap_sw_recoverable_error
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* For now assigning it to current strand. Need set esr to ERRORSTEER */
/* error_status[] */ { EAR( desr
), EIR( desr
), MASK64(56,56), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(58,58) },
/* error_report[] */ { EAR( s_eter
), MASK64(61,61) },
{ "ICL2C", SS_trap_sw_recoverable_error
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* For now assigning it to current strand. Need set esr to ERRORSTEER */
/* error_status[] */ { EAR( desr
), EIR( desr
), MASK64(57,57), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(55,55) },
/* error_report[] */ { EAR( s_eter
), MASK64(61,61) },
{ "DTL2C", SS_trap_sw_recoverable_error
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* For now assigning it to current strand. Need set esr to ERRORSTEER */
/* error_status[] */ { EAR( desr
), EIR( desr
), MASK64(57,56), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(58,58) },
/* error_report[] */ { EAR( s_eter
), MASK64(61,61) },
{ "DCL2C", SS_trap_sw_recoverable_error
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* For now assigning it to current strand. Need set esr to ERRORSTEER */
/* error_status[] */ { EAR( desr
), EIR( desr
), MASK64(58,58), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(40,40) },
/* error_report[] */ { EAR( s_eter
), MASK64(61,61) },
{ "MAL2C", SS_trap_sw_recoverable_error
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* For now assigning it to current strand. Need to assign to the STRAND field of MA_CTL reg*/
/* error_status[] */ { EAR( desr
), EIR( desr
), MASK64(59,59), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(5,5) },
/* error_report[] */ { EAR( s_eter
), MASK64(61,61) },
{ "CWQL2C", SS_trap_sw_recoverable_error
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* For now assigning it to current strand. Need to assign to the CoreID field of the CWQ entry*/
/* error_status[] */ { EAR( desr
), EIR( desr
), MASK64(59,59)|MASK64(57,56), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(2,2) },
/* error_report[] */ { EAR( s_eter
), MASK64(61,61) },
{ "IRFU", SS_trap_internal_processor_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(0,0), MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(52,52) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "IRFC", SS_trap_internal_processor_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(1,1), MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(52,52) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "FRFU", SS_trap_internal_processor_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(1,0), MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(50,50) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "FRFC", SS_trap_internal_processor_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(2,2), MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(50,50) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "SBDLU", SS_trap_internal_processor_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(2,1), MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(36,36) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "SBDLC", SS_trap_internal_processor_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(2,2)|MASK64(0,0), MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(37,37) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "SCAC", SS_trap_internal_processor_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(3,3)|MASK64(1,1), MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(30,30) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "SCAU", SS_trap_internal_processor_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(3,3)|MASK64(1,0), MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(29,29) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "TCCP", SS_trap_internal_processor_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(3,2), MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(28,28) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "TCUP", SS_trap_internal_processor_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(3,2)|MASK64(0,0), MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(27,27) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "TCCD", SS_trap_sw_recoverable_error
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( desr
), EIR( desr
), MASK64(59,57), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(7,7) },
/* error_report[] */ { EAR( s_eter
), MASK64(61,61) },
{ "TCUD", SS_trap_sw_recoverable_error
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( desr
), EIR( desr
), MASK64(59,56), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(6,6) },
/* error_report[] */ { EAR( s_eter
), MASK64(61,61) },
{ "TSAC", SS_trap_internal_processor_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(3,3), MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(32,32) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "TSAU", SS_trap_internal_processor_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(3,3)|MASK64(0,0), MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(31,31) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "MRAU", SS_trap_internal_processor_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(2,0), MMU_SFSR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(33,33) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "SBDIOU", N2_trap_store_error
, DEFERRED_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dfesr
), EIR( dfesr
), MASK64(60,60), DFESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(9,9) },
/* error_report[] */ { NULL
, 0 },
{ "SBAPP", N2_trap_store_error
, DEFERRED_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dfesr
), EIR( dfesr
), MASK64(61,61), DFESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(23,23) },
/* error_report[] */ { NULL
, 0 },
{ "ITL2U", SS_trap_instruction_access_MMU_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( isfsr
), EIR( isfsr
), MASK64(2,2)|MASK64(0,0), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(58,58) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "DTL2U", SS_trap_data_access_MMU_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(2,2)|MASK64(0,0), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(58,58) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "ICL2U", SS_trap_instruction_access_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( isfsr
), EIR( isfsr
), MASK64(0,0), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(54,54) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "DCL2U", SS_trap_data_access_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(0,0), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(39,39) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "L2U", SS_trap_sw_recoverable_error
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( desr
), EIR( desr
), MASK64(60,60), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(20,20) },
/* error_report[] */ { EAR( s_eter
), MASK64(61,61) },
{ "L2U_PART_ST", SS_trap_sw_recoverable_error
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( desr
), EIR( desr
), MASK64(60,60), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(20,20) },
/* error_report[] */ { EAR( s_eter
), MASK64(60,60) },
{ "CWQL2U", SS_trap_sw_recoverable_error
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( desr
), EIR( desr
), MASK64(59,58), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(1,1) },
/* error_report[] */ { EAR( s_eter
), MASK64(61,61) },
{ "MAL2U", SS_trap_sw_recoverable_error
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( desr
), EIR( desr
), MASK64(59,59)|MASK64(56,56), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(4,4) },
/* error_report[] */ { EAR( s_eter
), MASK64(61,61) },
{ "ITL2ND", SS_trap_instruction_access_MMU_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( isfsr
), EIR( isfsr
), MASK64(2,1), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(58,58) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "DTL2ND", SS_trap_data_access_MMU_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(2,1), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(58,58) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "ICL2ND", SS_trap_instruction_access_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( isfsr
), EIR( isfsr
), MASK64(1,1), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(53,53) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "DCL2ND", SS_trap_data_access_error
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dsfsr
), EIR( dsfsr
), MASK64(1,1), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(38,38) },
/* error_report[] */ { EAR( s_eter
), MASK64(62,62) },
{ "L2ND", SS_trap_sw_recoverable_error
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( desr
), EIR( desr
), MASK64(60,60)|MASK64(56,56), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(19,19) },
/* error_report[] */ { EAR( s_eter
), MASK64(61,61) },
{ "CWQL2ND", SS_trap_sw_recoverable_error
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( desr
), EIR( desr
), MASK64(59,58)|MASK64(56,56), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(0,0) },
/* error_report[] */ { EAR( s_eter
), MASK64(61,61) },
{ "MAL2ND", SS_trap_sw_recoverable_error
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( desr
), EIR( desr
), MASK64(59,59)|MASK64(57,57), DESR_MASK
},
/* error_record[] */ { EAR( c_erer
), MASK64(3,3) },
/* error_report[] */ { EAR( s_eter
), MASK64(61,61) },
* L2$ Errors. These errors are not persistent because the framework doesn't have the required functionality for
* for these error. The functionality will be added if required in the future.
{ "LDWC_0", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(51,51), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "LDWC_1", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(51,51), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "LDWC_2", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(51,51), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "LDWC_3", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(51,51), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "LDWC_4", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(51,51), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "LDWC_5", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(51,51), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(0,0) },
{ "LDWC_6", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(51,51), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "LDWC_7", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(51,51), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
{ "LDSC_0", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(47,47), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "LDSC_1", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(47,47), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "LDSC_2", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(47,47), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "LDSC_3", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(47,47), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "LDSC_4", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(47,47), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "LDSC_5", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(47,47), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(0,0) },
{ "LDSC_6", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(47,47), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "LDSC_7", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(47,47), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
{ "LTC_0", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(45,45), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "LTC_1", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(45,45), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "LTC_2", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(45,45), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "LTC_3", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(45,45), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "LTC_4", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(45,45), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "LTC_5", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(45,45), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(0,0) },
{ "LTC_6", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(45,45), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "LTC_7", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(45,45), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
{ "LVC_0", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(34,34), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "LVC_1", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(34,34), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "LVC_2", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(34,34), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "LVC_3", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(34,34), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "LVC_4", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(34,34), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "LVC_5", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(34,34), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(0,0) },
{ "LVC_6", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(34,34), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "LVC_7", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(34,34), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
{ "ITL2C_0", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(53,53), NULL
, "ITL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "ITL2C_1", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(53,53), NULL
, "ITL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "ITL2C_2", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(53,53), NULL
, "ITL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "ITL2C_3", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(53,53), NULL
, "ITL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "ITL2C_4", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(53,53), NULL
, "ITL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "ITL2C_5", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(53,53), NULL
, "ITL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(0,0) },
{ "ITL2C_6", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(53,53), NULL
, "ITL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "ITL2C_7", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(53,53), NULL
, "ITL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
{ "ICL2C_0", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(53,53), NULL
, "ICL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "ICL2C_1", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(53,53), NULL
, "ICL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "ICL2C_2", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(53,53), NULL
, "ICL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "ICL2C_3", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(53,53), NULL
, "ICL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "ICL2C_4", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(53,53), NULL
, "ICL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "ICL2C_5", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(53,53), NULL
, "ICL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(0,0) },
{ "ICL2C_6", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(53,53), NULL
, "ICL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "ICL2C_7", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(53,53), NULL
, "ICL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
{ "DTL2C_0", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(53,53), NULL
, "DTL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "DTL2C_1", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(53,53), NULL
, "DTL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "DTL2C_2", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(53,53), NULL
, "DTL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "DTL2C_3", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(53,53), NULL
, "DTL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "DTL2C_4", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(53,53), NULL
, "DTL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "DTL2C_5", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(53,53), NULL
, "DTL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(0,0) },
{ "DTL2C_6", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(53,53), NULL
, "DTL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "DTL2C_7", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(53,53), NULL
, "DTL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
/* Load Hit DCL2C Errors */
{ "DCL2C_LD_0", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(53,53), NULL
, "DCL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "DCL2C_LD_1", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(53,53), NULL
, "DCL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "DCL2C_LD_2", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(53,53), NULL
, "DCL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "DCL2C_LD_3", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(53,53), NULL
, "DCL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "DCL2C_LD_4", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(53,53), NULL
, "DCL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "DCL2C_LD_5", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(53,53), NULL
, "DCL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(0,0) },
{ "DCL2C_LD_6", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(53,53), NULL
, "DCL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "DCL2C_LD_7", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(53,53), NULL
, "DCL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
/* Prefetch Hit Errors */
{ "L2C_PREFETCH_0", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(53,53), NULL
, "L2C_CE_ECC" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "L2C_PREFETCH_1", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(53,53), NULL
, "L2C_CE_ECC" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "L2C_PREFETCH_2", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(53,53), NULL
, "L2C_CE_ECC" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "L2C_PREFETCH_3", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(53,53), NULL
, "L2C_CE_ECC" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "L2C_PREFETCH_4", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(53,53), NULL
, "L2C_CE_ECC" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "L2C_PREFETCH_5", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(53,53), NULL
, "L2C_CE_ECC" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(0,0) },
{ "L2C_PREFETCH_6", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(53,53), NULL
, "L2C_CE_ECC" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "L2C_PREFETCH_7", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(53,53), NULL
, "L2C_CE_ECC" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
/* Partial Store Hit/CWQ Partial Store Hit DCL2C Errors */
{ "DCL2C_ST_0", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(53,53), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "DCL2C_ST_1", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(53,53), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "DCL2C_ST_2", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(53,53), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "DCL2C_ST_3", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(53,53), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "DCL2C_ST_4", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(53,53), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "DCL2C_ST_5", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(53,53), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "DCL2C_ST_6", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(53,53), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "DCL2C_ST_7", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(53,53), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
{ "MAL2C_0", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(53,53), NULL
, "MAL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "MAL2C_1", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(53,53), NULL
, "MAL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "MAL2C_2", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(53,53), NULL
, "MAL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "MAL2C_3", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(53,53), NULL
, "MAL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "MAL2C_4", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(53,53), NULL
, "MAL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "MAL2C_5", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(53,53), NULL
, "MAL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(0,0) },
{ "MAL2C_6", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(53,53), NULL
, "MAL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "MAL2C_7", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(53,53), NULL
, "MAL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
{ "CWQL2C_0", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(53,53), NULL
, "CWQL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "CWQL2C_1", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(53,53), NULL
, "CWQL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "CWQL2C_2", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(53,53), NULL
, "CWQL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "CWQL2C_3", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(53,53), NULL
, "CWQL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "CWQL2C_4", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(53,53), NULL
, "CWQL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "CWQL2C_5", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(53,53), NULL
, "CWQL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(0,0) },
{ "CWQL2C_6", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(53,53), NULL
, "CWQL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "CWQL2C_7", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(53,53), NULL
, "CWQL2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
{ "LDRC_DMA_RD_0", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(49,49), NULL
, "L2C_CE_ECC" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "LDRC_DMA_RD_1", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(49,49), NULL
, "L2C_CE_ECC" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "LDRC_DMA_RD_2", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(49,49), NULL
, "L2C_CE_ECC" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "LDRC_DMA_RD_3", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(49,49), NULL
, "L2C_CE_ECC" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "LDRC_DMA_RD_4", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(49,49), NULL
, "L2C_CE_ECC" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "LDRC_DMA_RD_5", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(49,49), NULL
, "L2C_CE_ECC" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(0,0) },
{ "LDRC_DMA_RD_6", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(49,49), NULL
, "L2C_CE_ECC" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "LDRC_DMA_RD_7", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(49,49), NULL
, "L2C_CE_ECC" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
{ "LDRC_DMA_PART_WR_0", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(49,49), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "LDRC_DMA_PART_WR_1", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(49,49), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "LDRC_DMA_PART_WR_2", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(49,49), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "LDRC_DMA_PART_WR_3", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(49,49), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "LDRC_DMA_PART_WR_4", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(49,49), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "LDRC_DMA_PART_WR_5", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(49,49), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(0,0) },
{ "LDRC_DMA_PART_WR_6", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(49,49), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "LDRC_DMA_PART_WR_7", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(49,49), NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
{ "ITL2U_0", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(52,52), NULL
, "ITL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(1,1) },
{ "ITL2U_1", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(52,52), NULL
, "ITL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(1,1) },
{ "ITL2U_2", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(52,52), NULL
, "ITL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(1,1) },
{ "ITL2U_3", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(52,52), NULL
, "ITL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(1,1) },
{ "ITL2U_4", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(52,52), NULL
, "ITL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(1,1) },
{ "ITL2U_5", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(52,52), NULL
, "ITL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(1,1) },
{ "ITL2U_6", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(52,52), NULL
, "ITL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(1,1) },
{ "ITL2U_7", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(52,52), NULL
, "ITL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(1,1) },
{ "DTL2U_0", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(52,52), NULL
, "DTL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(1,1) },
{ "DTL2U_1", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(52,52), NULL
, "DTL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(1,1) },
{ "DTL2U_2", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(52,52), NULL
, "DTL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(1,1) },
{ "DTL2U_3", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(52,52), NULL
, "DTL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(1,1) },
{ "DTL2U_4", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(52,52), NULL
, "DTL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(1,1) },
{ "DTL2U_5", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(52,52), NULL
, "DTL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(1,1) },
{ "DTL2U_6", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(52,52), NULL
, "DTL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(1,1) },
{ "DTL2U_7", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(52,52), NULL
, "DTL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(1,1) },
{ "ICL2U_0", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(52,52), NULL
, "ICL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(1,1) },
{ "ICL2U_1", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(52,52), NULL
, "ICL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(1,1) },
{ "ICL2U_2", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(52,52), NULL
, "ICL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(1,1) },
{ "ICL2U_3", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(52,52), NULL
, "ICL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(1,1) },
{ "ICL2U_4", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(52,52), NULL
, "ICL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(1,1) },
{ "ICL2U_5", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(52,52), NULL
, "ICL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(1,1) },
{ "ICL2U_6", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(52,52), NULL
, "ICL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(1,1) },
{ "ICL2U_7", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(52,52), NULL
, "ICL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(1,1) },
{ "DCL2U_0", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(52,52), NULL
, "DCL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(1,1) },
{ "DCL2U_1", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(52,52), NULL
, "DCL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(1,1) },
{ "DCL2U_2", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(52,52), NULL
, "DCL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(1,1) },
{ "DCL2U_3", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(52,52), NULL
, "DCL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(1,1) },
{ "DCL2U_4", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(52,52), NULL
, "DCL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(1,1) },
{ "DCL2U_5", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(52,52), NULL
, "DCL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(1,1) },
{ "DCL2U_6", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(52,52), NULL
, "DCL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(1,1) },
{ "DCL2U_7", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(52,52), NULL
, "DCL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(1,1) },
/* Prefetch Hit Errors */
{ "L2U_PREFETCH_0", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(52,52), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "L2U_PREFETCH_1", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(52,52), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "L2U_PREFETCH_2", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(52,52), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "L2U_PREFETCH_3", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(52,52), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "L2U_PREFETCH_4", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(52,52), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "L2U_PREFETCH_5", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(52,52), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(0,0) },
{ "L2U_PREFETCH_6", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(52,52), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "L2U_PREFETCH_7", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(52,52), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
/* Partial Store Hit/CWQ Partial Store Hit Errors */
{ "L2U_ST_0", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(52,52), NULL
, "L2U_PART_ST" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "L2U_ST_1", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(52,52), NULL
, "L2U_PART_ST" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "L2U_ST_2", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(52,52), NULL
, "L2U_PART_ST" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "L2U_ST_3", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(52,52), NULL
, "L2U_PART_ST" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "L2U_ST_4", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(52,52), NULL
, "L2U_PART_ST" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "L2U_ST_5", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(52,52), NULL
, "L2U_PART_ST" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "L2U_ST_6", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(52,52), NULL
, "L2U_PART_ST" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "L2U_ST_7", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(52,52), NULL
, "L2U_PART_ST" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
{ "CWQL2U_0", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(52,52), NULL
, "CWQL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "CWQL2U_1", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(52,52), NULL
, "CWQL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "CWQL2U_2", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(52,52), NULL
, "CWQL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "CWQL2U_3", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(52,52), NULL
, "CWQL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "CWQL2U_4", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(52,52), NULL
, "CWQL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "CWQL2U_5", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(52,52), NULL
, "CWQL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "CWQL2U_6", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(52,52), NULL
, "CWQL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "CWQL2U_7", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(52,52), NULL
, "CWQL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
{ "MAL2U_0", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(52,52), NULL
, "MAL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "MAL2U_1", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(52,52), NULL
, "MAL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "MAL2U_2", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(52,52), NULL
, "MAL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "MAL2U_3", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(52,52), NULL
, "MAL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "MAL2U_4", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(52,52), NULL
, "MAL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "MAL2U_5", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(52,52), NULL
, "MAL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "MAL2U_6", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(52,52), NULL
, "MAL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "MAL2U_7", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(52,52), NULL
, "MAL2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
{ "ITL2ND_0", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b0_esr
), EIR( l2nd_b0_esr
), MASK64(49,49), NULL
, "ITL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(1,1) },
{ "ITL2ND_1", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b1_esr
), EIR( l2nd_b1_esr
), MASK64(49,49), NULL
, "ITL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(1,1) },
{ "ITL2ND_2", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b2_esr
), EIR( l2nd_b2_esr
), MASK64(49,49), NULL
, "ITL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(1,1) },
{ "ITL2ND_3", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b3_esr
), EIR( l2nd_b3_esr
), MASK64(49,49), NULL
, "ITL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(1,1) },
{ "ITL2ND_4", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b4_esr
), EIR( l2nd_b4_esr
), MASK64(49,49), NULL
, "ITL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(1,1) },
{ "ITL2ND_5", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b5_esr
), EIR( l2nd_b5_esr
), MASK64(49,49), NULL
, "ITL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(1,1) },
{ "ITL2ND_6", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b6_esr
), EIR( l2nd_b6_esr
), MASK64(49,49), NULL
, "ITL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(1,1) },
{ "ITL2ND_7", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b7_esr
), EIR( l2nd_b7_esr
), MASK64(49,49), NULL
, "ITL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(1,1) },
{ "DTL2ND_0", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b0_esr
), EIR( l2nd_b0_esr
), MASK64(49,49), NULL
, "DTL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(1,1) },
{ "DTL2ND_1", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b1_esr
), EIR( l2nd_b1_esr
), MASK64(49,49), NULL
, "DTL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(1,1) },
{ "DTL2ND_2", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b2_esr
), EIR( l2nd_b2_esr
), MASK64(49,49), NULL
, "DTL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(1,1) },
{ "DTL2ND_3", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b3_esr
), EIR( l2nd_b3_esr
), MASK64(49,49), NULL
, "DTL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(1,1) },
{ "DTL2ND_4", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b4_esr
), EIR( l2nd_b4_esr
), MASK64(49,49), NULL
, "DTL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(1,1) },
{ "DTL2ND_5", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b5_esr
), EIR( l2nd_b5_esr
), MASK64(49,49), NULL
, "DTL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(1,1) },
{ "DTL2ND_6", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b6_esr
), EIR( l2nd_b6_esr
), MASK64(49,49), NULL
, "DTL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(1,1) },
{ "DTL2ND_0", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b0_esr
), EIR( l2nd_b0_esr
), MASK64(49,49), NULL
, "DTL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(1,1) },
{ "ICL2ND_0", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b0_esr
), EIR( l2nd_b0_esr
), MASK64(52,52), NULL
, "ICL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(1,1) },
{ "ICL2ND_1", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b1_esr
), EIR( l2nd_b1_esr
), MASK64(52,52), NULL
, "ICL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(1,1) },
{ "ICL2ND_2", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b2_esr
), EIR( l2nd_b2_esr
), MASK64(52,52), NULL
, "ICL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(1,1) },
{ "ICL2ND_3", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b3_esr
), EIR( l2nd_b3_esr
), MASK64(52,52), NULL
, "ICL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(1,1) },
{ "ICL2ND_4", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b4_esr
), EIR( l2nd_b4_esr
), MASK64(52,52), NULL
, "ICL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(1,1) },
{ "ICL2ND_5", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b5_esr
), EIR( l2nd_b5_esr
), MASK64(52,52), NULL
, "ICL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(1,1) },
{ "ICL2ND_6", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b6_esr
), EIR( l2nd_b6_esr
), MASK64(52,52), NULL
, "ICL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(1,1) },
{ "ICL2ND_7", SS_UE_trap_forward_2_core
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b7_esr
), EIR( l2nd_b7_esr
), MASK64(52,52), NULL
, "ICL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(1,1) },
{ "DCL2ND_0", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b0_esr
), EIR( l2nd_b0_esr
), MASK64(49,49), NULL
, "DCL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(1,1) },
{ "DCL2ND_1", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b1_esr
), EIR( l2nd_b1_esr
), MASK64(49,49), NULL
, "DCL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(1,1) },
{ "DCL2ND_2", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b2_esr
), EIR( l2nd_b2_esr
), MASK64(49,49), NULL
, "DCL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(1,1) },
{ "DCL2ND_3", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b3_esr
), EIR( l2nd_b3_esr
), MASK64(49,49), NULL
, "DCL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(1,1) },
{ "DCL2ND_4", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b4_esr
), EIR( l2nd_b4_esr
), MASK64(49,49), NULL
, "DCL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(1,1) },
{ "DCL2ND_5", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b5_esr
), EIR( l2nd_b5_esr
), MASK64(49,49), NULL
, "DCL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(1,1) },
{ "DCL2ND_6", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b6_esr
), EIR( l2nd_b6_esr
), MASK64(49,49), NULL
, "DCL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(1,1) },
{ "DCL2ND_7", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b7_esr
), EIR( l2nd_b7_esr
), MASK64(49,49), NULL
, "DCL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(1,1) },
{ "L2ND_PREFETCH_0", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b0_esr
), EIR( l2nd_b0_esr
), MASK64(49,49), NULL
, "L2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "L2ND_PREFETCH_1", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b1_esr
), EIR( l2nd_b1_esr
), MASK64(49,49), NULL
, "L2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "L2ND_PREFETCH_2", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b2_esr
), EIR( l2nd_b2_esr
), MASK64(49,49), NULL
, "L2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "L2ND_PREFETCH_3", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b3_esr
), EIR( l2nd_b3_esr
), MASK64(49,49), NULL
, "L2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "L2ND_PREFETCH_4", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b4_esr
), EIR( l2nd_b4_esr
), MASK64(49,49), NULL
, "L2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "L2ND_PREFETCH_5", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b5_esr
), EIR( l2nd_b5_esr
), MASK64(49,49), NULL
, "L2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(0,0) },
{ "L2ND_PREFETCH_6", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b6_esr
), EIR( l2nd_b6_esr
), MASK64(49,49), NULL
, "L2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "L2ND_PREFETCH_7", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b7_esr
), EIR( l2nd_b7_esr
), MASK64(49,49), NULL
, "L2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
{ "CWQL2ND_0", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b0_esr
), EIR( l2nd_b0_esr
), MASK64(49,49), NULL
, "CWQL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "CWQL2ND_1", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b1_esr
), EIR( l2nd_b1_esr
), MASK64(49,49), NULL
, "CWQL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "CWQL2ND_2", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b2_esr
), EIR( l2nd_b2_esr
), MASK64(49,49), NULL
, "CWQL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "CWQL2ND_3", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b3_esr
), EIR( l2nd_b3_esr
), MASK64(49,49), NULL
, "CWQL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "CWQL2ND_4", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b4_esr
), EIR( l2nd_b4_esr
), MASK64(49,49), NULL
, "CWQL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "CWQL2ND_5", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b5_esr
), EIR( l2nd_b5_esr
), MASK64(49,49), NULL
, "CWQL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(0,0) },
{ "CWQL2ND_6", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b6_esr
), EIR( l2nd_b6_esr
), MASK64(49,49), NULL
, "CWQL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "CWQL2ND_7", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b7_esr
), EIR( l2nd_b7_esr
), MASK64(49,49), NULL
, "CWQL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
{ "MAL2ND_0", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b0_esr
), EIR( l2nd_b0_esr
), MASK64(49,49), NULL
, "MAL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "MAL2ND_1", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b1_esr
), EIR( l2nd_b1_esr
), MASK64(49,49), NULL
, "MAL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "MAL2ND_2", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b2_esr
), EIR( l2nd_b2_esr
), MASK64(49,49), NULL
, "MAL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "MAL2ND_3", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b3_esr
), EIR( l2nd_b3_esr
), MASK64(49,49), NULL
, "MAL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "MAL2ND_4", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b4_esr
), EIR( l2nd_b4_esr
), MASK64(49,49), NULL
, "MAL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "MAL2ND_5", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b5_esr
), EIR( l2nd_b5_esr
), MASK64(49,49), NULL
, "MAL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b5_eer
), MASK64(0,0) },
{ "MAL2ND_6", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b6_esr
), EIR( l2nd_b6_esr
), MASK64(49,49), NULL
, "MAL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "MAL2ND_7", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2nd_b7_esr
), EIR( l2nd_b7_esr
), MASK64(49,49), NULL
, "MAL2ND" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
{ "LDWU_0", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(50,50), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "LDWU_1", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(50,50), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "LDWU_2", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(50,50), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "LDWU_3", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(50,50), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "LDWU_4", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(50,50), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "LDWU_5", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(50,50), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "LDWU_6", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(50,50), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "LDWU_7", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(50,50), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
{ "LDRU_0", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(48,48), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "LDRU_1", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(48,48), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "LDRU_2", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(48,48), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "LDRU_3", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(48,48), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "LDRU_4", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(48,48), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "LDRU_5", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(48,48), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "LDRU_6", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(48,48), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "LDRU_7", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(48,48), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
{ "LDSU_0", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b0_esr
), EIR( l2_b0_esr
), MASK64(46,46), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "LDSU_1", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b1_esr
), EIR( l2_b1_esr
), MASK64(46,46), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b1_eer
), MASK64(0,0) },
{ "LDSU_2", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b2_esr
), EIR( l2_b2_esr
), MASK64(46,46), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b2_eer
), MASK64(0,0) },
{ "LDSU_3", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b3_esr
), EIR( l2_b3_esr
), MASK64(46,46), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b3_eer
), MASK64(0,0) },
{ "LDSU_4", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b4_esr
), EIR( l2_b4_esr
), MASK64(46,46), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b4_eer
), MASK64(0,0) },
{ "LDSU_5", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b5_esr
), EIR( l2_b5_esr
), MASK64(46,46), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b0_eer
), MASK64(0,0) },
{ "LDSU_6", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b6_esr
), EIR( l2_b6_esr
), MASK64(46,46), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b6_eer
), MASK64(0,0) },
{ "LDSU_7", SS_UE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( l2_b7_esr
), EIR( l2_b7_esr
), MASK64(46,46), NULL
, "L2U" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { EAR( l2_b7_eer
), MASK64(0,0) },
{ "DAC_LD_FTCH_TTE_MISS_0_L2_0", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b0_esr
), EIR( dram_b0_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_LD_FTCH_TTE_MISS_0_L2_1", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b0_esr
), EIR( dram_b0_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_LD_FTCH_TTE_MISS_1_L2_2", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b0_esr
), EIR( dram_b0_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_LD_FTCH_TTE_MISS_1_L2_3", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b0_esr
), EIR( dram_b0_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_LD_FTCH_TTE_MISS_2_L2_4", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b2_esr
), EIR( dram_b2_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_LD_FTCH_TTE_MISS_2_L2_5", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b2_esr
), EIR( dram_b2_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_LD_FTCH_TTE_MISS_3_L2_6", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b3_esr
), EIR( dram_b3_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_LD_FTCH_TTE_MISS_3_L2_7", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b3_esr
), EIR( dram_b3_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_ATOMIC_MISS_0_L2_0", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b0_esr
), EIR( dram_b0_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_ATOMIC_MISS_0_L2_1", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b0_esr
), EIR( dram_b0_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_ATOMIC_MISS_1_L2_2", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b1_esr
), EIR( dram_b1_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_ATOMIC_MISS_1_L2_3", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b1_esr
), EIR( dram_b1_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_ATOMIC_MISS_2_L2_4", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b2_esr
), EIR( dram_b2_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_ATOMIC_MISS_2_L2_5", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b2_esr
), EIR( dram_b2_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_ATOMIC_MISS_3_L2_6", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b3_esr
), EIR( dram_b3_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_ATOMIC_MISS_3_L2_7", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b3_esr
), EIR( dram_b3_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
/* Partial Store Miss / CWQ Partial Store Miss */
{ "DAC_PART_STX_MISS_0_L2_0", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b0_esr
), EIR( dram_b0_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_PART_STX_MISS_0_L2_1", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b0_esr
), EIR( dram_b0_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_PART_STX_MISS_1_L2_2", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b1_esr
), EIR( dram_b1_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_PART_STX_MISS_1_L2_3", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b1_esr
), EIR( dram_b1_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_PART_STX_MISS_2_L2_4", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b2_esr
), EIR( dram_b2_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_PART_STX_MISS_2_L2_5", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b2_esr
), EIR( dram_b2_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_PART_STX_MISS_3_L2_6", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b3_esr
), EIR( dram_b3_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_PART_STX_MISS_3_L2_7", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b3_esr
), EIR( dram_b3_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
/* Store Miss / Modular Arithmetic Store Miss/ CWQ Store Miss */
{ "DAC_STX_MISS_0_L2_0", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b0_esr
), EIR( dram_b0_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_STX_MISS_0_L2_1", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b0_esr
), EIR( dram_b0_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_STX_MISS_1_L2_2", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b1_esr
), EIR( dram_b1_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_STX_MISS_1_L2_3", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b1_esr
), EIR( dram_b1_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_STX_MISS_2_L2_4", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b2_esr
), EIR( dram_b2_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_STX_MISS_2_L2_5", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b2_esr
), EIR( dram_b2_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_STX_MISS_3_L2_6", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b3_esr
), EIR( dram_b3_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DAC_STX_MISS_3_L2_7", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b3_esr
), EIR( dram_b3_esr
), DRAM_DAC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DSC_0_L2_0", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b0_esr
), EIR( dram_b0_esr
), DRAM_DSC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DSC_0_L2_1", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b0_esr
), EIR( dram_b0_esr
), DRAM_DSC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DSC_1_L2_2", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b1_esr
), EIR( dram_b1_esr
), DRAM_DSC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DSC_1_L2_3", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b1_esr
), EIR( dram_b1_esr
), DRAM_DSC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DSC_2_L2_4", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b2_esr
), EIR( dram_b2_esr
), DRAM_DSC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DSC_2_L2_5", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b2_esr
), EIR( dram_b2_esr
), DRAM_DSC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DSC_3_L2_6", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b3_esr
), EIR( dram_b3_esr
), DRAM_DSC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
{ "DSC_3_L2_7", SS_CE_trap_forward_2_core
, DISRUPTING_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { EAR( dram_b3_esr
), EIR( dram_b3_esr
), DRAM_DSC_bit
, NULL
, "L2C" },
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
* Special case for generating traps which are not associated
* with any particular error.
{ TRAP_ERR_STRING
, TRAP_ONLY_TT
, PRECISE_TT
, false, TARGET_MYSELF
,
/* error_status[] */ { NULL
, NULL
, 0, NULL
},
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
* Special case for generating service processor interrupts
* which are not associated with any particular error.
{ SP_INTR_ERR_STRING
, SS_generate_SP_interrupt
, SP_INTR
, false, TARGET_SP
,
/* error_status */ { NULL
, NULL
, 0, NULL
},
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
* Special case for marking the end of the table.
{ END_ERR_STRING
, INVALID_TRAP
, 0, 0, 0,
/* error_status */ { NULL
, NULL
, 0, NULL
},
/* error_record[] */ { NULL
, 0 },
/* error_report[] */ { NULL
, 0 },
* CPU specific table of CPU errors for which Legion supports
* SP interrupt generation
static ss_sp_error_t sp_error_table
[] = {
{ SP_INTR_ERR_STRING
, NULL
},
{ END_ERR_STRING
, NULL
},
cpu_error_state_t
*cpu_es
; rpp
= (ss_proc_t
*)(config_procp
->procp
); rpp
->ss_err_state
.inj_error_trap
= NULL
; rpp
->ss_err_state
.ready_for_next_injection
= true; rpp
->ss_err_state
.esrs_clear
= true; lprintf(-1, "\n\nERROR_TRAP_GEN: ss_proc_t.ss_err_state = 0x%llx\n", &rpp
->ss_err_state
);
lprintf(-1, " &(...inj_error_trap) = 0x%llx\n", &(rpp
->ss_err_state
.inj_error_trap
));
lprintf(-1, " &(...ready_for_next_injection) = 0x%llx\n", &(rpp
->ss_err_state
.ready_for_next_injection
));
lprintf(-1, " &(...esrs_clear) = 0x%llx\n", &(rpp
->ss_err_state
.esrs_clear
));
lprintf(-1, " &(...err_lock) = 0x%llx\n\n", &(rpp
->ss_err_state
.err_lock
));
* Allocate space for and initialize the
* CPU-specific Error Trap Injection state.
cpu_es
= Xcalloc(1, cpu_error_state_t
); rpp
->cpu_err_statep
= cpu_es
; rpp
->ss_err_state
.err_reg_tbl
= err_reg_table
; rpp
->ss_err_state
.err_event_tbl
= error_table
; rpp
->ss_err_state
.sp_err_tbl
= sp_error_table
; lprintf(-1, "ERROR_TRAP_GEN: ss_proc_t->cpu_err_statep = 0x%llx\n", rpp
->cpu_err_statep
);
lprintf(-1, " &(...->desr[0]) = 0x%llx\n", &(rpp
->cpu_err_statep
->desr
[0]));
lprintf(-1, " &(...->c_erer[0]) = 0x%llx\n", &(rpp
->cpu_err_statep
->c_erer
[0]));
lprintf(-1, " &(...->s_eter) = 0x%llx\n", &(rpp
->cpu_err_statep
->s_eter
));
lprintf(-1, " &(...->dfesr[0]) = 0x%llx\n", &(rpp
->cpu_err_statep
->dfesr
[0]));
lprintf(-1, "\nERROR_TRAP_GEN: CPU Error Table\n");
dump_cpu_error_table(-1, error_table
);
lprintf(-1, "ERROR_TRAP_GEN: END CPU Error Table\n\n");
lprintf(-1, "ERROR_TRAP_GEN: Supported CPU Error Register Table\n");
dump_cpu_error_reg_table(-1, err_reg_table
);
lprintf(-1, "ERROR_TRAP_GEN: END Supported CPU Error Register Table\n\n");
lprintf(-1, "ERROR_TRAP_GEN: initial Error Event list:\n");
dump_error_event_list(-1, rpp
->ss_err_state
.error_event_list_rootp
);
lprintf(-1, "ERROR_TRAP_GEN: END initial Error Event list:\n\n");
lprintf(-1, "ERROR_TRAP_GEN: initial Error ASI Override list\n");
dump_error_asi_list(-1, rpp
->ss_err_state
.error_asi_list_rootp
);
lprintf(-1, "ERROR_TRAP_GEN: END Error ASI Override list\n\n");
pthread_mutex_init(&rpp
->ss_err_state
.injection_lock
, NULL
);
pthread_mutex_init(&rpp
->ss_err_state
.err_lock
, NULL
);
void ss_error_trap_strand_init(config_proc_t
* config_procp
, simcpu_t
* sp
) {
cpu_error_state_t
*cpu_es
; v9p
= (sparcv9_cpu_t
*)(sp
->specificp
); rsp
= v9p
->impl_specificp
; rpp
= (ss_proc_t
*)(config_procp
->procp
); cpu_es
= rpp
->cpu_err_statep
; * Allocate space for and initialize the
* per strand access pointers. This struct
* simply defines direct pointers from the
* strand to the various register values
* stored in the chip's cpu_error_state_t
strand_id
= rsp
->vcore_id
; cpu_er
= Xcalloc(1, cpu_error_reg_t
); cpu_er
->desr_ptr
= &(cpu_es
->desr
[strand_id
]); cpu_er
->clesr_ptr
= &(cpu_es
->clesr
[core_num
]); cpu_er
->c_erer_ptr
= &(cpu_es
->c_erer
[core_num
]); cpu_er
->s_eter_ptr
= &(cpu_es
->s_eter
[strand_id
]); cpu_er
->dfesr_ptr
= &(cpu_es
->dfesr
[strand_id
]); rsp
->cpu_err_regp
= cpu_er
; lprintf(sp
->gid
, "ERROR_TRAP_GEN: For Strand ID = %d we have initialized:\n", strand_id
);
lprintf(sp
->gid
, " ss_strand_t->cpu_err_regp = 0x%llx\n", rsp
->cpu_err_regp
);
lprintf(sp
->gid
, " rsp->cpu_err_regp->desr_ptr = 0x%llx\n", rsp
->cpu_err_regp
->desr_ptr
);
lprintf(sp
->gid
, " rsp->cpu_err_regp->c_erer_ptr = 0x%llx core_num=%d\n",
rsp
->cpu_err_regp
->c_erer_ptr
, core_num
); lprintf(sp
->gid
, " rsp->cpu_err_regp->s_eter_ptr = 0x%llx\n", rsp
->cpu_err_regp
->s_eter_ptr
);
lprintf(sp
->gid
, " rsp->error.isfsr = 0x%llx\n", &(rsp
->error
.isfsr
));
lprintf(sp
->gid
, " rsp->error.dsfsr = 0x%llx\n", &(rsp
->error
.dsfsr
));
lprintf(sp
->gid
, " rsp->error.dsfar = 0x%llx\n\n", &(rsp
->error
.dsfar
));
lprintf(sp
->gid
, " rsp->cpu_err_regp->dfesr_ptr = 0x%llx\n", rsp
->cpu_err_regp
->dfesr_ptr
);
* See if there are any other events which may need to
* be triggered on this CPU.
check_pending_error_events(sp
);
* This is a read only register. Much like the
* HW implementation, we don't store any state
* associated with this register. When there is
* an access to this register, we simply go read
* all the F bits of the other ESRs which are
* latched to bits in this register and return
EAR_DEFINITION( clesr
) {
int strand_id
, core_num
, strand
;
rpp
= (ss_proc_t
*)(sp
->config_procp
->procp
); v9p
= (sparcv9_cpu_t
*)(sp
->specificp
); rsp
= v9p
->impl_specificp
; strand_id
= rsp
->vcore_id
; cesp
= rpp
->cpu_err_statep
; * Not expected. I'm not sure if we should
* generate a DAX at this point or not. For
* now a warning message will do.
EXEC_WARNING(("ASI_CLESR is not writeble.\n"));
/* Core_num/strand0 desr */
if (cesp
->desr
[strand
] & MASK64(63,63))
/* Core_num/strand1 desr */
if (cesp
->desr
[strand
+ 1] & MASK64(63,63))
/* Core_num/strand2 desr */
if (cesp
->desr
[strand
+ 2] & MASK64(63,63))
/* Core_num/strand3 desr */
if (cesp
->desr
[strand
+ 3] & MASK64(63,63))
/* Core_num/strand4 desr */
if (cesp
->desr
[strand
+ 4] & MASK64(63,63))
/* Core_num/strand5 desr */
if (cesp
->desr
[strand
+ 5] & MASK64(63,63))
/* Core_num/strand6 desr */
if (cesp
->desr
[strand
+ 6] & MASK64(63,63))
/* Core_num/strand7 desr */
if (cesp
->desr
[strand
+ 7] & MASK64(63,63))
DBGERRTRAP( lprintf(sp
->gid
, "ERROR_TRAP_GEN: access to clesr. returning val 0x%llx\n", val
););
* One register per strand
* but we define one access routine.
* Use sp to identify register being
EAR_DEFINITION( isfsr
) {
rpp
= (ss_proc_t
*)(sp
->config_procp
->procp
); v9p
= (sparcv9_cpu_t
*)(sp
->specificp
); rsp
= v9p
->impl_specificp
; * We are only interested in the register
* associated with the strand in question.
* .----------------------------------------.
* | R E S E R V E D | ERRTYPE |
* `----------------------------------------'
* *-----------------------> RO
DBGERRTRAP( lprintf(sp
->gid
, "ERROR_TRAP_GEN: access to isfsr. returning val 0x%llx\n", val
););
* synchronize the read/modify/write
pthread_mutex_lock(&rpp
->ss_err_state
.err_lock
);
val
= store_val
& MMU_SFSR_MASK
;DBGERRTRAP( lprintf(sp
->gid
, "ERROR_TRAP_GEN: access to isfsr. storing val 0x%llx\n", rsp
->error
.isfsr
););
pthread_mutex_unlock(&rpp
->ss_err_state
.err_lock
);
return 0; /* ignored for store operations */
* One register per strand.
* but we define one access routine.
* Use sp to identify register for
EIR_DEFINITION( isfsr
) {
rpp
= (ss_proc_t
*)(sp
->config_procp
->procp
); v9p
= (sparcv9_cpu_t
*)(sp
->specificp
); rsp
= v9p
->impl_specificp
; pthread_mutex_lock(&rpp
->ss_err_state
.err_lock
);
* We are only interested in the register
* associated with the strand in question.
lprintf(sp
->gid
, "ERROR_TRAP_GEN: injecting isfsr. old value 0x%llx\n", val
);
* See Register diagram in the register
* access routine for isfsr.
* There is no latching of the first error. If another
* error occurs before the ISFSR has been examined, the
* new error information is captured in the ISFSR, overwriting
* Inject the ESR bit(s) specified
v9p
->tpc
[(v9p
->tl
)] = sp
->eep
->address
.addr
; lprintf(sp
->gid
, "ERROR_TRAP_GEN: injecting isfsr. new value 0x%llx\n", rsp
->error
.isfsr
);
pthread_mutex_unlock(&rpp
->ss_err_state
.err_lock
);
* One register per strand
* but we define one access routine.
* Use sp to identify register being
EAR_DEFINITION( dsfsr
) {
rpp
= (ss_proc_t
*)(sp
->config_procp
->procp
); v9p
= (sparcv9_cpu_t
*)(sp
->specificp
); rsp
= v9p
->impl_specificp
; * We are only interested in the register
* associated with the strand in question.
* .----------------------------------------.
* | R E S E R V E D | ERRTYPE |
* `----------------------------------------'
* *-----------------------> RO
DBGERRTRAP( lprintf(sp
->gid
, "ERROR_TRAP_GEN: access to dsfsr. returning val 0x%llx\n", val
););
* synchronize the read/modify/write
pthread_mutex_lock(&rpp
->ss_err_state
.err_lock
);
val
= store_val
& MMU_SFSR_MASK
;DBGERRTRAP( lprintf(sp
->gid
, "ERROR_TRAP_GEN: access to dsfsr. storing val 0x%llx\n", val
););
pthread_mutex_unlock(&rpp
->ss_err_state
.err_lock
);
return 0; /* ignored for store operations */
* One register per strand.
* but we define one access routine.
* Use sp to identify register for
EIR_DEFINITION( dsfsr
) {
rpp
= (ss_proc_t
*)(sp
->config_procp
->procp
); v9p
= (sparcv9_cpu_t
*)(sp
->specificp
); rsp
= v9p
->impl_specificp
; pthread_mutex_lock(&rpp
->ss_err_state
.err_lock
);
* We are only interested in the register
* associated with the strand in question.
lprintf(sp
->gid
, "ERROR_TRAP_GEN: injecting dsfsr. old value 0x%llx\n", val
);
* See Register diagram in the register
* access routine for dsfsr.
* There is no latching of the first error. If another
* error occurs before the DSFSR has been examined, the
* new error information is captured in the DSFSR, overwriting
* Inject the ESR bit(s) specified
rsp
->error
.dsfar
= sp
->eep
->address
.addr
& MASK64(47,0); lprintf(sp
->gid
, "ERROR_TRAP_GEN: injecting dsfsr. new value 0x%llx\n", rsp
->error
.dsfsr
);
lprintf(sp
->gid
, "ERROR_TRAP_GEN: injecting dsfar. new value 0x%llx\n", rsp
->error
.dsfar
);
pthread_mutex_unlock(&rpp
->ss_err_state
.err_lock
);
* One register per strand
* but we define one access routine.
* Use sp to identify register being
rpp
= (ss_proc_t
*)(sp
->config_procp
->procp
); v9p
= (sparcv9_cpu_t
*)(sp
->specificp
); rsp
= v9p
->impl_specificp
; * We are only interested in the register
* associated with the strand in question.
regp
= rsp
->cpu_err_regp
->desr_ptr
; * .----------------------------------------.
* | F | ME | S | ERRTYPE | RSVD | ERRADDR |
* `----------------------------------------'
* 63 62 61 60:56 55:11 10:0
* | | | | *------------> RC
* | | | *--------------------> RC
* | | *---------------------------> RC
* | *---------------------------------> RC
* *-------------------------------------> RC
DBGERRTRAP( lprintf(sp
->gid
, "ERROR_TRAP_GEN: access to desr. returning val 0x%llx\n", *regp
););
/* Most of the fields of this register are clear on read when accessed by HV.
* legion_access flag is used to prevent clearing this reg when legion accesses it.
if (!legion_access
) /* HV Access */
*regp
= 0; /* Clear all fields on read */
/* The ASI_DESR is clear on read, a store is not expected */
EXEC_WARNING(("ASI_DESR is not writeble.\n"));
* One register per strand.
* but we define one access routine.
* Use sp to identify register for
rpp
= (ss_proc_t
*)(sp
->config_procp
->procp
); v9p
= (sparcv9_cpu_t
*)(sp
->specificp
); rsp
= v9p
->impl_specificp
; pthread_mutex_lock(&rpp
->ss_err_state
.err_lock
);
* We are only interested in the register
* associated with the strand in question.
val
= *(rsp
->cpu_err_regp
->desr_ptr
); lprintf(sp
->gid
, "ERROR_TRAP_GEN: injecting desr. old value 0x%llx\n", val
);
* See Register diagram in the register
* access routine for desr.
if (errp
->trap_type
== SS_trap_sw_recoverable_error
) {
if (val
& MASK64(63,63)) { /* Checking the F bit */
if (val
& MASK64(61,61)) { /* Checking the S bit */
val
|= MASK64(62,62); /* Only turn on the ME bit */ val
|= mask
; /* Update DESR.Errortype field */ val
|= MASK64(63,61); /* Turn on F, Me & S bits */ } else { /* F bit is turned off */
val
|= mask
; /* Update DESR.Errortype field */ val
|= (MASK64(63,63)|MASK64(61,61)); /* Turn on F & S bits */ /*Modify the additional bits if its CWQL2U/MAL2U error*/
if (strcmp(sp
->eep
->error_str
, "CWQL2U") == 0) {
rpp
->stream_cwq_p
->cwq_CSR
& CWQ_CSR_HWE
& ~CWQ_CSR_BUSY
& ~CWQ_CSR_ENABLED
; } else if (strcmp(sp
->eep
->error_str
, "MAL2U") == 0) {
rpp
->mod_arith_p
->HWE
= 1; rpp
->mod_arith_p
->busy
= 0; } else if (errp
->trap_type
== SS_trap_hw_corrected_error
) {
if (val
& MASK64(63,63)) {
* Only turn on the ME bit.
* Inject the ESR bit(s) specified
if (val
& MASK64(60,56)) {
/* make sure F bit is on */
*(rsp
->cpu_err_regp
->desr_ptr
) = val
;
lprintf(sp
->gid
, "ERROR_TRAP_GEN: injecting desr. new value 0x%llx\n", val
);
pthread_mutex_unlock(&rpp
->ss_err_state
.err_lock
);
/* One register per strand
* but we define one access routine.
* Use sp to identify register being
EAR_DEFINITION( dfesr
) {
rpp
= (ss_proc_t
*)(sp
->config_procp
->procp
); v9p
= (sparcv9_cpu_t
*)(sp
->specificp
); rsp
= v9p
->impl_specificp
; * We are only interested in the register
* associated with the strand in question.
regp
= rsp
->cpu_err_regp
->dfesr_ptr
; * .----------------------------------------.
* | RSVD | TYPE | PRIV | STBIDX | RESERVED |
* `----------------------------------------'
* 63:62 61:60 59:58 57:55 54:0
* | | | *--------------> RC
* | | *---------------------> RC
* | *-----------------------------> RC
* *------------------------------------> RC
DBGERRTRAP( lprintf(sp
->gid
, "ERROR_TRAP_GEN: access to dfesr. returning val 0x%llx\n", *regp
););
/* All the fields of this register are cleared on read when accessed by HV.
* legion_access flag is used to prevent clearing this reg when legion accesses it.
if (!legion_access
) /* HV Access */
*regp
= 0; /* Clear all fields on read */
/* The ASI_DESR is clear on read, a store is not expected */
EXEC_WARNING(("ASI_DESR (DFESR) is not writeble.\n"));
* One register per strand.
* but we define one access routine.
* Use sp to identify register for
EIR_DEFINITION( dfesr
) {
rpp
= (ss_proc_t
*)(sp
->config_procp
->procp
); v9p
= (sparcv9_cpu_t
*)(sp
->specificp
); rsp
= v9p
->impl_specificp
; pthread_mutex_lock(&rpp
->ss_err_state
.err_lock
);
* We are only interested in the register
* associated with the strand in question.
val
= *(rsp
->cpu_err_regp
->dfesr_ptr
); lprintf(sp
->gid
, "ERROR_TRAP_GEN: injecting dfesr. old value 0x%llx\n", val
);
/*Setting the priv level of this error as specified in error.conf*/
lprintf(sp
->gid
, "ERROR_TRAP_GEN: %s priv level = USER\n", sp
->eep
->error_str
);
lprintf(sp
->gid
, "ERROR_TRAP_GEN: %s priv level = PRIVILEDGED\n", sp
->eep
->error_str
);
lprintf(sp
->gid
, "ERROR_TRAP_GEN: %s priv level = HYPERPRIVILEDGED\n", sp
->eep
->error_str
);
lprintf(sp
->gid
, "ERROR_TRAP_GEN: No priv level specified for %s, defaulting to PRIVILEDGED\n", sp
->eep
->error_str
);
*(rsp
->cpu_err_regp
->dfesr_ptr
) = val
;
lprintf(sp
->gid
, "ERROR_TRAP_GEN: injecting dfesr. new value 0x%llx\n", val
);
pthread_mutex_unlock(&rpp
->ss_err_state
.err_lock
);
* One register per core. (8 total)
* but we define one access routine.
* Use sp to identify register being
EAR_DEFINITION( c_erer
) {
rpp
= (ss_proc_t
*)(sp
->config_procp
->procp
); v9p
= (sparcv9_cpu_t
*)(sp
->specificp
); rsp
= v9p
->impl_specificp
; * We are only interested in the register
* associated with the strand in question.
regp
= rsp
->cpu_err_regp
->c_erer_ptr
;DBGERRTRAP( lprintf(sp
->gid
, "ERROR_TRAP_GEN: access to c_erer. returning val 0x%llx\n", *regp
););
val
= store_val
& CERER_MASK
;DBGERRTRAP( lprintf(sp
->gid
, "ERROR_TRAP_GEN: access to c_erer. storing val 0x%llx\n", *regp
););
return 0; /* ignored for store operations */
* One register per strand.
EAR_DEFINITION( s_eter
) {
ss_error_entry_t
*error_table
; rpp
= (ss_proc_t
*)(sp
->config_procp
->procp
); v9p
= (sparcv9_cpu_t
*)(sp
->specificp
); rsp
= v9p
->impl_specificp
; error_table
= rpp
->ss_err_state
.err_event_tbl
; regp
= rsp
->cpu_err_regp
->s_eter_ptr
; * .---------------------------------------------.
* | RSVD | PSCCE | DE | DHCCE | RSVD |
* `---------------------------------------------'
* | | | *---------------> R/W
* | | *---------------------> R/W
* | *----------------------------> R/W
* *------------------------------------> R
DBGERRTRAP( lprintf(sp
->gid
, "ERROR_TRAP_GEN: access to s_eter. returning val 0x%llx\n", *regp
););
pthread_mutex_lock(&rpp
->ss_err_state
.err_lock
);
val
= store_val
& MASK64(62,60); * Get new StrandID value for disrupting traps
* Update the trap target StrandID value for
* all disrupting traps in our global error
for (idx
=0; error_table
[idx
].trap_type
!= INVALID_TRAP
; idx
++) {
if (error_table
[idx
].trap_class
== DISRUPTING_TT
) {
error_table
[idx
].trap_target
= val
; lprintf(sp
->gid
, "ERROR_TRAP_GEN: access to s_eter. storing val 0x%llx\n", *regp
);
lprintf(sp
->gid
, "ERROR_TRAP_GEN: access to s_eter: Updated all disrupting trap targets to CPU 0x%x\n", val
);
lprintf(sp
->gid
, "ERROR_TRAP_GEN: Updated CPU Error Table\n");
dump_cpu_error_table(sp
->gid
, error_table
);
lprintf(sp
->gid
, "ERROR_TRAP_GEN: END Updated CPU Error Table\n\n");
pthread_mutex_unlock(&rpp
->ss_err_state
.err_lock
);
return 0; /* ignored for store operations */
* One register per l2$ bank (8 total)
* we define separate access routines.
EAR_DEFINITION( l2_b0_esr
) {
return (l2_esr_access(0, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2_b1_esr
) {
return (l2_esr_access(1, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2_b2_esr
) {
return (l2_esr_access(2, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2_b3_esr
) {
return (l2_esr_access(3, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2_b4_esr
) {
return (l2_esr_access(4, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2_b5_esr
) {
return (l2_esr_access(5, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2_b6_esr
) {
return (l2_esr_access(6, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2_b7_esr
) {
return (l2_esr_access(7, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
uint64_t l2_esr_access (int bank
, EAR_ARGS
) {
rpp
= (ss_proc_t
*)(sp
->config_procp
->procp
); v9p
= (sparcv9_cpu_t
*)(sp
->specificp
); rsp
= v9p
->impl_specificp
; reg
= l2p
->error_status
[bank
]; * .--------------------------------------------------------------.
* |MEU|MEC|RW|MODA| VCID |LDAC|LDAU|LDWC|LDWU|LDRC|LDRU|LDSC|LDSU|
* `--------------------------------------------------------------'
* 63 62 61 60 59:54 53 52 51 50 49 48 47 46
* ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
* | | | | | | | | | | | | |
* | | | | | *----*----*----*----*----*----*----*
* | | | | | *--------------------> R/W1C
* | | | | *-----------------------------------------> RW
* | | | *-----------------------------------------------> RW
* | | *---------------------------------------------------> RW
* | *-------------------------------------------------------> R/W1C
* *-----------------------------------------------------------> R/W1C
* .------------------------------------------------------------.
* |LTC|LRF|LVF|DAC|DAU|DRC|DRU|DSC|DSU|VEC|VEU|LVC| RSVD1 |SYND|
* `------------------------------------------------------------'
* 45 44 43 42 41 40 39 38 37 36 35 34 33:28 27:0
* ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
* | | | | | | | | | | | | | |
* *---*---*---*---*----*---*---*---*---*---*---* | *-> RW
* *-------------------------------------> R/W1C
DBGERRTRAP( lprintf(sp
->gid
, "ERROR_TRAP_GEN: access to l2_b%d_esr. returning val 0x%llx\n", bank
, reg
););
* synchronize the read/modify/write
pthread_mutex_lock(&rpp
->ss_err_state
.err_lock
);
val
= store_val
& ( MASK64(63,62)|MASK64(53,34) ); if (!(reg
& ( MASK64(63,62)|MASK64(53,34) ))){
/* make sure MODA bit is off */
l2p
->error_status
[bank
] = reg
;DBGERRTRAP( lprintf(sp
->gid
, "ERROR_TRAP_GEN: access to l2_b%d_esr. storing val 0x%llx\n", bank
, reg
););
pthread_mutex_unlock(&rpp
->ss_err_state
.err_lock
);
return 0; /* ignored for store operations */
EIR_DEFINITION( l2_b0_esr
) {
return (l2_esr_inject(0, sp
, mask
, errp
));
EIR_DEFINITION( l2_b1_esr
) {
return (l2_esr_inject(1, sp
, mask
, errp
));
EIR_DEFINITION( l2_b2_esr
) {
return (l2_esr_inject(2, sp
, mask
, errp
));
EIR_DEFINITION( l2_b3_esr
) {
return (l2_esr_inject(3, sp
, mask
, errp
));
EIR_DEFINITION( l2_b4_esr
) {
return (l2_esr_inject(4, sp
, mask
, errp
));
EIR_DEFINITION( l2_b5_esr
) {
return (l2_esr_inject(5, sp
, mask
, errp
));
EIR_DEFINITION( l2_b6_esr
) {
return (l2_esr_inject(6, sp
, mask
, errp
));
EIR_DEFINITION( l2_b7_esr
) {
return (l2_esr_inject(7, sp
, mask
, errp
));
bool_t
l2_esr_inject (int bank
, EIR_ARGS
) { bool_t new_trap
, is_ready
; rpp
= (ss_proc_t
*)(sp
->config_procp
->procp
); v9p
= (sparcv9_cpu_t
*)(sp
->specificp
); rsp
= v9p
->impl_specificp
; err_string
= errp
->error_status
.err_inject_name
; pthread_mutex_lock(&rpp
->ss_err_state
.err_lock
);
reg
= l2p
->error_status
[bank
]; lprintf(sp
->gid
, "ERROR_TRAP_GEN: injecting l2_b%d_esr. old value 0x%llx\n", bank
, reg
);
* See Register diagram in the register
* access routine for l2_esr.
if (mask
& CE_MASK
) { /* Correctable Error */
if (l2_esr_access (bank
, sp
, ASI_NA
, ADDR_NA
, true, 0, true) & MASK64(36,36)) {
/* VEC bit is already set in l2_esr
* Inject the ESR bit(s) specified
* and update the VEC bit.
/* make sure VEC bit is on */
if (strncmp(sp
->eep
->error_str
, "MAL2C_", 6) == 0)
reg
|= MASK64(60,60); /* Set the MODA bit */ lprintf(sp
->gid
, "ERROR_TRAP_GEN: injecting l2_b%d_esr. new value 0x%llx\n", bank
, reg
);
l2p
->error_status
[bank
] = reg
; /* This error will be forwarded to the core and the error name
* defined by error_inject_name field of this error_entry will be
* injected into the core. The core error injection code will try
* to grab this lock so releasing it here before injecting core error
pthread_mutex_unlock(&rpp
->ss_err_state
.err_lock
);
* Checking L2_eer to see if CEEN is set
if (l2_eer_access(bank
, sp
, ASI_NA
, ADDR_NA
, true, 0, true) & MASK64(0,0)){
* The hw correctable L2$ error are posted as L2C disrupting traps
lprintf(sp
->gid
, "ERROR_TRAP_GEN: This L2$ error in l2_b%d_esr is actually posted as %s error trap\n", bank
, err_string
);
ss_inject_error_trap(sp
, err_string
, 0, 0);
* The trap has already been posted as L2C error trap.
* Hence setting new_trap to false
lprintf(sp
->gid
, "ERROR_TRAP_GEN: CEEN in L2 Error Enable Register is %s\n",
is_ready
? "ON" : "OFF" ); } else { /*Uncorrectable Error*/
if (l2_esr_access (bank
, sp
, ASI_NA
, ADDR_NA
, true, 0, true) & MASK64(35,35)) {
/* VEU bit is already set in l2_esr
* Inject the ESR bit(s) specified
* and update the VEU bit.
/* make sure VEU bit is on */
if (strncmp(sp
->eep
->error_str
, "MAL2U_", 6) == 0)
reg
|= MASK64(60,60); /* Set the MODA bit */ lprintf(sp
->gid
, "ERROR_TRAP_GEN: injecting l2_b%d_esr. new value 0x%llx\n", bank
, reg
);
l2p
->error_status
[bank
] = reg
; /* This error will be forwarded to the core and the error name
* defined by error_inject_name field of this error_entry will be
* injected into the core. The core error injection code will try
* to grab this lock so releasing it here before injecting core error
pthread_mutex_unlock(&rpp
->ss_err_state
.err_lock
);
* Checking L2_eer to see if NCEEN is set
if (l2_eer_access(bank
, sp
, ASI_NA
, ADDR_NA
, true, 0, true) & MASK64(1,1)){
* The hw uncorrectable L2$ error are posted as precise traps
lprintf(sp
->gid
, "ERROR_TRAP_GEN: This L2$ error in l2_b%d_esr is actually posted as %s error trap\n", bank
, err_string
);
ss_inject_error_trap(sp
, err_string
, 0, 0);
* The trap has already been posted as L2C error trap.
* Hence setting new_trap to false
lprintf(sp
->gid
, "ERROR_TRAP_GEN: NCEEN in L2 Error Enable Register is %s\n",
is_ready
? "ON" : "OFF" ); * One register per l2$ bank (8 total)
* we define separate access routines.
EAR_DEFINITION( l2_b0_eer
) {
return (l2_eer_access(0, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2_b1_eer
) {
return (l2_eer_access(1, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2_b2_eer
) {
return (l2_eer_access(2, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2_b3_eer
) {
return (l2_eer_access(3, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2_b4_eer
) {
return (l2_eer_access(4, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2_b5_eer
) {
return (l2_eer_access(5, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2_b6_eer
) {
return (l2_eer_access(6, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2_b7_eer
) {
return (l2_eer_access(7, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
uint64_t l2_eer_access (int bank
, EAR_ARGS
) {
rpp
= (ss_proc_t
*)(sp
->config_procp
->procp
); v9p
= (sparcv9_cpu_t
*)(sp
->specificp
); rsp
= v9p
->impl_specificp
; reg
= l2p
->error_enable
[bank
];DBGERRTRAP( lprintf(sp
->gid
, "ERROR_TRAP_GEN: access to l2_b%d_eer. returning val 0x%llx\n", bank
, reg
););
reg
= store_val
& MASK64(2,0);DBGERRTRAP( lprintf(sp
->gid
, "ERROR_TRAP_GEN: access to l2_b%d_eer. storing val 0x%llx\n", bank
, reg
););
return 0; /* ignored for store operations */
* L2 notdata registers, one per l2$ bank (8 total)
* we define separate access routines.
EAR_DEFINITION( l2nd_b0_esr
) {
return (l2nd_esr_access(0, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2nd_b1_esr
) {
return (l2nd_esr_access(1, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2nd_b2_esr
) {
return (l2_esr_access(2, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2nd_b3_esr
) {
return (l2nd_esr_access(3, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2nd_b4_esr
) {
return (l2nd_esr_access(4, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2nd_b5_esr
) {
return (l2nd_esr_access(5, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2nd_b6_esr
) {
return (l2nd_esr_access(6, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( l2nd_b7_esr
) {
return (l2nd_esr_access(7, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
uint64_t l2nd_esr_access (int bank
, EAR_ARGS
) {
rpp
= (ss_proc_t
*)(sp
->config_procp
->procp
); v9p
= (sparcv9_cpu_t
*)(sp
->specificp
); rsp
= v9p
->impl_specificp
; reg
= l2p
->error_notdata
[bank
]; * .-------------------------------------------------------------.
* | RESERVED |MEND|RW|NDSP|NDDM| RSVD | VCID | ADDRESS | RSVD |
* `-------------------------------------------------------------'
* 63:52 51 50 49 48 47:46 45:40 39:4 3:0
* | | | *----* | *---------* *---> RO
* | | | | | *---------------> RW
* | | | | *----------------------------> RO
* | | | *-------------------------------------> R/W1C
* | | *-------------------------------------------> RW
* | *-----------------------------------------------> R/W1C
* *-------------------------------------------------------> RO
DBGERRTRAP( lprintf(sp
->gid
, "ERROR_TRAP_GEN: access to l2nd_b%d_esr. returning val 0x%llx\n", bank
, reg
););
* synchronize the read/modify/write
pthread_mutex_lock(&rpp
->ss_err_state
.err_lock
);
val
= store_val
& ( MASK64(51,51)|MASK64(49,48) ); l2p
->error_notdata
[bank
] = reg
;DBGERRTRAP( lprintf(sp
->gid
, "ERROR_TRAP_GEN: access to l2nd_b%d_esr. storing val 0x%llx\n", bank
, reg
););
pthread_mutex_unlock(&rpp
->ss_err_state
.err_lock
);
return 0; /* ignored for store operations */
EIR_DEFINITION( l2nd_b0_esr
) {
return (l2nd_esr_inject(0, sp
, mask
, errp
));
EIR_DEFINITION( l2nd_b1_esr
) {
return (l2nd_esr_inject(1, sp
, mask
, errp
));
EIR_DEFINITION( l2nd_b2_esr
) {
return (l2nd_esr_inject(2, sp
, mask
, errp
));
EIR_DEFINITION( l2nd_b3_esr
) {
return (l2nd_esr_inject(3, sp
, mask
, errp
));
EIR_DEFINITION( l2nd_b4_esr
) {
return (l2nd_esr_inject(4, sp
, mask
, errp
));
EIR_DEFINITION( l2nd_b5_esr
) {
return (l2nd_esr_inject(5, sp
, mask
, errp
));
EIR_DEFINITION( l2nd_b6_esr
) {
return (l2nd_esr_inject(6, sp
, mask
, errp
));
EIR_DEFINITION( l2nd_b7_esr
) {
return (l2nd_esr_inject(7, sp
, mask
, errp
));
bool_t
l2nd_esr_inject (int bank
, EIR_ARGS
) { bool_t new_trap
, is_ready
; rpp
= (ss_proc_t
*)(sp
->config_procp
->procp
); v9p
= (sparcv9_cpu_t
*)(sp
->specificp
); rsp
= v9p
->impl_specificp
; err_string
= errp
->error_status
.err_inject_name
; pthread_mutex_lock(&rpp
->ss_err_state
.err_lock
);
reg
= l2p
->error_notdata
[bank
]; lprintf(sp
->gid
, "ERROR_TRAP_GEN: injecting l2nd_b%d_esr. old value 0x%llx\n", bank
, reg
);
* See Register diagram in the register
* access routine for l2nd_esr.
if (l2_esr_access (bank
, sp
, ASI_NA
, ADDR_NA
, true, 0, true) & MASK64(49,48)) {
* Multiple Not Data errors, update the MEND bit
* Inject the ESR bit(s) specified
lprintf(sp
->gid
, "ERROR_TRAP_GEN: injecting l2nd_b%d_esr. new value 0x%llx\n", bank
, reg
);
l2p
->error_notdata
[bank
] = reg
; /* This error will be forwarded to the core and the error name
* defined by error_inject_name field of this error_entry will be
* injected into the core. The core error injection code will try
* to grab this lock so releasing it here before injecting core error
pthread_mutex_unlock(&rpp
->ss_err_state
.err_lock
);
* Checking L2_eer to see if NCEEN is set
if (l2_eer_access(bank
, sp
, ASI_NA
, ADDR_NA
, true, 0, true) & MASK64(1,1)){
lprintf(sp
->gid
, "ERROR_TRAP_GEN: This L2$ not data error in l2nd_b%d_esr is actually posted as %s error trap\n", bank
, err_string
);
ss_inject_error_trap(sp
, err_string
, 0, 0);
* The trap has already been posted.
* Hence setting new_trap to false
lprintf(sp
->gid
, "ERROR_TRAP_GEN: NCEEN in L2 Error Enable Register is %s\n",
is_ready
? "ON" : "OFF" ); * One register per dram channel(8 total)
* we define separate access routines.
EAR_DEFINITION( dram_b0_esr
) {
return (dram_esr_access(0, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( dram_b1_esr
) {
return (dram_esr_access(1, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( dram_b2_esr
) {
return (dram_esr_access(2, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
EAR_DEFINITION( dram_b3_esr
) {
return (dram_esr_access(3, sp
, asi
, addr
, is_load
, store_val
, legion_access
));
uint64_t dram_esr_access (int bank
, EAR_ARGS
) {
rpp
= (ss_proc_t
*)(sp
->config_procp
->procp
); v9p
= (sparcv9_cpu_t
*)(sp
->specificp
); rsp
= v9p
->impl_specificp
; reg
= mbankp
->error_status
; * .-------------------------------------------------------------------------.
* | MEU | MEC | DAC | DAU | DSC | DSU | DBU | MEB | FBU | FBR | RSVD | SYND |
* `-------------------------------------------------------------------------'
* 63 62 61 60 59 58 57 56 55 54 53:16 15:0
* ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
* | | | | | | | | | | | |
* *-----*-----*-----*-----*-----*-----*-----*-----*-----* | *----> RW
* *-----------------------------------------------> R/W1C
DBGERRTRAP( lprintf(sp
->gid
, "ERROR_TRAP_GEN: access to dram_b%d_esr. returning val 0x%llx\n", bank
, reg
););
* synchronize the read/modify/write
pthread_mutex_lock(&rpp
->ss_err_state
.err_lock
);
val
= store_val
& MASK64(63,54); mbankp
->error_status
= reg
;DBGERRTRAP( lprintf(sp
->gid
, "ERROR_TRAP_GEN: access to dram_b%d_esr. storing val 0x%llx\n", bank
, reg
););
pthread_mutex_unlock(&rpp
->ss_err_state
.err_lock
);
return 0; /* ignored for store operations */
EIR_DEFINITION( dram_b0_esr
) {
return (dram_esr_inject(0, sp
, mask
, errp
));
EIR_DEFINITION( dram_b1_esr
) {
return (dram_esr_inject(1, sp
, mask
, errp
));
EIR_DEFINITION( dram_b2_esr
) {
return (dram_esr_inject(2, sp
, mask
, errp
));
EIR_DEFINITION( dram_b3_esr
) {
return (dram_esr_inject(3, sp
, mask
, errp
));
bool_t
dram_esr_inject (int bank
, EIR_ARGS
) { uint64_t l2_esr_mask
; /* error bits to be set in L2$ ESR */
rpp
= (ss_proc_t
*)(sp
->config_procp
->procp
); v9p
= (sparcv9_cpu_t
*)(sp
->specificp
); rsp
= v9p
->impl_specificp
; mbankp
= &(rpp
->mbankp
[bank
]); pthread_mutex_lock(&rpp
->ss_err_state
.err_lock
);
reg
= mbankp
->error_status
; lprintf(sp
->gid
, "ERROR_TRAP_GEN: injecting dram_b%d_esr. old value 0x%llx\n", bank
, reg
);
* See Register diagram in the register
* access routine for dram_esr.
* Checking only for existing errors. See
if ((reg
& DRAM_DSU_bit
) | (reg
& DRAM_DAU_bit
) | (reg
& DRAM_FBU_bit
))
else if ((reg
& DRAM_DSC_bit
) | (reg
& DRAM_DAC_bit
) | (reg
& DRAM_FBR_bit
))
else /* existing error == DBU or no existing error */
if ((reg
& DRAM_DSU_bit
) | (reg
& DRAM_DAU_bit
) | (reg
& DRAM_FBU_bit
))
else /* existing error == (DBU | DSC | DAC | FBR) or no existing error */
if ((reg
& DRAM_DSU_bit
) | (reg
& DRAM_DAU_bit
) | (reg
& DRAM_FBU_bit
))
else if ((reg
& DRAM_DSC_bit
) | (reg
& DRAM_DAC_bit
) | (reg
& DRAM_FBR_bit
))
else /* existing error == DBU or no existing error */
if ((reg
& DRAM_DSU_bit
) | (reg
& DRAM_DAU_bit
) | (reg
& DRAM_FBU_bit
))
else /* existing error == (DBU | DSC | DAC | FBR) or no existing error */
else /* existing error == (DSU | DAU | FBU | DSC | DAC | FBR) or no existing error */
if ((reg
& DRAM_DSU_bit
) | (reg
& DRAM_DAU_bit
) | (reg
& DRAM_FBU_bit
))
else /* existing error == (DBU | DSC | DAC | FBR) or no existing error */
if ((reg
& DRAM_DSU_bit
) | (reg
& DRAM_DAU_bit
) | (reg
& DRAM_FBU_bit
))
else if ((reg
& DRAM_DSC_bit
) | (reg
& DRAM_DAC_bit
) | (reg
& DRAM_FBR_bit
))
else /* existing error == DBU or no existing error */
EXEC_WARNING( ("Invalid dram_b%d_esr mask = 0x%llx \n", bank
, mask
) );
lprintf(sp
->gid
, "ERROR_TRAP_GEN: injecting dram_b%d_esr. new value 0x%llx\n", bank
, reg
);
mbankp
->error_status
= reg
; /* The DRAM error info is also captured in the L2$ ESRs and ultimately
* presented to the core as L2C error (for correctable errors). The l2_esr_inject
* code will try to grab this lock so releasing it here.
pthread_mutex_unlock(&rpp
->ss_err_state
.err_lock
);
/* Mapping dram banks to the L2$ banks*/
err_name_len
= strlen(errp
->error_name
); l2_bank
= *(errp
->error_name
+ err_name_len
-1) -'0'; l2_esr_inject(l2_bank
, sp
, l2_esr_mask
, errp
);
* The trap has already been posted as L2C error trap.
* Hence setting new_trap to false
#endif /* } ERROR_TRAP_GEN */
bool_t
n2_sp_interrupt(simcpu_t
* sp
, uint64_t intr_level
, char * error_name
) { FIXME_WARNING(("SP interrupts not supported on Niagara2\n" \
"\terror name = %s, intr_level = %d\n",
error_name
, intr_level
));int no_niagara2_error_trap_gen
;
projects / OpenSPARC-T2-SAM / blob