Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / ras / bin / N2_RasState.py

# ========== Copyright Header Begin ==========================================
# 
# OpenSPARC T2 Processor File: N2_RasState.py
# Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
# 
# The above named program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
# 
# The above named program is distributed in the hope that it will be 
# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
# General Public License for more details.
# 
# You should have received a copy of the GNU General Public
# License along with this work; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
# 
# ========== Copyright Header End ============================================

import sys

from SS_State import *
from SS_Setup import *

setup = setups[sys.argv[1]]


n2_ras_regs=[

SS_RasCtrReg('N2','icache_addressing_fields',0,0,0,64,
  [
    ('rsvd0'	        , 0, 1,RO,0),
    ('instr'   		, 2, 4,RW,0),
    ('sets'   		, 5, 10,RW,0),
    ('tag'  		,11,39,RW,0),
  ],
  [ 'static const uint32_t ICACHE_WAYS = 8;\n'
    '    static const uint32_t N2_ICACHE_LINE_SIZE = 32'])
, SS_RasCtrReg('N2','icache_diag_tag_addr_fields',0,0,0,64,
  [
    ('rsvd0'     	, 0,5,RO,0),	
    ('index'		,6,11,RW,0), 
    ('way'		,12,14,RW,0), 
    ('vb_err_en	'	,15,15,RW,0), 
    ('perren'		,16,16,RW,0), 
  ]) 
, SS_RasCtrReg('N2','icache_instr_st_reg',0,0,0,64,
  [
    ('instr'		, 0, 31,RW,0),
    ('perrinj'		, 32,32,RW,0)
  ],
  [ 'static const uint32_t ICACHE_DATA_SIZE_MASK = 0x1ffffffff'])
, SS_RasCtrReg('N2','icache_tag_ld_reg',0,0,0,64,
  [
    ('valid0'		,0,0,RW,0),
    ('valid1'		,1,1,RW,0),
    ('tag'		,2,30,RW,0),
    ('tag_parity'	,31,31,RW,0),
  ],
  [ 'static const uint32_t ICACHE_TAG_SIZE_MASK = 0xffffffff'])
, SS_RasCtrReg('N2','icache_diag_instr_addr_fields',0,0,0,64,
  [
    ('rsvd0'	        , 0, 2,RO,0),
    ('word'		,3,5,RW,0),
    ('index'		,6,11,RW,0),
    ('way'		,12,14,RW,0),
  ])
, SS_RasCtrReg('N2','dcache_addressing_fields',0,0,0,64,
  [
    ('data'    		, 0,3,RW,0),	
    ('sets'      	,4,10,RW,0),
    ('tag'		,11,39,RW,0),
  ],['static const uint32_t DCACHE_WAYS = 4;\n' 
     '    static const uint32_t N2_DCACHE_LINE_SIZE = 16'])
, SS_RasCtrReg('N2','dcache_diag_data_st_addr_fields',0,0,0,64,
  [
    ('rsvd0'	        , 0, 2,RO,0),
    ('doubleword'	, 3, 3,RW,0),
    ('index'   		, 4, 10,RW,0),
    ('way'   		, 11, 12,RW,0),
    ('perrmask'		, 13, 20,RW,0),
  ])
, SS_RasCtrReg('N2','dcache_diag_data_ld_addr_fields',0,0,0,64,
  [
    ('rsvd0'	        , 0, 2,RO,0),
    ('doubleword'	, 3, 3,RW,0),
    ('index'   		, 4, 10,RW,0),
    ('way'   		, 11, 12,RW,0),
    ('data_notparity'	, 13, 13,RW,0),
  ])
, SS_RasCtrReg('N2','dcache_diag_tag_addr_fields',0,0,0,64,
  [
    ('rsvd0'	        , 0, 3,RO,0),
    ('index'    	, 4, 10,RW,0),
    ('way'   		, 11, 12,RW,0),
    ('perren'  		, 13, 13,RW,0),
    ('vb_err_en'	, 14, 14,RW,0),
  ])
, SS_RasCtrReg('N2','dcache_tag_ld_reg',0,0,0,64,
  [
    ('valid0'		,0,0,RW,0),
    ('valid1'		,1,1,RW,0),
    ('tag'		,2,30,RW,0),
    ('tag_parity'	,31,31,RW,0),
  ],
  [ 'static const uint32_t DCACHE_TAG_SIZE_MASK = 0xffffffff'])
, SS_RasCtrReg('N2','dcache_data_st_reg',0,0,0,64,
  [
    ('data'     	, 0, 63,RW,0),	
  ],
  [ 'static const uint64_t DCACHE_DATA_SIZE_MASK = 0xffffffffffffffff']) 
, SS_RasCtrReg('N2','stb_access_da_reg',0,0,0,64,
  [
    ('data'     	, 0, 63,RW,0),	
  ])
, SS_RasCtrReg('N2','stb_access_addr_fields',0,0,0,64,
  [
    ('rsvd0'		,0,2,RO,0),
    ('entry'		,3,5,RW,0),
    ('field'		,6,8,RW,0),
    ('rsvd1'	        ,9,63,RO,0),
  ],
  [ 'static const uint_t DATA_FIELD = 0;\n'
    '    static const uint_t ECC_FIELD = 1;\n'
    '    static const uint_t CNTRL_PARITY_FIELD = 2;\n'
    '    static const uint_t CAM_FIELD = 3;\n'
    '    static const uint_t STB_POINTER_FIELD = 4'])
, SS_RasCtrReg('N2','stb_access_cam_reg',0,0,0,64,
  [
    ('rsvd0'		,0,2,RO,0),
    ('pa'		,3,39,RW,0),
    ('bm_asi'		,40,47,RW,0),
    ('rsvd1'	        ,48,63,RO,0),
  ])
, SS_RasCtrReg('N2','stb_access_ctl_reg',0,0,0,64,
  [
    ('control'		,0,2,RW,0),
    ('c_p'		,3,3,RW,0),
    ('rsvd0'	        ,4,63,RO,0),
  ],
  [ 'const static uint_t CTL_USER = 0;\n'
    '    const static uint_t CTL_PRIV = 3;\n'
    '    const static uint_t CTL_HPRIV = 5'])
, SS_RasCtrReg('N2','stb_access_ecc_reg',0,0,0,64,
  [
    ('ecc_even'		,0,6,RW,0),
    ('ecc_odd'		,7,13,RW,0),
    ('rsvd0'	        ,14,63,RO,0),
  ])
]

h_file=open('%s' % sys.argv[2],'w')

h_base_name = sys.argv[2].split('/')[-1].split('.')[0]

h_file.write('#ifndef __'+h_base_name+'_h__\n')
h_file.write('#define __'+h_base_name+'_h__\n')
h_file.write('\n')
#h_file.write('#include "SS_AsiCtrReg.h"\n')
h_file.write('\n')

for reg in n2_ras_regs:
  reg.cpp(h_file)

h_file.write('\n')
h_file.write('#endif\n')
h_file.write('\n')

h_file.close()