# ========== Copyright Header Begin ==========================================
# OpenSPARC T2 Processor File: N2_RasState.py
# Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
# The above named program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
# The above named program is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
# You should have received a copy of the GNU General Public
# License along with this work; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
# ========== Copyright Header End ============================================
setup
= setups
[sys
.argv
[1]]
SS_RasCtrReg('N2','icache_addressing_fields',0,0,0,64,
[ 'static const uint32_t ICACHE_WAYS = 8;\n'
' static const uint32_t N2_ICACHE_LINE_SIZE = 32'])
, SS_RasCtrReg('N2','icache_diag_tag_addr_fields',0,0,0,64,
('vb_err_en ' ,15,15,RW
,0),
, SS_RasCtrReg('N2','icache_instr_st_reg',0,0,0,64,
[ 'static const uint32_t ICACHE_DATA_SIZE_MASK = 0x1ffffffff'])
, SS_RasCtrReg('N2','icache_tag_ld_reg',0,0,0,64,
('tag_parity' ,31,31,RW
,0),
[ 'static const uint32_t ICACHE_TAG_SIZE_MASK = 0xffffffff'])
, SS_RasCtrReg('N2','icache_diag_instr_addr_fields',0,0,0,64,
, SS_RasCtrReg('N2','dcache_addressing_fields',0,0,0,64,
],['static const uint32_t DCACHE_WAYS = 4;\n'
' static const uint32_t N2_DCACHE_LINE_SIZE = 16'])
, SS_RasCtrReg('N2','dcache_diag_data_st_addr_fields',0,0,0,64,
('doubleword' , 3, 3,RW
,0),
('perrmask' , 13, 20,RW
,0),
, SS_RasCtrReg('N2','dcache_diag_data_ld_addr_fields',0,0,0,64,
('doubleword' , 3, 3,RW
,0),
('data_notparity' , 13, 13,RW
,0),
, SS_RasCtrReg('N2','dcache_diag_tag_addr_fields',0,0,0,64,
('perren' , 13, 13,RW
,0),
('vb_err_en' , 14, 14,RW
,0),
, SS_RasCtrReg('N2','dcache_tag_ld_reg',0,0,0,64,
('tag_parity' ,31,31,RW
,0),
[ 'static const uint32_t DCACHE_TAG_SIZE_MASK = 0xffffffff'])
, SS_RasCtrReg('N2','dcache_data_st_reg',0,0,0,64,
[ 'static const uint64_t DCACHE_DATA_SIZE_MASK = 0xffffffffffffffff'])
, SS_RasCtrReg('N2','stb_access_da_reg',0,0,0,64,
, SS_RasCtrReg('N2','stb_access_addr_fields',0,0,0,64,
[ 'static const uint_t DATA_FIELD = 0;\n'
' static const uint_t ECC_FIELD = 1;\n'
' static const uint_t CNTRL_PARITY_FIELD = 2;\n'
' static const uint_t CAM_FIELD = 3;\n'
' static const uint_t STB_POINTER_FIELD = 4'])
, SS_RasCtrReg('N2','stb_access_cam_reg',0,0,0,64,
, SS_RasCtrReg('N2','stb_access_ctl_reg',0,0,0,64,
[ 'const static uint_t CTL_USER = 0;\n'
' const static uint_t CTL_PRIV = 3;\n'
' const static uint_t CTL_HPRIV = 5'])
, SS_RasCtrReg('N2','stb_access_ecc_reg',0,0,0,64,
h_file
=open('%s' % sys
.argv
[2],'w')
h_base_name
= sys
.argv
[2].split('/')[-1].split('.')[0]
h_file
.write('#ifndef __'+h_base_name
+'_h__\n')
h_file
.write('#define __'+h_base_name
+'_h__\n')
#h_file.write('#include "SS_AsiCtrReg.h"\n')