[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / lib / cpu / src / MemoryTransaction.h

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: MemoryTransaction.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* 
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* 
* The above named program is distributed in the hope that it will be 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
* 
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* 
* ========== Copyright Header End ============================================
*/
//============================================================================
// WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
//
// THIS FILE IS ONLY HERE FOR BACKWARDS COMPATIBILITY. DO NOT WRITE NEW CODE
// THAT DEPENDS ON THIS CLASS AND DO NOT ADD MORE CODE TO THIS CLASS HERE.
// THE ORIGINAL OF THIS FILE IS IN THE RIESLING REPOSITORY.
//============================================================================

#ifndef _MEMORYTRANSACTION_H__
#define _MEMORYTRANSACTION_H__

#include "SS_Types.h"

typedef SS_Vaddr VaddrT;
typedef SS_Paddr PaddrT;

class SS_Strand;

class MemoryTransaction {
 public:
    
    typedef enum { DATA, INSTR } RefT;

    enum Access_T
    { 
      READ               = 1 << 0,  // read access
      WRITE              = 1 << 1,  // write access
      ATOMIC             = 1 << 2,  // atomic instruction
      INTERNAL           = 1 << 3,  // internal read/write, allow access to RO/WO area
      TABLE_WALK         = 1 << 4,  // the memory transaction is generated by hardware table walk, rather then instruction fetch or LSU operation.
      NO_WRITE           = 1 << 5,  // do not overwrite data in the object
      MEM_SLAM           = 1 << 6,  // testbench slam a data into (read-only) memory section.
      FOLLOW_ME          = 1 << 7,  // indicate the value is a follow-me
      LITTLE_ENDIAN      = 1 << 8,  // data in little endian format
      NOP                = 1 << 9,  // silently ignore the read/write
      DEBUG              = 1 << 31  // last item, for debug purpose
    };
    
	typedef uint32_t AccessT;
        
	/**
	  * Default constructor
	  */
	MemoryTransaction()
         :
          strand( 0 ),
          size_( 0 ),
          ref_( DATA ),
          vaddr_( ~0x0 ),
          paddr_( ~0x0 )
        {}
	

        MemoryTransaction( VaddrT vaddr,AccessT a, uint_t id=0 )
         :
          strand(id),
          vaddr_(vaddr),
          paddr_(~0x0),
          ref_(DATA),
          access_(a),
          size_(0)
        {} 
        
	/**
	  * Copy constructor
	  * 
	  * @param orig The MemoryTransaction object to copy.
          */
	MemoryTransaction( const MemoryTransaction &orig )
         :
          strand( orig.strand ),
          vaddr_( orig.vaddr_ ),
          paddr_( orig.paddr_ ),
          ref_( orig.ref_ ),
          access_( orig.access_ ),
          size_( orig.size_ )
        {
          for (uint_t i = 0; i < ((size_ + 7) >> 3); i++)
            data_[i] = orig.data_[i];
        }

	/**
	  * Destructor
          */
	~MemoryTransaction()  {}


	/**
	  * Assignment operator
	  * 
	  * @param rhs The right hand side of the assignment operator.
          * @return The lvalue of the assignment.
          */
	const MemoryTransaction & operator=( const MemoryTransaction &rhs )
        {
          strand = rhs.strand;
          vaddr_ = rhs.vaddr_;
          paddr_ = rhs.paddr_;
          ref_ = rhs.ref_;
          access_ = rhs.access_;
          size_ = rhs.size_;

          for (uint_t i = 0; i < ((size_ + 7) >> 3); i++)
            data_[i] = rhs.data_[i];
          return *this;
        }

	/**
	  * Return a string representation of this MemoryTransaction object. 
          */
#if 0
	std::string toString() const{
	    ostringstream os;

            os << "reference type:    " << ( ref_ == DATA ? "data" : "instruction" ) << "\n";
            os << "access type:       " << ( access_ == READ ? "read" : "write" ) << "\n";
            os << "virtual addr:    0x" << RIESLING_VADDR_FORMAT << vaddr_ << "\n";
            os << "physical addr:   0x" << RIESLING_VADDR_FORMAT << paddr_ << "\n";
            os << "data:            ";
            for( uint_t i = 0; i < ((size_ + 7) >> 3); i++)
	        os  << "0x" << data_[i] << " ";

            os << "\n";
            return os.str();
	}
#endif

	/**
	  * Return the virtual address of the transaction
	  */
	VaddrT vaddr() const                        { return vaddr_; }
	VaddrT getVaddr() const { return vaddr_; }

	/**
	  * Set the virtual address of the transaction
	  */
	void vaddr( VaddrT va )                     { vaddr_ = va; }

	/**
	  * Return the physical address of the transaction
	  */
	PaddrT paddr() const                        { return paddr_; }
	PaddrT getPaddr() const { return paddr_; }

	/**
	  * Set the physcial address of the transaction
	  */
        void paddr( PaddrT pa )                     { paddr_ = pa; }


	/**
	  * Return the type of the transaction, either DATA or INSTR
	  */
	RefT referenceType() const                  { return ref_; }
	RefT getReferenceType() const { return ref_; }

	/**
	  * Set the type of the transaction, either DATA or INSTR
	  */
	void referenceType( RefT r )                { ref_ = r; }


	/**
	  * Set access characteristics of the transaction.  
	  * 
	  * @param val The value of the access word.  The following values can be
	  * ored into the access word:  
	  * READ     - a read transaction
	  * WRITE    - a write transaction
	  * INTERNAL - an internal transaction mean that the transaction may
	  *            not be subject to some MMU checks
	  * REVERSE_BYTE_ORDER
	  *
	  */
	void reset_access()			    { access_ = 0; }
	void access( AccessT val )
        {
          assert((val & (READ|WRITE)) && (val & (READ|WRITE)) != (READ|WRITE));
          access_ = val;
        }
	AccessT access() const                      { return access_; }
	AccessT getAccess() const { return access_; }

	void size( uint_t s )                       { size_ = s; }
	uint8_t size() const                        { return size_; }

	uint64_t getData ( uint_t dword = 0 ) const { return data_[dword]; }
        
	void     setData( uint_t dword, uint64_t data )         { data_[dword] = data; }
	void     setData( uint64_t data )                       { data_[0] = data; }
	void     setData( uint64_t *data )                       { 
	  data_[0] = data[0];
	  data_[1] = data[1];
	  data_[2] = data[2];
	  data_[3] = data[3];
	  data_[4] = data[4];
	  data_[5] = data[5];
	  data_[6] = data[6];
	  data_[7] = data[7];
	}

	bool readXact() const                     { return access_ & READ; }
	bool writeXact() const                    { return access_ & WRITE; }
	bool internalXact() const                 { return access_ & INTERNAL; }
	bool memSlamXact() const                 { return access_ & MEM_SLAM; }
	bool debugXact() const                     { return access_ & DEBUG; }
	bool tablewalk() const                    { return access_ & TABLE_WALK; }
	bool noWriteXact() const { return access_ & NO_WRITE; }
	bool followmeXact() const { return access_ & FOLLOW_ME; }
	bool atomicXact() const { return access_ & ATOMIC; }
	bool noOperationXact() const              { return access_ & NOP; }


        void setStrand( uint_t id )       { strand = id; }
	uint_t getStrand()           const    { return strand; }
          	
	
    protected:
	uint_t                  strand;               // The strand that generated the transaction.
	VaddrT                  vaddr_;               // The virtual address of the access
	PaddrT                  paddr_;               // The physical address of the access
	RefT                    ref_;                 // DATA/INSTR access
	AccessT                 access_;              // READ/WRITE and other flags
	uint_t                  size_;                // The number of bytes this transaction is accessing
	uint64_t                data_[8];             // Largest request is 64 bytes
};
#endif /* __MEMORYTRANSACTION_H__ */
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: MemoryTransaction.h
	5	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	6	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
	7	*
	8	* The above named program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public
	10	* License version 2 as published by the Free Software Foundation.
	11	*
	12	* The above named program is distributed in the hope that it will be
	13	* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public
	18	* License along with this work; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
	20	*
	21	* ========== Copyright Header End ============================================
	22	*/
	23	//============================================================================
	24	// WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
	25	//
	26	// THIS FILE IS ONLY HERE FOR BACKWARDS COMPATIBILITY. DO NOT WRITE NEW CODE
	27	// THAT DEPENDS ON THIS CLASS AND DO NOT ADD MORE CODE TO THIS CLASS HERE.
	28	// THE ORIGINAL OF THIS FILE IS IN THE RIESLING REPOSITORY.
	29	//============================================================================
	30
	31	#ifndef _MEMORYTRANSACTION_H__
	32	#define _MEMORYTRANSACTION_H__
	33
	34	#include "SS_Types.h"
	35
	36	typedef SS_Vaddr VaddrT;
	37	typedef SS_Paddr PaddrT;
	38
	39	class SS_Strand;
	40
	41	class MemoryTransaction {
	42	public:
	43
	44	typedef enum { DATA, INSTR } RefT;
	45
	46	enum Access_T
	47	{
	48	READ = 1 << 0, // read access
	49	WRITE = 1 << 1, // write access
	50	ATOMIC = 1 << 2, // atomic instruction
	51	INTERNAL = 1 << 3, // internal read/write, allow access to RO/WO area
	52	TABLE_WALK = 1 << 4, // the memory transaction is generated by hardware table walk, rather then instruction fetch or LSU operation.
	53	NO_WRITE = 1 << 5, // do not overwrite data in the object
	54	MEM_SLAM = 1 << 6, // testbench slam a data into (read-only) memory section.
	55	FOLLOW_ME = 1 << 7, // indicate the value is a follow-me
	56	LITTLE_ENDIAN = 1 << 8, // data in little endian format
	57	NOP = 1 << 9, // silently ignore the read/write
	58	DEBUG = 1 << 31 // last item, for debug purpose
	59	};
	60
	61	typedef uint32_t AccessT;
	62
	63	/**
	64	* Default constructor
65	*/
66	MemoryTransaction()
67	:
68	strand( 0 ),
69	size_( 0 ),
70	ref_( DATA ),
71	vaddr_( ~0x0 ),
72	paddr_( ~0x0 )
73	{}
74
75
76	MemoryTransaction( VaddrT vaddr,AccessT a, uint_t id=0 )
77	:
78	strand(id),
79	vaddr_(vaddr),
80	paddr_(~0x0),
81	ref_(DATA),
82	access_(a),
83	size_(0)
84	{}
85
86	/**
87	* Copy constructor
88	*
89	* @param orig The MemoryTransaction object to copy.
90	*/
91	MemoryTransaction( const MemoryTransaction &orig )
92	:
93	strand( orig.strand ),
94	vaddr_( orig.vaddr_ ),
95	paddr_( orig.paddr_ ),
96	ref_( orig.ref_ ),
97	access_( orig.access_ ),
98	size_( orig.size_ )
99	{
100	for (uint_t i = 0; i < ((size_ + 7) >> 3); i++)
101	data_[i] = orig.data_[i];
102	}
103
104	/**
105	* Destructor
106	*/
107	~MemoryTransaction() {}
108
109
110	/**
111	* Assignment operator
112	*
113	* @param rhs The right hand side of the assignment operator.
114	* @return The lvalue of the assignment.
115	*/
116	const MemoryTransaction & operator=( const MemoryTransaction &rhs )
117	{
118	strand = rhs.strand;
119	vaddr_ = rhs.vaddr_;
120	paddr_ = rhs.paddr_;
121	ref_ = rhs.ref_;
122	access_ = rhs.access_;
123	size_ = rhs.size_;
124
125	for (uint_t i = 0; i < ((size_ + 7) >> 3); i++)
126	data_[i] = rhs.data_[i];
127	return *this;
128	}
129
130	/**
131	* Return a string representation of this MemoryTransaction object.
132	*/
133	#if 0
134	std::string toString() const{
135	ostringstream os;
136
137	os << "reference type: " << ( ref_ == DATA ? "data" : "instruction" ) << "\n";
138	os << "access type: " << ( access_ == READ ? "read" : "write" ) << "\n";
139	os << "virtual addr: 0x" << RIESLING_VADDR_FORMAT << vaddr_ << "\n";
140	os << "physical addr: 0x" << RIESLING_VADDR_FORMAT << paddr_ << "\n";
141	os << "data: ";
142	for( uint_t i = 0; i < ((size_ + 7) >> 3); i++)
143	os << "0x" << data_[i] << " ";
144
145	os << "\n";
146	return os.str();
147	}
148	#endif
149
150	/**
151	* Return the virtual address of the transaction
152	*/
153	VaddrT vaddr() const { return vaddr_; }
154	VaddrT getVaddr() const { return vaddr_; }
155
156	/**
157	* Set the virtual address of the transaction
158	*/
159	void vaddr( VaddrT va ) { vaddr_ = va; }
160
161	/**
162	* Return the physical address of the transaction
163	*/
164	PaddrT paddr() const { return paddr_; }
165	PaddrT getPaddr() const { return paddr_; }
166
167	/**
168	* Set the physcial address of the transaction
169	*/
170	void paddr( PaddrT pa ) { paddr_ = pa; }
171
172
173	/**
174	* Return the type of the transaction, either DATA or INSTR
175	*/
176	RefT referenceType() const { return ref_; }
177	RefT getReferenceType() const { return ref_; }
178
179	/**
180	* Set the type of the transaction, either DATA or INSTR
181	*/
182	void referenceType( RefT r ) { ref_ = r; }
183
184
185	/**
186	* Set access characteristics of the transaction.
187	*
188	* @param val The value of the access word. The following values can be
189	* ored into the access word:
190	* READ - a read transaction
191	* WRITE - a write transaction
192	* INTERNAL - an internal transaction mean that the transaction may
193	* not be subject to some MMU checks
194	* REVERSE_BYTE_ORDER
195	*
196	*/
197	void reset_access() { access_ = 0; }
198	void access( AccessT val )
199	{
200	assert((val & (READ\|WRITE)) && (val & (READ\|WRITE)) != (READ\|WRITE));
201	access_ = val;
202	}
203	AccessT access() const { return access_; }
204	AccessT getAccess() const { return access_; }
205
206	void size( uint_t s ) { size_ = s; }
207	uint8_t size() const { return size_; }
208
209	uint64_t getData ( uint_t dword = 0 ) const { return data_[dword]; }
210
211	void setData( uint_t dword, uint64_t data ) { data_[dword] = data; }
212	void setData( uint64_t data ) { data_[0] = data; }
213	void setData( uint64_t *data ) {
214	data_[0] = data[0];
215	data_[1] = data[1];
216	data_[2] = data[2];
217	data_[3] = data[3];
218	data_[4] = data[4];
219	data_[5] = data[5];
220	data_[6] = data[6];
221	data_[7] = data[7];
222	}
223
224	bool readXact() const { return access_ & READ; }
225	bool writeXact() const { return access_ & WRITE; }
226	bool internalXact() const { return access_ & INTERNAL; }
227	bool memSlamXact() const { return access_ & MEM_SLAM; }
228	bool debugXact() const { return access_ & DEBUG; }
229	bool tablewalk() const { return access_ & TABLE_WALK; }
230	bool noWriteXact() const { return access_ & NO_WRITE; }
231	bool followmeXact() const { return access_ & FOLLOW_ME; }
232	bool atomicXact() const { return access_ & ATOMIC; }
233	bool noOperationXact() const { return access_ & NOP; }
234
235
236	void setStrand( uint_t id ) { strand = id; }
237	uint_t getStrand() const { return strand; }
238
239
240	protected:
241	uint_t strand; // The strand that generated the transaction.
242	VaddrT vaddr_; // The virtual address of the access
243	PaddrT paddr_; // The physical address of the access
244	RefT ref_; // DATA/INSTR access
245	AccessT access_; // READ/WRITE and other flags
246	uint_t size_; // The number of bytes this transaction is accessing
247	uint64_t data_[8]; // Largest request is 64 bytes
248	};
249	#endif /* __MEMORYTRANSACTION_H__ */
250